1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright 2021-2024 NXP 4 * 5 * Authors: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com> 6 * Ciprian Costea <ciprianmarian.costea@nxp.com> 7 * Andra-Teodora Ilie <andra.ilie@nxp.com> 8 */ 9 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11 12/ { 13 compatible = "nxp,s32g3"; 14 interrupt-parent = <&gic>; 15 #address-cells = <0x02>; 16 #size-cells = <0x02>; 17 18 cpus { 19 #address-cells = <1>; 20 #size-cells = <0>; 21 22 cpu-map { 23 cluster0 { 24 core0 { 25 cpu = <&cpu0>; 26 }; 27 28 core1 { 29 cpu = <&cpu1>; 30 }; 31 32 core2 { 33 cpu = <&cpu2>; 34 }; 35 36 core3 { 37 cpu = <&cpu3>; 38 }; 39 }; 40 41 cluster1 { 42 core0 { 43 cpu = <&cpu4>; 44 }; 45 46 core1 { 47 cpu = <&cpu5>; 48 }; 49 50 core2 { 51 cpu = <&cpu6>; 52 }; 53 54 core3 { 55 cpu = <&cpu7>; 56 }; 57 }; 58 }; 59 60 cpu0: cpu@0 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a53"; 63 reg = <0x0>; 64 enable-method = "psci"; 65 clocks = <&dfs 0>; 66 }; 67 68 cpu1: cpu@1 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a53"; 71 reg = <0x1>; 72 enable-method = "psci"; 73 clocks = <&dfs 0>; 74 }; 75 76 cpu2: cpu@2 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a53"; 79 reg = <0x2>; 80 enable-method = "psci"; 81 clocks = <&dfs 0>; 82 }; 83 84 cpu3: cpu@3 { 85 device_type = "cpu"; 86 compatible = "arm,cortex-a53"; 87 reg = <0x3>; 88 enable-method = "psci"; 89 clocks = <&dfs 0>; 90 }; 91 92 cpu4: cpu@100 { 93 device_type = "cpu"; 94 compatible = "arm,cortex-a53"; 95 reg = <0x100>; 96 enable-method = "psci"; 97 clocks = <&dfs 0>; 98 }; 99 100 cpu5: cpu@101 { 101 device_type = "cpu"; 102 compatible = "arm,cortex-a53"; 103 reg = <0x101>; 104 enable-method = "psci"; 105 clocks = <&dfs 0>; 106 }; 107 108 cpu6: cpu@102 { 109 device_type = "cpu"; 110 compatible = "arm,cortex-a53"; 111 reg = <0x102>; 112 enable-method = "psci"; 113 clocks = <&dfs 0>; 114 }; 115 116 cpu7: cpu@103 { 117 device_type = "cpu"; 118 compatible = "arm,cortex-a53"; 119 reg = <0x103>; 120 enable-method = "psci"; 121 clocks = <&dfs 0>; 122 }; 123 }; 124 125 firmware { 126 scmi: scmi { 127 compatible = "arm,scmi-smc"; 128 shmem = <&scmi_shmem>; 129 arm,smc-id = <0xc20000fe>; 130 #address-cells = <1>; 131 #size-cells = <0>; 132 133 dfs: protocol@13 { 134 reg = <0x13>; 135 #clock-cells = <1>; 136 }; 137 138 clks: protocol@14 { 139 reg = <0x14>; 140 #clock-cells = <1>; 141 }; 142 }; 143 144 psci: psci { 145 compatible = "arm,psci-1.0"; 146 method = "smc"; 147 }; 148 }; 149 150 151 pmu { 152 compatible = "arm,cortex-a53-pmu"; 153 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 154 }; 155 156 reserved-memory { 157 #address-cells = <2>; 158 #size-cells = <2>; 159 ranges; 160 161 scmi_shmem: shm@d0000000 { 162 compatible = "arm,scmi-shmem"; 163 reg = <0x0 0xd0000000 0x0 0x80>; 164 no-map; 165 }; 166 }; 167 168 soc@0 { 169 compatible = "simple-bus"; 170 #address-cells = <1>; 171 #size-cells = <1>; 172 ranges = <0 0 0 0x80000000>; 173 174 pinctrl: pinctrl@4009c240 { 175 compatible = "nxp,s32g2-siul2-pinctrl"; 176 /* MSCR0-MSCR101 registers on siul2_0 */ 177 reg = <0x4009c240 0x198>, 178 /* MSCR112-MSCR122 registers on siul2_1 */ 179 <0x44010400 0x2c>, 180 /* MSCR144-MSCR190 registers on siul2_1 */ 181 <0x44010480 0xbc>, 182 /* IMCR0-IMCR83 registers on siul2_0 */ 183 <0x4009ca40 0x150>, 184 /* IMCR119-IMCR397 registers on siul2_1 */ 185 <0x44010c1c 0x45c>, 186 /* IMCR430-IMCR495 registers on siul2_1 */ 187 <0x440110f8 0x108>; 188 189 jtag_pins: jtag-pins { 190 jtag-grp0 { 191 pinmux = <0x0>; 192 input-enable; 193 bias-pull-up; 194 slew-rate = <166>; 195 }; 196 197 jtag-grp1 { 198 pinmux = <0x11>; 199 slew-rate = <166>; 200 }; 201 202 jtag-grp2 { 203 pinmux = <0x40>; 204 input-enable; 205 bias-pull-down; 206 slew-rate = <166>; 207 }; 208 209 jtag-grp3 { 210 pinmux = <0x23c0>, 211 <0x23d0>, 212 <0x2320>; 213 }; 214 215 jtag-grp4 { 216 pinmux = <0x51>; 217 input-enable; 218 bias-pull-up; 219 slew-rate = <166>; 220 }; 221 }; 222 223 pinctrl_usdhc0: usdhc0grp-pins { 224 usdhc0-grp0 { 225 pinmux = <0x2e1>, 226 <0x381>; 227 output-enable; 228 bias-pull-down; 229 slew-rate = <150>; 230 }; 231 232 usdhc0-grp1 { 233 pinmux = <0x2f1>, 234 <0x301>, 235 <0x311>, 236 <0x321>, 237 <0x331>, 238 <0x341>, 239 <0x351>, 240 <0x361>, 241 <0x371>; 242 output-enable; 243 input-enable; 244 bias-pull-up; 245 slew-rate = <150>; 246 }; 247 248 usdhc0-grp2 { 249 pinmux = <0x391>; 250 output-enable; 251 slew-rate = <150>; 252 }; 253 254 usdhc0-grp3 { 255 pinmux = <0x3a0>; 256 input-enable; 257 slew-rate = <150>; 258 }; 259 260 usdhc0-grp4 { 261 pinmux = <0x2032>, 262 <0x2042>, 263 <0x2052>, 264 <0x2062>, 265 <0x2072>, 266 <0x2082>, 267 <0x2092>, 268 <0x20a2>, 269 <0x20b2>, 270 <0x20c2>; 271 }; 272 }; 273 274 pinctrl_usdhc0_100mhz: usdhc0-100mhzgrp-pins { 275 usdhc0-100mhz-grp0 { 276 pinmux = <0x2e1>, 277 <0x381>; 278 output-enable; 279 bias-pull-down; 280 slew-rate = <150>; 281 }; 282 283 usdhc0-100mhz-grp1 { 284 pinmux = <0x2f1>, 285 <0x301>, 286 <0x311>, 287 <0x321>, 288 <0x331>, 289 <0x341>, 290 <0x351>, 291 <0x361>, 292 <0x371>; 293 output-enable; 294 input-enable; 295 bias-pull-up; 296 slew-rate = <150>; 297 }; 298 299 usdhc0-100mhz-grp2 { 300 pinmux = <0x391>; 301 output-enable; 302 slew-rate = <150>; 303 }; 304 305 usdhc0-100mhz-grp3 { 306 pinmux = <0x3a0>; 307 input-enable; 308 slew-rate = <150>; 309 }; 310 311 usdhc0-100mhz-grp4 { 312 pinmux = <0x2032>, 313 <0x2042>, 314 <0x2052>, 315 <0x2062>, 316 <0x2072>, 317 <0x2082>, 318 <0x2092>, 319 <0x20a2>, 320 <0x20b2>, 321 <0x20c2>; 322 }; 323 }; 324 325 pinctrl_usdhc0_200mhz: usdhc0-200mhzgrp-pins { 326 usdhc0-200mhz-grp0 { 327 pinmux = <0x2e1>, 328 <0x381>; 329 output-enable; 330 bias-pull-down; 331 slew-rate = <208>; 332 }; 333 334 usdhc0-200mhz-grp1 { 335 pinmux = <0x2f1>, 336 <0x301>, 337 <0x311>, 338 <0x321>, 339 <0x331>, 340 <0x341>, 341 <0x351>, 342 <0x361>, 343 <0x371>; 344 output-enable; 345 input-enable; 346 bias-pull-up; 347 slew-rate = <208>; 348 }; 349 350 usdhc0-200mhz-grp2 { 351 pinmux = <0x391>; 352 output-enable; 353 slew-rate = <208>; 354 }; 355 356 usdhc0-200mhz-grp3 { 357 pinmux = <0x3a0>; 358 input-enable; 359 slew-rate = <208>; 360 }; 361 362 usdhc0-200mhz-grp4 { 363 pinmux = <0x2032>, 364 <0x2042>, 365 <0x2052>, 366 <0x2062>, 367 <0x2072>, 368 <0x2082>, 369 <0x2092>, 370 <0x20a2>, 371 <0x20b2>, 372 <0x20c2>; 373 }; 374 }; 375 }; 376 377 edma0: dma-controller@40144000 { 378 compatible = "nxp,s32g3-edma", "nxp,s32g2-edma"; 379 reg = <0x40144000 0x24000>, 380 <0x4012c000 0x3000>, 381 <0x40130000 0x3000>; 382 #dma-cells = <2>; 383 dma-channels = <32>; 384 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 385 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 386 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 387 interrupt-names = "tx-0-15", 388 "tx-16-31", 389 "err"; 390 clocks = <&clks 63>, <&clks 64>; 391 clock-names = "dmamux0", "dmamux1"; 392 }; 393 394 can0: can@401b4000 { 395 compatible = "nxp,s32g3-flexcan", 396 "nxp,s32g2-flexcan"; 397 reg = <0x401b4000 0xa000>; 398 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 399 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 400 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 401 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 402 interrupt-names = "mb-0", "state", "berr", "mb-1"; 403 clocks = <&clks 9>, <&clks 11>; 404 clock-names = "ipg", "per"; 405 status = "disabled"; 406 }; 407 408 can1: can@401be000 { 409 compatible = "nxp,s32g3-flexcan", 410 "nxp,s32g2-flexcan"; 411 reg = <0x401be000 0xa000>; 412 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 413 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 414 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 415 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 416 interrupt-names = "mb-0", "state", "berr", "mb-1"; 417 clocks = <&clks 9>, <&clks 11>; 418 clock-names = "ipg", "per"; 419 status = "disabled"; 420 }; 421 422 uart0: serial@401c8000 { 423 compatible = "nxp,s32g3-linflexuart", 424 "fsl,s32v234-linflexuart"; 425 reg = <0x401c8000 0x3000>; 426 interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>; 427 status = "disabled"; 428 }; 429 430 uart1: serial@401cc000 { 431 compatible = "nxp,s32g3-linflexuart", 432 "fsl,s32v234-linflexuart"; 433 reg = <0x401cc000 0x3000>; 434 interrupts = <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>; 435 status = "disabled"; 436 }; 437 438 i2c0: i2c@401e4000 { 439 compatible = "nxp,s32g3-i2c", 440 "nxp,s32g2-i2c"; 441 reg = <0x401e4000 0x1000>; 442 #address-cells = <1>; 443 #size-cells = <0>; 444 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 445 clocks = <&clks 40>; 446 clock-names = "ipg"; 447 status = "disabled"; 448 }; 449 450 i2c1: i2c@401e8000 { 451 compatible = "nxp,s32g3-i2c", 452 "nxp,s32g2-i2c"; 453 reg = <0x401e8000 0x1000>; 454 #address-cells = <1>; 455 #size-cells = <0>; 456 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 457 clocks = <&clks 40>; 458 clock-names = "ipg"; 459 status = "disabled"; 460 }; 461 462 i2c2: i2c@401ec000 { 463 compatible = "nxp,s32g3-i2c", 464 "nxp,s32g2-i2c"; 465 reg = <0x401ec000 0x1000>; 466 #address-cells = <1>; 467 #size-cells = <0>; 468 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 469 clocks = <&clks 40>; 470 clock-names = "ipg"; 471 status = "disabled"; 472 }; 473 474 edma1: dma-controller@40244000 { 475 compatible = "nxp,s32g3-edma", "nxp,s32g2-edma"; 476 reg = <0x40244000 0x24000>, 477 <0x4022c000 0x3000>, 478 <0x40230000 0x3000>; 479 #dma-cells = <2>; 480 dma-channels = <32>; 481 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 482 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 483 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 484 interrupt-names = "tx-0-15", 485 "tx-16-31", 486 "err"; 487 clocks = <&clks 63>, <&clks 64>; 488 clock-names = "dmamux0", "dmamux1"; 489 }; 490 491 can2: can@402a8000 { 492 compatible = "nxp,s32g3-flexcan", 493 "nxp,s32g2-flexcan"; 494 reg = <0x402a8000 0xa000>; 495 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 496 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 497 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 498 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 499 interrupt-names = "mb-0", "state", "berr", "mb-1"; 500 clocks = <&clks 9>, <&clks 11>; 501 clock-names = "ipg", "per"; 502 status = "disabled"; 503 }; 504 505 can3: can@402b2000 { 506 compatible = "nxp,s32g3-flexcan", 507 "nxp,s32g2-flexcan"; 508 reg = <0x402b2000 0xa000>; 509 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 513 interrupt-names = "mb-0", "state", "berr", "mb-1"; 514 clocks = <&clks 9>, <&clks 11>; 515 clock-names = "ipg", "per"; 516 status = "disabled"; 517 }; 518 519 uart2: serial@402bc000 { 520 compatible = "nxp,s32g3-linflexuart", 521 "fsl,s32v234-linflexuart"; 522 reg = <0x402bc000 0x3000>; 523 interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>; 524 status = "disabled"; 525 }; 526 527 i2c3: i2c@402d8000 { 528 compatible = "nxp,s32g3-i2c", 529 "nxp,s32g2-i2c"; 530 reg = <0x402d8000 0x1000>; 531 #address-cells = <1>; 532 #size-cells = <0>; 533 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 534 clocks = <&clks 40>; 535 clock-names = "ipg"; 536 status = "disabled"; 537 }; 538 539 i2c4: i2c@402dc000 { 540 compatible = "nxp,s32g3-i2c", 541 "nxp,s32g2-i2c"; 542 reg = <0x402dc000 0x1000>; 543 #address-cells = <1>; 544 #size-cells = <0>; 545 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 546 clocks = <&clks 40>; 547 clock-names = "ipg"; 548 status = "disabled"; 549 }; 550 551 usdhc0: mmc@402f0000 { 552 compatible = "nxp,s32g3-usdhc", 553 "nxp,s32g2-usdhc"; 554 reg = <0x402f0000 0x1000>; 555 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 556 clocks = <&clks 32>, 557 <&clks 31>, 558 <&clks 33>; 559 clock-names = "ipg", "ahb", "per"; 560 status = "disabled"; 561 }; 562 563 gic: interrupt-controller@50800000 { 564 compatible = "arm,gic-v3"; 565 #interrupt-cells = <3>; 566 interrupt-controller; 567 reg = <0x50800000 0x10000>, 568 <0x50900000 0x200000>, 569 <0x50400000 0x2000>, 570 <0x50410000 0x2000>, 571 <0x50420000 0x2000>; 572 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 573 }; 574 }; 575 576 timer { 577 compatible = "arm,armv8-timer"; 578 interrupt-parent = <&gic>; 579 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* sec-phys */ 580 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* phys */ 581 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* virt */ 582 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, /* hyp-phys */ 583 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; /* hyp-virt */ 584 arm,no-tick-in-suspend; 585 }; 586}; 587