1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * NXP S32G2 SoC family 4 * 5 * Copyright (c) 2021 SUSE LLC 6 * Copyright 2017-2021, 2024 NXP 7 */ 8 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 compatible = "nxp,s32g2"; 13 interrupt-parent = <&gic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 reserved-memory { 18 #address-cells = <2>; 19 #size-cells = <2>; 20 ranges; 21 22 scmi_buf: shm@d0000000 { 23 compatible = "arm,scmi-shmem"; 24 reg = <0x0 0xd0000000 0x0 0x80>; 25 no-map; 26 }; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 cpu0: cpu@0 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a53"; 36 reg = <0x0>; 37 enable-method = "psci"; 38 next-level-cache = <&cluster0_l2>; 39 }; 40 41 cpu1: cpu@1 { 42 device_type = "cpu"; 43 compatible = "arm,cortex-a53"; 44 reg = <0x1>; 45 enable-method = "psci"; 46 next-level-cache = <&cluster0_l2>; 47 }; 48 49 cpu2: cpu@100 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a53"; 52 reg = <0x100>; 53 enable-method = "psci"; 54 next-level-cache = <&cluster1_l2>; 55 }; 56 57 cpu3: cpu@101 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a53"; 60 reg = <0x101>; 61 enable-method = "psci"; 62 next-level-cache = <&cluster1_l2>; 63 }; 64 65 cluster0_l2: l2-cache0 { 66 compatible = "cache"; 67 cache-level = <2>; 68 cache-unified; 69 }; 70 71 cluster1_l2: l2-cache1 { 72 compatible = "cache"; 73 cache-level = <2>; 74 cache-unified; 75 }; 76 }; 77 78 pmu { 79 compatible = "arm,cortex-a53-pmu"; 80 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 81 }; 82 83 timer { 84 compatible = "arm,armv8-timer"; 85 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 86 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 87 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 88 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 89 }; 90 91 firmware { 92 scmi { 93 compatible = "arm,scmi-smc"; 94 arm,smc-id = <0xc20000fe>; 95 #address-cells = <1>; 96 #size-cells = <0>; 97 shmem = <&scmi_buf>; 98 99 clks: protocol@14 { 100 reg = <0x14>; 101 #clock-cells = <1>; 102 }; 103 }; 104 105 psci { 106 compatible = "arm,psci-1.0"; 107 method = "smc"; 108 }; 109 }; 110 111 soc@0 { 112 compatible = "simple-bus"; 113 #address-cells = <1>; 114 #size-cells = <1>; 115 ranges = <0 0 0 0x80000000>; 116 117 pinctrl: pinctrl@4009c240 { 118 compatible = "nxp,s32g2-siul2-pinctrl"; 119 /* MSCR0-MSCR101 registers on siul2_0 */ 120 reg = <0x4009c240 0x198>, 121 /* MSCR112-MSCR122 registers on siul2_1 */ 122 <0x44010400 0x2c>, 123 /* MSCR144-MSCR190 registers on siul2_1 */ 124 <0x44010480 0xbc>, 125 /* IMCR0-IMCR83 registers on siul2_0 */ 126 <0x4009ca40 0x150>, 127 /* IMCR119-IMCR397 registers on siul2_1 */ 128 <0x44010c1c 0x45c>, 129 /* IMCR430-IMCR495 registers on siul2_1 */ 130 <0x440110f8 0x108>; 131 132 jtag_pins: jtag-pins { 133 jtag-grp0 { 134 pinmux = <0x0>; 135 input-enable; 136 bias-pull-up; 137 slew-rate = <166>; 138 }; 139 140 jtag-grp1 { 141 pinmux = <0x11>; 142 slew-rate = <166>; 143 }; 144 145 jtag-grp2 { 146 pinmux = <0x40>; 147 input-enable; 148 bias-pull-down; 149 slew-rate = <166>; 150 }; 151 152 jtag-grp3 { 153 pinmux = <0x23c0>, 154 <0x23d0>, 155 <0x2320>; 156 }; 157 158 jtag-grp4 { 159 pinmux = <0x51>; 160 input-enable; 161 bias-pull-up; 162 slew-rate = <166>; 163 }; 164 }; 165 166 pinctrl_usdhc0: usdhc0grp-pins { 167 usdhc0-grp0 { 168 pinmux = <0x2e1>, 169 <0x381>; 170 output-enable; 171 bias-pull-down; 172 slew-rate = <150>; 173 }; 174 175 usdhc0-grp1 { 176 pinmux = <0x2f1>, 177 <0x301>, 178 <0x311>, 179 <0x321>, 180 <0x331>, 181 <0x341>, 182 <0x351>, 183 <0x361>, 184 <0x371>; 185 output-enable; 186 input-enable; 187 bias-pull-up; 188 slew-rate = <150>; 189 }; 190 191 usdhc0-grp2 { 192 pinmux = <0x391>; 193 output-enable; 194 slew-rate = <150>; 195 }; 196 197 usdhc0-grp3 { 198 pinmux = <0x3a0>; 199 input-enable; 200 slew-rate = <150>; 201 }; 202 203 usdhc0-grp4 { 204 pinmux = <0x2032>, 205 <0x2042>, 206 <0x2052>, 207 <0x2062>, 208 <0x2072>, 209 <0x2082>, 210 <0x2092>, 211 <0x20a2>, 212 <0x20b2>, 213 <0x20c2>; 214 }; 215 }; 216 217 pinctrl_usdhc0_100mhz: usdhc0-100mhzgrp-pins { 218 usdhc0-100mhz-grp0 { 219 pinmux = <0x2e1>, 220 <0x381>; 221 output-enable; 222 bias-pull-down; 223 slew-rate = <150>; 224 }; 225 226 usdhc0-100mhz-grp1 { 227 pinmux = <0x2f1>, 228 <0x301>, 229 <0x311>, 230 <0x321>, 231 <0x331>, 232 <0x341>, 233 <0x351>, 234 <0x361>, 235 <0x371>; 236 output-enable; 237 input-enable; 238 bias-pull-up; 239 slew-rate = <150>; 240 }; 241 242 usdhc0-100mhz-grp2 { 243 pinmux = <0x391>; 244 output-enable; 245 slew-rate = <150>; 246 }; 247 248 usdhc0-100mhz-grp3 { 249 pinmux = <0x3a0>; 250 input-enable; 251 slew-rate = <150>; 252 }; 253 254 usdhc0-100mhz-grp4 { 255 pinmux = <0x2032>, 256 <0x2042>, 257 <0x2052>, 258 <0x2062>, 259 <0x2072>, 260 <0x2082>, 261 <0x2092>, 262 <0x20a2>, 263 <0x20b2>, 264 <0x20c2>; 265 }; 266 }; 267 268 pinctrl_usdhc0_200mhz: usdhc0-200mhzgrp-pins { 269 usdhc0-200mhz-grp0 { 270 pinmux = <0x2e1>, 271 <0x381>; 272 output-enable; 273 bias-pull-down; 274 slew-rate = <208>; 275 }; 276 277 usdhc0-200mhz-grp1 { 278 pinmux = <0x2f1>, 279 <0x301>, 280 <0x311>, 281 <0x321>, 282 <0x331>, 283 <0x341>, 284 <0x351>, 285 <0x361>, 286 <0x371>; 287 output-enable; 288 input-enable; 289 bias-pull-up; 290 slew-rate = <208>; 291 }; 292 293 usdhc0-200mhz-grp2 { 294 pinmux = <0x391>; 295 output-enable; 296 slew-rate = <208>; 297 }; 298 299 usdhc0-200mhz-grp3 { 300 pinmux = <0x3a0>; 301 input-enable; 302 slew-rate = <208>; 303 }; 304 305 usdhc0-200mhz-grp4 { 306 pinmux = <0x2032>, 307 <0x2042>, 308 <0x2052>, 309 <0x2062>, 310 <0x2072>, 311 <0x2082>, 312 <0x2092>, 313 <0x20a2>, 314 <0x20b2>, 315 <0x20c2>; 316 }; 317 }; 318 }; 319 320 edma0: dma-controller@40144000 { 321 compatible = "nxp,s32g2-edma"; 322 reg = <0x40144000 0x24000>, 323 <0x4012c000 0x3000>, 324 <0x40130000 0x3000>; 325 #dma-cells = <2>; 326 dma-channels = <32>; 327 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 328 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 329 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 330 interrupt-names = "tx-0-15", 331 "tx-16-31", 332 "err"; 333 clocks = <&clks 63>, <&clks 64>; 334 clock-names = "dmamux0", "dmamux1"; 335 }; 336 337 can0: can@401b4000 { 338 compatible = "nxp,s32g2-flexcan"; 339 reg = <0x401b4000 0xa000>; 340 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 341 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 342 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 343 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 344 interrupt-names = "mb-0", "state", "berr", "mb-1"; 345 clocks = <&clks 9>, <&clks 11>; 346 clock-names = "ipg", "per"; 347 status = "disabled"; 348 }; 349 350 can1: can@401be000 { 351 compatible = "nxp,s32g2-flexcan"; 352 reg = <0x401be000 0xa000>; 353 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 354 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 355 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 356 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 357 interrupt-names = "mb-0", "state", "berr", "mb-1"; 358 clocks = <&clks 9>, <&clks 11>; 359 clock-names = "ipg", "per"; 360 status = "disabled"; 361 }; 362 363 uart0: serial@401c8000 { 364 compatible = "nxp,s32g2-linflexuart", 365 "fsl,s32v234-linflexuart"; 366 reg = <0x401c8000 0x3000>; 367 interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>; 368 status = "disabled"; 369 }; 370 371 uart1: serial@401cc000 { 372 compatible = "nxp,s32g2-linflexuart", 373 "fsl,s32v234-linflexuart"; 374 reg = <0x401cc000 0x3000>; 375 interrupts = <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>; 376 status = "disabled"; 377 }; 378 379 i2c0: i2c@401e4000 { 380 compatible = "nxp,s32g2-i2c"; 381 reg = <0x401e4000 0x1000>; 382 #address-cells = <1>; 383 #size-cells = <0>; 384 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 385 clocks = <&clks 40>; 386 clock-names = "ipg"; 387 status = "disabled"; 388 }; 389 390 i2c1: i2c@401e8000 { 391 compatible = "nxp,s32g2-i2c"; 392 reg = <0x401e8000 0x1000>; 393 #address-cells = <1>; 394 #size-cells = <0>; 395 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 396 clocks = <&clks 40>; 397 clock-names = "ipg"; 398 status = "disabled"; 399 }; 400 401 i2c2: i2c@401ec000 { 402 compatible = "nxp,s32g2-i2c"; 403 reg = <0x401ec000 0x1000>; 404 #address-cells = <1>; 405 #size-cells = <0>; 406 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 407 clocks = <&clks 40>; 408 clock-names = "ipg"; 409 status = "disabled"; 410 }; 411 412 edma1: dma-controller@40244000 { 413 compatible = "nxp,s32g2-edma"; 414 reg = <0x40244000 0x24000>, 415 <0x4022c000 0x3000>, 416 <0x40230000 0x3000>; 417 #dma-cells = <2>; 418 dma-channels = <32>; 419 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 420 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 421 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 422 interrupt-names = "tx-0-15", 423 "tx-16-31", 424 "err"; 425 clocks = <&clks 63>, <&clks 64>; 426 clock-names = "dmamux0", "dmamux1"; 427 }; 428 429 can2: can@402a8000 { 430 compatible = "nxp,s32g2-flexcan"; 431 reg = <0x402a8000 0xa000>; 432 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 433 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 434 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 435 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 436 interrupt-names = "mb-0", "state", "berr", "mb-1"; 437 clocks = <&clks 9>, <&clks 11>; 438 clock-names = "ipg", "per"; 439 status = "disabled"; 440 }; 441 442 can3: can@402b2000 { 443 compatible = "nxp,s32g2-flexcan"; 444 reg = <0x402b2000 0xa000>; 445 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 446 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 447 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 448 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 449 interrupt-names = "mb-0", "state", "berr", "mb-1"; 450 clocks = <&clks 9>, <&clks 11>; 451 clock-names = "ipg", "per"; 452 status = "disabled"; 453 }; 454 455 uart2: serial@402bc000 { 456 compatible = "nxp,s32g2-linflexuart", 457 "fsl,s32v234-linflexuart"; 458 reg = <0x402bc000 0x3000>; 459 interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>; 460 status = "disabled"; 461 }; 462 463 i2c3: i2c@402d8000 { 464 compatible = "nxp,s32g2-i2c"; 465 reg = <0x402d8000 0x1000>; 466 #address-cells = <1>; 467 #size-cells = <0>; 468 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 469 clocks = <&clks 40>; 470 clock-names = "ipg"; 471 status = "disabled"; 472 }; 473 474 i2c4: i2c@402dc000 { 475 compatible = "nxp,s32g2-i2c"; 476 reg = <0x402dc000 0x1000>; 477 #address-cells = <1>; 478 #size-cells = <0>; 479 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 480 clocks = <&clks 40>; 481 clock-names = "ipg"; 482 status = "disabled"; 483 }; 484 485 usdhc0: mmc@402f0000 { 486 compatible = "nxp,s32g2-usdhc"; 487 reg = <0x402f0000 0x1000>; 488 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 489 clocks = <&clks 32>, <&clks 31>, <&clks 33>; 490 clock-names = "ipg", "ahb", "per"; 491 bus-width = <8>; 492 status = "disabled"; 493 }; 494 495 gic: interrupt-controller@50800000 { 496 compatible = "arm,gic-v3"; 497 reg = <0x50800000 0x10000>, 498 <0x50880000 0x80000>, 499 <0x50400000 0x2000>, 500 <0x50410000 0x2000>, 501 <0x50420000 0x2000>; 502 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 503 interrupt-controller; 504 #interrupt-cells = <3>; 505 }; 506 }; 507}; 508