1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rk3568-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3568-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 gpio0 = &gpio0; 22 gpio1 = &gpio1; 23 gpio2 = &gpio2; 24 gpio3 = &gpio3; 25 gpio4 = &gpio4; 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 i2c4 = &i2c4; 31 i2c5 = &i2c5; 32 serial0 = &uart0; 33 serial1 = &uart1; 34 serial2 = &uart2; 35 serial3 = &uart3; 36 serial4 = &uart4; 37 serial5 = &uart5; 38 serial6 = &uart6; 39 serial7 = &uart7; 40 serial8 = &uart8; 41 serial9 = &uart9; 42 spi0 = &spi0; 43 spi1 = &spi1; 44 spi2 = &spi2; 45 spi3 = &spi3; 46 }; 47 48 cpus { 49 #address-cells = <2>; 50 #size-cells = <0>; 51 52 cpu0: cpu@0 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a55"; 55 reg = <0x0 0x0>; 56 clocks = <&scmi_clk 0>; 57 #cooling-cells = <2>; 58 enable-method = "psci"; 59 i-cache-size = <0x8000>; 60 i-cache-line-size = <64>; 61 i-cache-sets = <128>; 62 d-cache-size = <0x8000>; 63 d-cache-line-size = <64>; 64 d-cache-sets = <128>; 65 next-level-cache = <&l3_cache>; 66 }; 67 68 cpu1: cpu@100 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a55"; 71 reg = <0x0 0x100>; 72 #cooling-cells = <2>; 73 enable-method = "psci"; 74 i-cache-size = <0x8000>; 75 i-cache-line-size = <64>; 76 i-cache-sets = <128>; 77 d-cache-size = <0x8000>; 78 d-cache-line-size = <64>; 79 d-cache-sets = <128>; 80 next-level-cache = <&l3_cache>; 81 }; 82 83 cpu2: cpu@200 { 84 device_type = "cpu"; 85 compatible = "arm,cortex-a55"; 86 reg = <0x0 0x200>; 87 #cooling-cells = <2>; 88 enable-method = "psci"; 89 i-cache-size = <0x8000>; 90 i-cache-line-size = <64>; 91 i-cache-sets = <128>; 92 d-cache-size = <0x8000>; 93 d-cache-line-size = <64>; 94 d-cache-sets = <128>; 95 next-level-cache = <&l3_cache>; 96 }; 97 98 cpu3: cpu@300 { 99 device_type = "cpu"; 100 compatible = "arm,cortex-a55"; 101 reg = <0x0 0x300>; 102 #cooling-cells = <2>; 103 enable-method = "psci"; 104 i-cache-size = <0x8000>; 105 i-cache-line-size = <64>; 106 i-cache-sets = <128>; 107 d-cache-size = <0x8000>; 108 d-cache-line-size = <64>; 109 d-cache-sets = <128>; 110 next-level-cache = <&l3_cache>; 111 }; 112 }; 113 114 /* 115 * There are no private per-core L2 caches, but only the 116 * L3 cache that appears to the CPU cores as L2 caches 117 */ 118 l3_cache: l3-cache { 119 compatible = "cache"; 120 cache-level = <2>; 121 cache-unified; 122 cache-size = <0x80000>; 123 cache-line-size = <64>; 124 cache-sets = <512>; 125 }; 126 127 display_subsystem: display-subsystem { 128 compatible = "rockchip,display-subsystem"; 129 ports = <&vop_out>; 130 }; 131 132 firmware { 133 scmi: scmi { 134 compatible = "arm,scmi-smc"; 135 arm,smc-id = <0x82000010>; 136 shmem = <&scmi_shmem>; 137 #address-cells = <1>; 138 #size-cells = <0>; 139 140 scmi_clk: protocol@14 { 141 reg = <0x14>; 142 #clock-cells = <1>; 143 }; 144 }; 145 }; 146 147 hdmi_sound: hdmi-sound { 148 compatible = "simple-audio-card"; 149 simple-audio-card,name = "HDMI"; 150 simple-audio-card,format = "i2s"; 151 simple-audio-card,mclk-fs = <256>; 152 status = "disabled"; 153 154 simple-audio-card,codec { 155 sound-dai = <&hdmi>; 156 }; 157 158 simple-audio-card,cpu { 159 sound-dai = <&i2s0_8ch>; 160 }; 161 }; 162 163 pmu { 164 compatible = "arm,cortex-a55-pmu"; 165 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 168 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 169 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 170 }; 171 172 psci { 173 compatible = "arm,psci-1.0"; 174 method = "smc"; 175 }; 176 177 reserved-memory { 178 #address-cells = <2>; 179 #size-cells = <2>; 180 ranges; 181 182 scmi_shmem: shmem@10f000 { 183 compatible = "arm,scmi-shmem"; 184 reg = <0x0 0x0010f000 0x0 0x100>; 185 no-map; 186 }; 187 }; 188 189 timer { 190 compatible = "arm,armv8-timer"; 191 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 195 arm,no-tick-in-suspend; 196 }; 197 198 xin24m: xin24m { 199 compatible = "fixed-clock"; 200 clock-frequency = <24000000>; 201 clock-output-names = "xin24m"; 202 #clock-cells = <0>; 203 }; 204 205 xin32k: xin32k { 206 compatible = "fixed-clock"; 207 clock-frequency = <32768>; 208 clock-output-names = "xin32k"; 209 pinctrl-0 = <&clk32k_out0>; 210 pinctrl-names = "default"; 211 #clock-cells = <0>; 212 }; 213 214 sata1: sata@fc400000 { 215 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; 216 reg = <0 0xfc400000 0 0x1000>; 217 clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>, 218 <&cru CLK_SATA1_RXOOB>; 219 clock-names = "sata", "pmalive", "rxoob"; 220 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 221 phys = <&combphy1 PHY_TYPE_SATA>; 222 phy-names = "sata-phy"; 223 ports-implemented = <0x1>; 224 power-domains = <&power RK3568_PD_PIPE>; 225 status = "disabled"; 226 }; 227 228 sata2: sata@fc800000 { 229 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; 230 reg = <0 0xfc800000 0 0x1000>; 231 clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>, 232 <&cru CLK_SATA2_RXOOB>; 233 clock-names = "sata", "pmalive", "rxoob"; 234 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 235 phys = <&combphy2 PHY_TYPE_SATA>; 236 phy-names = "sata-phy"; 237 ports-implemented = <0x1>; 238 power-domains = <&power RK3568_PD_PIPE>; 239 status = "disabled"; 240 }; 241 242 usb_host0_xhci: usb@fcc00000 { 243 compatible = "rockchip,rk3568-dwc3", "snps,dwc3"; 244 reg = <0x0 0xfcc00000 0x0 0x400000>; 245 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 246 clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>, 247 <&cru ACLK_USB3OTG0>; 248 clock-names = "ref_clk", "suspend_clk", 249 "bus_clk"; 250 dr_mode = "otg"; 251 phy_type = "utmi_wide"; 252 power-domains = <&power RK3568_PD_PIPE>; 253 resets = <&cru SRST_USB3OTG0>; 254 snps,dis_u2_susphy_quirk; 255 status = "disabled"; 256 }; 257 258 usb_host1_xhci: usb@fd000000 { 259 compatible = "rockchip,rk3568-dwc3", "snps,dwc3"; 260 reg = <0x0 0xfd000000 0x0 0x400000>; 261 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 262 clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>, 263 <&cru ACLK_USB3OTG1>; 264 clock-names = "ref_clk", "suspend_clk", 265 "bus_clk"; 266 dr_mode = "host"; 267 phys = <&usb2phy0_host>, <&combphy1 PHY_TYPE_USB3>; 268 phy-names = "usb2-phy", "usb3-phy"; 269 phy_type = "utmi_wide"; 270 power-domains = <&power RK3568_PD_PIPE>; 271 resets = <&cru SRST_USB3OTG1>; 272 snps,dis_u2_susphy_quirk; 273 status = "disabled"; 274 }; 275 276 gic: interrupt-controller@fd400000 { 277 compatible = "arm,gic-v3"; 278 reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ 279 <0x0 0xfd460000 0 0x80000>; /* GICR */ 280 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 281 interrupt-controller; 282 #interrupt-cells = <3>; 283 mbi-alias = <0x0 0xfd410000>; 284 mbi-ranges = <296 24>; 285 msi-controller; 286 }; 287 288 usb_host0_ehci: usb@fd800000 { 289 compatible = "generic-ehci"; 290 reg = <0x0 0xfd800000 0x0 0x40000>; 291 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 292 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, 293 <&cru PCLK_USB>; 294 phys = <&usb2phy1_otg>; 295 phy-names = "usb"; 296 status = "disabled"; 297 }; 298 299 usb_host0_ohci: usb@fd840000 { 300 compatible = "generic-ohci"; 301 reg = <0x0 0xfd840000 0x0 0x40000>; 302 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 303 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, 304 <&cru PCLK_USB>; 305 phys = <&usb2phy1_otg>; 306 phy-names = "usb"; 307 status = "disabled"; 308 }; 309 310 usb_host1_ehci: usb@fd880000 { 311 compatible = "generic-ehci"; 312 reg = <0x0 0xfd880000 0x0 0x40000>; 313 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 314 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, 315 <&cru PCLK_USB>; 316 phys = <&usb2phy1_host>; 317 phy-names = "usb"; 318 status = "disabled"; 319 }; 320 321 usb_host1_ohci: usb@fd8c0000 { 322 compatible = "generic-ohci"; 323 reg = <0x0 0xfd8c0000 0x0 0x40000>; 324 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 325 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, 326 <&cru PCLK_USB>; 327 phys = <&usb2phy1_host>; 328 phy-names = "usb"; 329 status = "disabled"; 330 }; 331 332 pmugrf: syscon@fdc20000 { 333 compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd"; 334 reg = <0x0 0xfdc20000 0x0 0x10000>; 335 336 pmu_io_domains: io-domains { 337 compatible = "rockchip,rk3568-pmu-io-voltage-domain"; 338 status = "disabled"; 339 }; 340 }; 341 342 pipegrf: syscon@fdc50000 { 343 reg = <0x0 0xfdc50000 0x0 0x1000>; 344 }; 345 346 grf: syscon@fdc60000 { 347 compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; 348 reg = <0x0 0xfdc60000 0x0 0x10000>; 349 }; 350 351 pipe_phy_grf1: syscon@fdc80000 { 352 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; 353 reg = <0x0 0xfdc80000 0x0 0x1000>; 354 }; 355 356 pipe_phy_grf2: syscon@fdc90000 { 357 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; 358 reg = <0x0 0xfdc90000 0x0 0x1000>; 359 }; 360 361 usb2phy0_grf: syscon@fdca0000 { 362 compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; 363 reg = <0x0 0xfdca0000 0x0 0x8000>; 364 }; 365 366 usb2phy1_grf: syscon@fdca8000 { 367 compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; 368 reg = <0x0 0xfdca8000 0x0 0x8000>; 369 }; 370 371 pmucru: clock-controller@fdd00000 { 372 compatible = "rockchip,rk3568-pmucru"; 373 reg = <0x0 0xfdd00000 0x0 0x1000>; 374 #clock-cells = <1>; 375 #reset-cells = <1>; 376 }; 377 378 cru: clock-controller@fdd20000 { 379 compatible = "rockchip,rk3568-cru"; 380 reg = <0x0 0xfdd20000 0x0 0x1000>; 381 clocks = <&xin24m>; 382 clock-names = "xin24m"; 383 #clock-cells = <1>; 384 #reset-cells = <1>; 385 assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>; 386 assigned-clock-rates = <32768>, <1200000000>, <200000000>; 387 assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>; 388 rockchip,grf = <&grf>; 389 }; 390 391 i2c0: i2c@fdd40000 { 392 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 393 reg = <0x0 0xfdd40000 0x0 0x1000>; 394 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 395 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; 396 clock-names = "i2c", "pclk"; 397 pinctrl-0 = <&i2c0_xfer>; 398 pinctrl-names = "default"; 399 #address-cells = <1>; 400 #size-cells = <0>; 401 status = "disabled"; 402 }; 403 404 uart0: serial@fdd50000 { 405 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 406 reg = <0x0 0xfdd50000 0x0 0x100>; 407 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 408 clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>; 409 clock-names = "baudclk", "apb_pclk"; 410 dmas = <&dmac0 0>, <&dmac0 1>; 411 pinctrl-0 = <&uart0_xfer>; 412 pinctrl-names = "default"; 413 reg-io-width = <4>; 414 reg-shift = <2>; 415 status = "disabled"; 416 }; 417 418 pwm0: pwm@fdd70000 { 419 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 420 reg = <0x0 0xfdd70000 0x0 0x10>; 421 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 422 clock-names = "pwm", "pclk"; 423 pinctrl-0 = <&pwm0m0_pins>; 424 pinctrl-names = "default"; 425 #pwm-cells = <3>; 426 status = "disabled"; 427 }; 428 429 pwm1: pwm@fdd70010 { 430 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 431 reg = <0x0 0xfdd70010 0x0 0x10>; 432 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 433 clock-names = "pwm", "pclk"; 434 pinctrl-0 = <&pwm1m0_pins>; 435 pinctrl-names = "default"; 436 #pwm-cells = <3>; 437 status = "disabled"; 438 }; 439 440 pwm2: pwm@fdd70020 { 441 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 442 reg = <0x0 0xfdd70020 0x0 0x10>; 443 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 444 clock-names = "pwm", "pclk"; 445 pinctrl-0 = <&pwm2m0_pins>; 446 pinctrl-names = "default"; 447 #pwm-cells = <3>; 448 status = "disabled"; 449 }; 450 451 pwm3: pwm@fdd70030 { 452 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 453 reg = <0x0 0xfdd70030 0x0 0x10>; 454 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 455 clock-names = "pwm", "pclk"; 456 pinctrl-0 = <&pwm3_pins>; 457 pinctrl-names = "default"; 458 #pwm-cells = <3>; 459 status = "disabled"; 460 }; 461 462 pmu: power-management@fdd90000 { 463 compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd"; 464 reg = <0x0 0xfdd90000 0x0 0x1000>; 465 466 power: power-controller { 467 compatible = "rockchip,rk3568-power-controller"; 468 #power-domain-cells = <1>; 469 #address-cells = <1>; 470 #size-cells = <0>; 471 472 /* These power domains are grouped by VD_GPU */ 473 power-domain@RK3568_PD_GPU { 474 reg = <RK3568_PD_GPU>; 475 clocks = <&cru ACLK_GPU_PRE>, 476 <&cru PCLK_GPU_PRE>; 477 pm_qos = <&qos_gpu>; 478 #power-domain-cells = <0>; 479 }; 480 481 /* These power domains are grouped by VD_LOGIC */ 482 power-domain@RK3568_PD_VI { 483 reg = <RK3568_PD_VI>; 484 clocks = <&cru HCLK_VI>, 485 <&cru PCLK_VI>; 486 pm_qos = <&qos_isp>, 487 <&qos_vicap0>, 488 <&qos_vicap1>; 489 #power-domain-cells = <0>; 490 }; 491 492 power-domain@RK3568_PD_VO { 493 reg = <RK3568_PD_VO>; 494 clocks = <&cru HCLK_VO>, 495 <&cru PCLK_VO>, 496 <&cru ACLK_VOP_PRE>; 497 pm_qos = <&qos_hdcp>, 498 <&qos_vop_m0>, 499 <&qos_vop_m1>; 500 #power-domain-cells = <0>; 501 }; 502 503 power-domain@RK3568_PD_RGA { 504 reg = <RK3568_PD_RGA>; 505 clocks = <&cru HCLK_RGA_PRE>, 506 <&cru PCLK_RGA_PRE>; 507 pm_qos = <&qos_ebc>, 508 <&qos_iep>, 509 <&qos_jpeg_dec>, 510 <&qos_jpeg_enc>, 511 <&qos_rga_rd>, 512 <&qos_rga_wr>; 513 #power-domain-cells = <0>; 514 }; 515 516 power-domain@RK3568_PD_VPU { 517 reg = <RK3568_PD_VPU>; 518 clocks = <&cru HCLK_VPU_PRE>; 519 pm_qos = <&qos_vpu>; 520 #power-domain-cells = <0>; 521 }; 522 523 power-domain@RK3568_PD_RKVDEC { 524 clocks = <&cru HCLK_RKVDEC_PRE>; 525 reg = <RK3568_PD_RKVDEC>; 526 pm_qos = <&qos_rkvdec>; 527 #power-domain-cells = <0>; 528 }; 529 530 power-domain@RK3568_PD_RKVENC { 531 reg = <RK3568_PD_RKVENC>; 532 clocks = <&cru HCLK_RKVENC_PRE>; 533 pm_qos = <&qos_rkvenc_rd_m0>, 534 <&qos_rkvenc_rd_m1>, 535 <&qos_rkvenc_wr_m0>; 536 #power-domain-cells = <0>; 537 }; 538 }; 539 }; 540 541 gpu: gpu@fde60000 { 542 compatible = "rockchip,rk3568-mali", "arm,mali-bifrost"; 543 reg = <0x0 0xfde60000 0x0 0x4000>; 544 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 545 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 547 interrupt-names = "job", "mmu", "gpu"; 548 clocks = <&scmi_clk 1>, <&cru CLK_GPU>; 549 clock-names = "gpu", "bus"; 550 #cooling-cells = <2>; 551 power-domains = <&power RK3568_PD_GPU>; 552 status = "disabled"; 553 }; 554 555 vpu: video-codec@fdea0400 { 556 compatible = "rockchip,rk3568-vpu"; 557 reg = <0x0 0xfdea0000 0x0 0x800>; 558 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 559 interrupt-names = "vdpu"; 560 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 561 clock-names = "aclk", "hclk"; 562 iommus = <&vdpu_mmu>; 563 power-domains = <&power RK3568_PD_VPU>; 564 }; 565 566 vdpu_mmu: iommu@fdea0800 { 567 compatible = "rockchip,rk3568-iommu"; 568 reg = <0x0 0xfdea0800 0x0 0x40>; 569 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 570 clock-names = "aclk", "iface"; 571 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 572 power-domains = <&power RK3568_PD_VPU>; 573 #iommu-cells = <0>; 574 }; 575 576 rga: rga@fdeb0000 { 577 compatible = "rockchip,rk3568-rga", "rockchip,rk3288-rga"; 578 reg = <0x0 0xfdeb0000 0x0 0x180>; 579 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 580 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_RGA_CORE>; 581 clock-names = "aclk", "hclk", "sclk"; 582 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>; 583 reset-names = "core", "axi", "ahb"; 584 power-domains = <&power RK3568_PD_RGA>; 585 }; 586 587 vepu: video-codec@fdee0000 { 588 compatible = "rockchip,rk3568-vepu"; 589 reg = <0x0 0xfdee0000 0x0 0x800>; 590 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 591 clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>; 592 clock-names = "aclk", "hclk"; 593 iommus = <&vepu_mmu>; 594 power-domains = <&power RK3568_PD_RGA>; 595 }; 596 597 vepu_mmu: iommu@fdee0800 { 598 compatible = "rockchip,rk3568-iommu"; 599 reg = <0x0 0xfdee0800 0x0 0x40>; 600 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 601 clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>; 602 clock-names = "aclk", "iface"; 603 power-domains = <&power RK3568_PD_RGA>; 604 #iommu-cells = <0>; 605 }; 606 607 sdmmc2: mmc@fe000000 { 608 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; 609 reg = <0x0 0xfe000000 0x0 0x4000>; 610 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 611 clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>, 612 <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>; 613 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 614 fifo-depth = <0x100>; 615 max-frequency = <150000000>; 616 resets = <&cru SRST_SDMMC2>; 617 reset-names = "reset"; 618 status = "disabled"; 619 }; 620 621 gmac1: ethernet@fe010000 { 622 compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; 623 reg = <0x0 0xfe010000 0x0 0x10000>; 624 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 625 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 626 interrupt-names = "macirq", "eth_wake_irq"; 627 clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>, 628 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>, 629 <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>, 630 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>; 631 clock-names = "stmmaceth", "mac_clk_rx", 632 "mac_clk_tx", "clk_mac_refout", 633 "aclk_mac", "pclk_mac", 634 "clk_mac_speed", "ptp_ref"; 635 resets = <&cru SRST_A_GMAC1>; 636 reset-names = "stmmaceth"; 637 rockchip,grf = <&grf>; 638 snps,axi-config = <&gmac1_stmmac_axi_setup>; 639 snps,mixed-burst; 640 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 641 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 642 snps,tso; 643 status = "disabled"; 644 645 mdio1: mdio { 646 compatible = "snps,dwmac-mdio"; 647 #address-cells = <0x1>; 648 #size-cells = <0x0>; 649 }; 650 651 gmac1_stmmac_axi_setup: stmmac-axi-config { 652 snps,blen = <0 0 0 0 16 8 4>; 653 snps,rd_osr_lmt = <8>; 654 snps,wr_osr_lmt = <4>; 655 }; 656 657 gmac1_mtl_rx_setup: rx-queues-config { 658 snps,rx-queues-to-use = <1>; 659 queue0 {}; 660 }; 661 662 gmac1_mtl_tx_setup: tx-queues-config { 663 snps,tx-queues-to-use = <1>; 664 queue0 {}; 665 }; 666 }; 667 668 vop: vop@fe040000 { 669 reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>; 670 reg-names = "vop", "gamma-lut"; 671 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 672 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>, 673 <&cru DCLK_VOP1>, <&cru DCLK_VOP2>; 674 clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2"; 675 iommus = <&vop_mmu>; 676 power-domains = <&power RK3568_PD_VO>; 677 rockchip,grf = <&grf>; 678 status = "disabled"; 679 680 vop_out: ports { 681 #address-cells = <1>; 682 #size-cells = <0>; 683 684 vp0: port@0 { 685 reg = <0>; 686 #address-cells = <1>; 687 #size-cells = <0>; 688 }; 689 690 vp1: port@1 { 691 reg = <1>; 692 #address-cells = <1>; 693 #size-cells = <0>; 694 }; 695 696 vp2: port@2 { 697 reg = <2>; 698 #address-cells = <1>; 699 #size-cells = <0>; 700 }; 701 }; 702 }; 703 704 vop_mmu: iommu@fe043e00 { 705 compatible = "rockchip,rk3568-iommu"; 706 reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>; 707 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 708 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 709 clock-names = "aclk", "iface"; 710 #iommu-cells = <0>; 711 power-domains = <&power RK3568_PD_VO>; 712 status = "disabled"; 713 }; 714 715 dsi0: dsi@fe060000 { 716 compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi"; 717 reg = <0x00 0xfe060000 0x00 0x10000>; 718 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 719 clock-names = "pclk"; 720 clocks = <&cru PCLK_DSITX_0>; 721 phy-names = "dphy"; 722 phys = <&dsi_dphy0>; 723 power-domains = <&power RK3568_PD_VO>; 724 reset-names = "apb"; 725 resets = <&cru SRST_P_DSITX_0>; 726 rockchip,grf = <&grf>; 727 status = "disabled"; 728 729 ports { 730 #address-cells = <1>; 731 #size-cells = <0>; 732 733 dsi0_in: port@0 { 734 reg = <0>; 735 }; 736 737 dsi0_out: port@1 { 738 reg = <1>; 739 }; 740 }; 741 }; 742 743 dsi1: dsi@fe070000 { 744 compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi"; 745 reg = <0x0 0xfe070000 0x0 0x10000>; 746 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 747 clock-names = "pclk"; 748 clocks = <&cru PCLK_DSITX_1>; 749 phy-names = "dphy"; 750 phys = <&dsi_dphy1>; 751 power-domains = <&power RK3568_PD_VO>; 752 reset-names = "apb"; 753 resets = <&cru SRST_P_DSITX_1>; 754 rockchip,grf = <&grf>; 755 status = "disabled"; 756 757 ports { 758 #address-cells = <1>; 759 #size-cells = <0>; 760 761 dsi1_in: port@0 { 762 reg = <0>; 763 }; 764 765 dsi1_out: port@1 { 766 reg = <1>; 767 }; 768 }; 769 }; 770 771 hdmi: hdmi@fe0a0000 { 772 compatible = "rockchip,rk3568-dw-hdmi"; 773 reg = <0x0 0xfe0a0000 0x0 0x20000>; 774 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 775 clocks = <&cru PCLK_HDMI_HOST>, 776 <&cru CLK_HDMI_SFR>, 777 <&cru CLK_HDMI_CEC>, 778 <&pmucru CLK_HDMI_REF>, 779 <&cru HCLK_VO>; 780 clock-names = "iahb", "isfr", "cec", "ref"; 781 pinctrl-names = "default"; 782 pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>; 783 power-domains = <&power RK3568_PD_VO>; 784 reg-io-width = <4>; 785 rockchip,grf = <&grf>; 786 #sound-dai-cells = <0>; 787 status = "disabled"; 788 789 ports { 790 #address-cells = <1>; 791 #size-cells = <0>; 792 793 hdmi_in: port@0 { 794 reg = <0>; 795 }; 796 797 hdmi_out: port@1 { 798 reg = <1>; 799 }; 800 }; 801 }; 802 803 qos_gpu: qos@fe128000 { 804 compatible = "rockchip,rk3568-qos", "syscon"; 805 reg = <0x0 0xfe128000 0x0 0x20>; 806 }; 807 808 qos_rkvenc_rd_m0: qos@fe138080 { 809 compatible = "rockchip,rk3568-qos", "syscon"; 810 reg = <0x0 0xfe138080 0x0 0x20>; 811 }; 812 813 qos_rkvenc_rd_m1: qos@fe138100 { 814 compatible = "rockchip,rk3568-qos", "syscon"; 815 reg = <0x0 0xfe138100 0x0 0x20>; 816 }; 817 818 qos_rkvenc_wr_m0: qos@fe138180 { 819 compatible = "rockchip,rk3568-qos", "syscon"; 820 reg = <0x0 0xfe138180 0x0 0x20>; 821 }; 822 823 qos_isp: qos@fe148000 { 824 compatible = "rockchip,rk3568-qos", "syscon"; 825 reg = <0x0 0xfe148000 0x0 0x20>; 826 }; 827 828 qos_vicap0: qos@fe148080 { 829 compatible = "rockchip,rk3568-qos", "syscon"; 830 reg = <0x0 0xfe148080 0x0 0x20>; 831 }; 832 833 qos_vicap1: qos@fe148100 { 834 compatible = "rockchip,rk3568-qos", "syscon"; 835 reg = <0x0 0xfe148100 0x0 0x20>; 836 }; 837 838 qos_vpu: qos@fe150000 { 839 compatible = "rockchip,rk3568-qos", "syscon"; 840 reg = <0x0 0xfe150000 0x0 0x20>; 841 }; 842 843 qos_ebc: qos@fe158000 { 844 compatible = "rockchip,rk3568-qos", "syscon"; 845 reg = <0x0 0xfe158000 0x0 0x20>; 846 }; 847 848 qos_iep: qos@fe158100 { 849 compatible = "rockchip,rk3568-qos", "syscon"; 850 reg = <0x0 0xfe158100 0x0 0x20>; 851 }; 852 853 qos_jpeg_dec: qos@fe158180 { 854 compatible = "rockchip,rk3568-qos", "syscon"; 855 reg = <0x0 0xfe158180 0x0 0x20>; 856 }; 857 858 qos_jpeg_enc: qos@fe158200 { 859 compatible = "rockchip,rk3568-qos", "syscon"; 860 reg = <0x0 0xfe158200 0x0 0x20>; 861 }; 862 863 qos_rga_rd: qos@fe158280 { 864 compatible = "rockchip,rk3568-qos", "syscon"; 865 reg = <0x0 0xfe158280 0x0 0x20>; 866 }; 867 868 qos_rga_wr: qos@fe158300 { 869 compatible = "rockchip,rk3568-qos", "syscon"; 870 reg = <0x0 0xfe158300 0x0 0x20>; 871 }; 872 873 qos_npu: qos@fe180000 { 874 compatible = "rockchip,rk3568-qos", "syscon"; 875 reg = <0x0 0xfe180000 0x0 0x20>; 876 }; 877 878 qos_pcie2x1: qos@fe190000 { 879 compatible = "rockchip,rk3568-qos", "syscon"; 880 reg = <0x0 0xfe190000 0x0 0x20>; 881 }; 882 883 qos_sata1: qos@fe190280 { 884 compatible = "rockchip,rk3568-qos", "syscon"; 885 reg = <0x0 0xfe190280 0x0 0x20>; 886 }; 887 888 qos_sata2: qos@fe190300 { 889 compatible = "rockchip,rk3568-qos", "syscon"; 890 reg = <0x0 0xfe190300 0x0 0x20>; 891 }; 892 893 qos_usb3_0: qos@fe190380 { 894 compatible = "rockchip,rk3568-qos", "syscon"; 895 reg = <0x0 0xfe190380 0x0 0x20>; 896 }; 897 898 qos_usb3_1: qos@fe190400 { 899 compatible = "rockchip,rk3568-qos", "syscon"; 900 reg = <0x0 0xfe190400 0x0 0x20>; 901 }; 902 903 qos_rkvdec: qos@fe198000 { 904 compatible = "rockchip,rk3568-qos", "syscon"; 905 reg = <0x0 0xfe198000 0x0 0x20>; 906 }; 907 908 qos_hdcp: qos@fe1a8000 { 909 compatible = "rockchip,rk3568-qos", "syscon"; 910 reg = <0x0 0xfe1a8000 0x0 0x20>; 911 }; 912 913 qos_vop_m0: qos@fe1a8080 { 914 compatible = "rockchip,rk3568-qos", "syscon"; 915 reg = <0x0 0xfe1a8080 0x0 0x20>; 916 }; 917 918 qos_vop_m1: qos@fe1a8100 { 919 compatible = "rockchip,rk3568-qos", "syscon"; 920 reg = <0x0 0xfe1a8100 0x0 0x20>; 921 }; 922 923 dfi: dfi@fe230000 { 924 compatible = "rockchip,rk3568-dfi"; 925 reg = <0x00 0xfe230000 0x00 0x400>; 926 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 927 rockchip,pmu = <&pmugrf>; 928 }; 929 930 pcie2x1: pcie@fe260000 { 931 compatible = "rockchip,rk3568-pcie"; 932 reg = <0x3 0xc0000000 0x0 0x00400000>, 933 <0x0 0xfe260000 0x0 0x00010000>, 934 <0x0 0xf4000000 0x0 0x00100000>; 935 reg-names = "dbi", "apb", "config"; 936 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 937 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 938 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 939 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 941 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 942 bus-range = <0x0 0xf>; 943 clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, 944 <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, 945 <&cru CLK_PCIE20_AUX_NDFT>; 946 clock-names = "aclk_mst", "aclk_slv", 947 "aclk_dbi", "pclk", "aux"; 948 device_type = "pci"; 949 #interrupt-cells = <1>; 950 interrupt-map-mask = <0 0 0 7>; 951 interrupt-map = <0 0 0 1 &pcie_intc 0>, 952 <0 0 0 2 &pcie_intc 1>, 953 <0 0 0 3 &pcie_intc 2>, 954 <0 0 0 4 &pcie_intc 3>; 955 linux,pci-domain = <0>; 956 num-ib-windows = <6>; 957 num-ob-windows = <2>; 958 max-link-speed = <2>; 959 msi-map = <0x0 &gic 0x0 0x1000>; 960 num-lanes = <1>; 961 phys = <&combphy2 PHY_TYPE_PCIE>; 962 phy-names = "pcie-phy"; 963 power-domains = <&power RK3568_PD_PIPE>; 964 ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, 965 <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>, 966 <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>; 967 resets = <&cru SRST_PCIE20_POWERUP>; 968 reset-names = "pipe"; 969 #address-cells = <3>; 970 #size-cells = <2>; 971 status = "disabled"; 972 973 pcie_intc: legacy-interrupt-controller { 974 #address-cells = <0>; 975 #interrupt-cells = <1>; 976 interrupt-controller; 977 interrupt-parent = <&gic>; 978 interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>; 979 }; 980 }; 981 982 sdmmc0: mmc@fe2b0000 { 983 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; 984 reg = <0x0 0xfe2b0000 0x0 0x4000>; 985 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 986 clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>, 987 <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>; 988 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 989 fifo-depth = <0x100>; 990 max-frequency = <150000000>; 991 resets = <&cru SRST_SDMMC0>; 992 reset-names = "reset"; 993 status = "disabled"; 994 }; 995 996 sdmmc1: mmc@fe2c0000 { 997 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; 998 reg = <0x0 0xfe2c0000 0x0 0x4000>; 999 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1000 clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>, 1001 <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>; 1002 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1003 fifo-depth = <0x100>; 1004 max-frequency = <150000000>; 1005 resets = <&cru SRST_SDMMC1>; 1006 reset-names = "reset"; 1007 status = "disabled"; 1008 }; 1009 1010 sfc: spi@fe300000 { 1011 compatible = "rockchip,sfc"; 1012 reg = <0x0 0xfe300000 0x0 0x4000>; 1013 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1014 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 1015 clock-names = "clk_sfc", "hclk_sfc"; 1016 pinctrl-0 = <&fspi_pins>; 1017 pinctrl-names = "default"; 1018 status = "disabled"; 1019 }; 1020 1021 sdhci: mmc@fe310000 { 1022 compatible = "rockchip,rk3568-dwcmshc"; 1023 reg = <0x0 0xfe310000 0x0 0x10000>; 1024 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1025 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>; 1026 assigned-clock-rates = <200000000>, <24000000>; 1027 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, 1028 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 1029 <&cru TCLK_EMMC>; 1030 clock-names = "core", "bus", "axi", "block", "timer"; 1031 status = "disabled"; 1032 }; 1033 1034 /* 1035 * Testing showed that the HWRNG found in RK3566 produces unacceptably 1036 * low quality of random data, so the HWRNG isn't enabled for all RK356x 1037 * SoC variants despite its presence. 1038 */ 1039 rng: rng@fe388000 { 1040 compatible = "rockchip,rk3568-rng"; 1041 reg = <0x0 0xfe388000 0x0 0x4000>; 1042 clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>; 1043 clock-names = "core", "ahb"; 1044 resets = <&cru SRST_TRNG_NS>; 1045 status = "disabled"; 1046 }; 1047 1048 i2s0_8ch: i2s@fe400000 { 1049 compatible = "rockchip,rk3568-i2s-tdm"; 1050 reg = <0x0 0xfe400000 0x0 0x1000>; 1051 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1052 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; 1053 assigned-clock-rates = <1188000000>, <1188000000>; 1054 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; 1055 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1056 dmas = <&dmac1 0>; 1057 dma-names = "tx"; 1058 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; 1059 reset-names = "tx-m", "rx-m"; 1060 rockchip,grf = <&grf>; 1061 #sound-dai-cells = <0>; 1062 status = "disabled"; 1063 }; 1064 1065 i2s1_8ch: i2s@fe410000 { 1066 compatible = "rockchip,rk3568-i2s-tdm"; 1067 reg = <0x0 0xfe410000 0x0 0x1000>; 1068 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1069 assigned-clocks = <&cru CLK_I2S1_8CH_TX_SRC>, <&cru CLK_I2S1_8CH_RX_SRC>; 1070 assigned-clock-rates = <1188000000>, <1188000000>; 1071 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, 1072 <&cru HCLK_I2S1_8CH>; 1073 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1074 dmas = <&dmac1 3>, <&dmac1 2>; 1075 dma-names = "rx", "tx"; 1076 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; 1077 reset-names = "tx-m", "rx-m"; 1078 rockchip,grf = <&grf>; 1079 pinctrl-names = "default"; 1080 pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx 1081 &i2s1m0_lrcktx &i2s1m0_lrckrx 1082 &i2s1m0_sdi0 &i2s1m0_sdi1 1083 &i2s1m0_sdi2 &i2s1m0_sdi3 1084 &i2s1m0_sdo0 &i2s1m0_sdo1 1085 &i2s1m0_sdo2 &i2s1m0_sdo3>; 1086 #sound-dai-cells = <0>; 1087 status = "disabled"; 1088 }; 1089 1090 i2s2_2ch: i2s@fe420000 { 1091 compatible = "rockchip,rk3568-i2s-tdm"; 1092 reg = <0x0 0xfe420000 0x0 0x1000>; 1093 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1094 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>; 1095 assigned-clock-rates = <1188000000>; 1096 clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; 1097 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1098 dmas = <&dmac1 4>, <&dmac1 5>; 1099 dma-names = "tx", "rx"; 1100 resets = <&cru SRST_M_I2S2_2CH>; 1101 reset-names = "tx-m"; 1102 rockchip,grf = <&grf>; 1103 pinctrl-names = "default"; 1104 pinctrl-0 = <&i2s2m0_sclktx 1105 &i2s2m0_lrcktx 1106 &i2s2m0_sdi 1107 &i2s2m0_sdo>; 1108 #sound-dai-cells = <0>; 1109 status = "disabled"; 1110 }; 1111 1112 i2s3_2ch: i2s@fe430000 { 1113 compatible = "rockchip,rk3568-i2s-tdm"; 1114 reg = <0x0 0xfe430000 0x0 0x1000>; 1115 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 1116 clocks = <&cru MCLK_I2S3_2CH_TX>, <&cru MCLK_I2S3_2CH_RX>, 1117 <&cru HCLK_I2S3_2CH>; 1118 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1119 dmas = <&dmac1 6>, <&dmac1 7>; 1120 dma-names = "tx", "rx"; 1121 resets = <&cru SRST_M_I2S3_2CH_TX>, <&cru SRST_M_I2S3_2CH_RX>; 1122 reset-names = "tx-m", "rx-m"; 1123 rockchip,grf = <&grf>; 1124 #sound-dai-cells = <0>; 1125 status = "disabled"; 1126 }; 1127 1128 pdm: pdm@fe440000 { 1129 compatible = "rockchip,rk3568-pdm"; 1130 reg = <0x0 0xfe440000 0x0 0x1000>; 1131 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 1132 clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>; 1133 clock-names = "pdm_clk", "pdm_hclk"; 1134 dmas = <&dmac1 9>; 1135 dma-names = "rx"; 1136 pinctrl-0 = <&pdmm0_clk 1137 &pdmm0_clk1 1138 &pdmm0_sdi0 1139 &pdmm0_sdi1 1140 &pdmm0_sdi2 1141 &pdmm0_sdi3>; 1142 pinctrl-names = "default"; 1143 resets = <&cru SRST_M_PDM>; 1144 reset-names = "pdm-m"; 1145 #sound-dai-cells = <0>; 1146 status = "disabled"; 1147 }; 1148 1149 spdif: spdif@fe460000 { 1150 compatible = "rockchip,rk3568-spdif"; 1151 reg = <0x0 0xfe460000 0x0 0x1000>; 1152 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1153 clock-names = "mclk", "hclk"; 1154 clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>; 1155 dmas = <&dmac1 1>; 1156 dma-names = "tx"; 1157 pinctrl-names = "default"; 1158 pinctrl-0 = <&spdifm0_tx>; 1159 #sound-dai-cells = <0>; 1160 status = "disabled"; 1161 }; 1162 1163 dmac0: dma-controller@fe530000 { 1164 compatible = "arm,pl330", "arm,primecell"; 1165 reg = <0x0 0xfe530000 0x0 0x4000>; 1166 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1167 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1168 arm,pl330-periph-burst; 1169 clocks = <&cru ACLK_BUS>; 1170 clock-names = "apb_pclk"; 1171 #dma-cells = <1>; 1172 }; 1173 1174 dmac1: dma-controller@fe550000 { 1175 compatible = "arm,pl330", "arm,primecell"; 1176 reg = <0x0 0xfe550000 0x0 0x4000>; 1177 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1178 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1179 arm,pl330-periph-burst; 1180 clocks = <&cru ACLK_BUS>; 1181 clock-names = "apb_pclk"; 1182 #dma-cells = <1>; 1183 }; 1184 1185 i2c1: i2c@fe5a0000 { 1186 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 1187 reg = <0x0 0xfe5a0000 0x0 0x1000>; 1188 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1189 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 1190 clock-names = "i2c", "pclk"; 1191 pinctrl-0 = <&i2c1_xfer>; 1192 pinctrl-names = "default"; 1193 #address-cells = <1>; 1194 #size-cells = <0>; 1195 status = "disabled"; 1196 }; 1197 1198 i2c2: i2c@fe5b0000 { 1199 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 1200 reg = <0x0 0xfe5b0000 0x0 0x1000>; 1201 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1202 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 1203 clock-names = "i2c", "pclk"; 1204 pinctrl-0 = <&i2c2m0_xfer>; 1205 pinctrl-names = "default"; 1206 #address-cells = <1>; 1207 #size-cells = <0>; 1208 status = "disabled"; 1209 }; 1210 1211 i2c3: i2c@fe5c0000 { 1212 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 1213 reg = <0x0 0xfe5c0000 0x0 0x1000>; 1214 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1215 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 1216 clock-names = "i2c", "pclk"; 1217 pinctrl-0 = <&i2c3m0_xfer>; 1218 pinctrl-names = "default"; 1219 #address-cells = <1>; 1220 #size-cells = <0>; 1221 status = "disabled"; 1222 }; 1223 1224 i2c4: i2c@fe5d0000 { 1225 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 1226 reg = <0x0 0xfe5d0000 0x0 0x1000>; 1227 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 1228 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 1229 clock-names = "i2c", "pclk"; 1230 pinctrl-0 = <&i2c4m0_xfer>; 1231 pinctrl-names = "default"; 1232 #address-cells = <1>; 1233 #size-cells = <0>; 1234 status = "disabled"; 1235 }; 1236 1237 i2c5: i2c@fe5e0000 { 1238 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 1239 reg = <0x0 0xfe5e0000 0x0 0x1000>; 1240 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1241 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 1242 clock-names = "i2c", "pclk"; 1243 pinctrl-0 = <&i2c5m0_xfer>; 1244 pinctrl-names = "default"; 1245 #address-cells = <1>; 1246 #size-cells = <0>; 1247 status = "disabled"; 1248 }; 1249 1250 wdt: watchdog@fe600000 { 1251 compatible = "rockchip,rk3568-wdt", "snps,dw-wdt"; 1252 reg = <0x0 0xfe600000 0x0 0x100>; 1253 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 1254 clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>; 1255 clock-names = "tclk", "pclk"; 1256 }; 1257 1258 spi0: spi@fe610000 { 1259 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 1260 reg = <0x0 0xfe610000 0x0 0x1000>; 1261 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1262 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 1263 clock-names = "spiclk", "apb_pclk"; 1264 dmas = <&dmac0 20>, <&dmac0 21>; 1265 dma-names = "tx", "rx"; 1266 pinctrl-names = "default"; 1267 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; 1268 #address-cells = <1>; 1269 #size-cells = <0>; 1270 status = "disabled"; 1271 }; 1272 1273 spi1: spi@fe620000 { 1274 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 1275 reg = <0x0 0xfe620000 0x0 0x1000>; 1276 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1277 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 1278 clock-names = "spiclk", "apb_pclk"; 1279 dmas = <&dmac0 22>, <&dmac0 23>; 1280 dma-names = "tx", "rx"; 1281 pinctrl-names = "default"; 1282 pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>; 1283 #address-cells = <1>; 1284 #size-cells = <0>; 1285 status = "disabled"; 1286 }; 1287 1288 spi2: spi@fe630000 { 1289 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 1290 reg = <0x0 0xfe630000 0x0 0x1000>; 1291 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1292 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; 1293 clock-names = "spiclk", "apb_pclk"; 1294 dmas = <&dmac0 24>, <&dmac0 25>; 1295 dma-names = "tx", "rx"; 1296 pinctrl-names = "default"; 1297 pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>; 1298 #address-cells = <1>; 1299 #size-cells = <0>; 1300 status = "disabled"; 1301 }; 1302 1303 spi3: spi@fe640000 { 1304 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 1305 reg = <0x0 0xfe640000 0x0 0x1000>; 1306 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1307 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; 1308 clock-names = "spiclk", "apb_pclk"; 1309 dmas = <&dmac0 26>, <&dmac0 27>; 1310 dma-names = "tx", "rx"; 1311 pinctrl-names = "default"; 1312 pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>; 1313 #address-cells = <1>; 1314 #size-cells = <0>; 1315 status = "disabled"; 1316 }; 1317 1318 uart1: serial@fe650000 { 1319 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1320 reg = <0x0 0xfe650000 0x0 0x100>; 1321 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1322 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 1323 clock-names = "baudclk", "apb_pclk"; 1324 dmas = <&dmac0 2>, <&dmac0 3>; 1325 pinctrl-0 = <&uart1m0_xfer>; 1326 pinctrl-names = "default"; 1327 reg-io-width = <4>; 1328 reg-shift = <2>; 1329 status = "disabled"; 1330 }; 1331 1332 uart2: serial@fe660000 { 1333 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1334 reg = <0x0 0xfe660000 0x0 0x100>; 1335 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1336 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 1337 clock-names = "baudclk", "apb_pclk"; 1338 dmas = <&dmac0 4>, <&dmac0 5>; 1339 pinctrl-0 = <&uart2m0_xfer>; 1340 pinctrl-names = "default"; 1341 reg-io-width = <4>; 1342 reg-shift = <2>; 1343 status = "disabled"; 1344 }; 1345 1346 uart3: serial@fe670000 { 1347 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1348 reg = <0x0 0xfe670000 0x0 0x100>; 1349 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 1350 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 1351 clock-names = "baudclk", "apb_pclk"; 1352 dmas = <&dmac0 6>, <&dmac0 7>; 1353 pinctrl-0 = <&uart3m0_xfer>; 1354 pinctrl-names = "default"; 1355 reg-io-width = <4>; 1356 reg-shift = <2>; 1357 status = "disabled"; 1358 }; 1359 1360 uart4: serial@fe680000 { 1361 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1362 reg = <0x0 0xfe680000 0x0 0x100>; 1363 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1364 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 1365 clock-names = "baudclk", "apb_pclk"; 1366 dmas = <&dmac0 8>, <&dmac0 9>; 1367 pinctrl-0 = <&uart4m0_xfer>; 1368 pinctrl-names = "default"; 1369 reg-io-width = <4>; 1370 reg-shift = <2>; 1371 status = "disabled"; 1372 }; 1373 1374 uart5: serial@fe690000 { 1375 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1376 reg = <0x0 0xfe690000 0x0 0x100>; 1377 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1378 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 1379 clock-names = "baudclk", "apb_pclk"; 1380 dmas = <&dmac0 10>, <&dmac0 11>; 1381 pinctrl-0 = <&uart5m0_xfer>; 1382 pinctrl-names = "default"; 1383 reg-io-width = <4>; 1384 reg-shift = <2>; 1385 status = "disabled"; 1386 }; 1387 1388 uart6: serial@fe6a0000 { 1389 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1390 reg = <0x0 0xfe6a0000 0x0 0x100>; 1391 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1392 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 1393 clock-names = "baudclk", "apb_pclk"; 1394 dmas = <&dmac0 12>, <&dmac0 13>; 1395 pinctrl-0 = <&uart6m0_xfer>; 1396 pinctrl-names = "default"; 1397 reg-io-width = <4>; 1398 reg-shift = <2>; 1399 status = "disabled"; 1400 }; 1401 1402 uart7: serial@fe6b0000 { 1403 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1404 reg = <0x0 0xfe6b0000 0x0 0x100>; 1405 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 1406 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 1407 clock-names = "baudclk", "apb_pclk"; 1408 dmas = <&dmac0 14>, <&dmac0 15>; 1409 pinctrl-0 = <&uart7m0_xfer>; 1410 pinctrl-names = "default"; 1411 reg-io-width = <4>; 1412 reg-shift = <2>; 1413 status = "disabled"; 1414 }; 1415 1416 uart8: serial@fe6c0000 { 1417 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1418 reg = <0x0 0xfe6c0000 0x0 0x100>; 1419 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 1420 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 1421 clock-names = "baudclk", "apb_pclk"; 1422 dmas = <&dmac0 16>, <&dmac0 17>; 1423 pinctrl-0 = <&uart8m0_xfer>; 1424 pinctrl-names = "default"; 1425 reg-io-width = <4>; 1426 reg-shift = <2>; 1427 status = "disabled"; 1428 }; 1429 1430 uart9: serial@fe6d0000 { 1431 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1432 reg = <0x0 0xfe6d0000 0x0 0x100>; 1433 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 1434 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 1435 clock-names = "baudclk", "apb_pclk"; 1436 dmas = <&dmac0 18>, <&dmac0 19>; 1437 pinctrl-0 = <&uart9m0_xfer>; 1438 pinctrl-names = "default"; 1439 reg-io-width = <4>; 1440 reg-shift = <2>; 1441 status = "disabled"; 1442 }; 1443 1444 thermal_zones: thermal-zones { 1445 cpu_thermal: cpu-thermal { 1446 polling-delay-passive = <100>; 1447 polling-delay = <1000>; 1448 1449 thermal-sensors = <&tsadc 0>; 1450 1451 trips { 1452 cpu_alert0: cpu_alert0 { 1453 temperature = <70000>; 1454 hysteresis = <2000>; 1455 type = "passive"; 1456 }; 1457 cpu_alert1: cpu_alert1 { 1458 temperature = <75000>; 1459 hysteresis = <2000>; 1460 type = "passive"; 1461 }; 1462 cpu_crit: cpu_crit { 1463 temperature = <95000>; 1464 hysteresis = <2000>; 1465 type = "critical"; 1466 }; 1467 }; 1468 1469 cooling-maps { 1470 map0 { 1471 trip = <&cpu_alert0>; 1472 cooling-device = 1473 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1474 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1475 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1476 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1477 }; 1478 }; 1479 }; 1480 1481 gpu_thermal: gpu-thermal { 1482 polling-delay-passive = <20>; /* milliseconds */ 1483 polling-delay = <1000>; /* milliseconds */ 1484 1485 thermal-sensors = <&tsadc 1>; 1486 1487 trips { 1488 gpu_threshold: gpu-threshold { 1489 temperature = <70000>; 1490 hysteresis = <2000>; 1491 type = "passive"; 1492 }; 1493 gpu_target: gpu-target { 1494 temperature = <75000>; 1495 hysteresis = <2000>; 1496 type = "passive"; 1497 }; 1498 gpu_crit: gpu-crit { 1499 temperature = <95000>; 1500 hysteresis = <2000>; 1501 type = "critical"; 1502 }; 1503 }; 1504 1505 cooling-maps { 1506 map0 { 1507 trip = <&gpu_target>; 1508 cooling-device = 1509 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1510 }; 1511 }; 1512 }; 1513 }; 1514 1515 tsadc: tsadc@fe710000 { 1516 compatible = "rockchip,rk3568-tsadc"; 1517 reg = <0x0 0xfe710000 0x0 0x100>; 1518 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 1519 assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>; 1520 assigned-clock-rates = <17000000>, <700000>; 1521 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; 1522 clock-names = "tsadc", "apb_pclk"; 1523 resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>, 1524 <&cru SRST_TSADCPHY>; 1525 rockchip,grf = <&grf>; 1526 rockchip,hw-tshut-temp = <95000>; 1527 pinctrl-names = "default", "sleep"; 1528 pinctrl-0 = <&tsadc_shutorg>; 1529 pinctrl-1 = <&tsadc_pin>; 1530 #thermal-sensor-cells = <1>; 1531 status = "disabled"; 1532 }; 1533 1534 saradc: saradc@fe720000 { 1535 compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc"; 1536 reg = <0x0 0xfe720000 0x0 0x100>; 1537 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1538 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 1539 clock-names = "saradc", "apb_pclk"; 1540 resets = <&cru SRST_P_SARADC>; 1541 reset-names = "saradc-apb"; 1542 #io-channel-cells = <1>; 1543 status = "disabled"; 1544 }; 1545 1546 pwm4: pwm@fe6e0000 { 1547 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1548 reg = <0x0 0xfe6e0000 0x0 0x10>; 1549 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1550 clock-names = "pwm", "pclk"; 1551 pinctrl-0 = <&pwm4_pins>; 1552 pinctrl-names = "default"; 1553 #pwm-cells = <3>; 1554 status = "disabled"; 1555 }; 1556 1557 pwm5: pwm@fe6e0010 { 1558 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1559 reg = <0x0 0xfe6e0010 0x0 0x10>; 1560 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1561 clock-names = "pwm", "pclk"; 1562 pinctrl-0 = <&pwm5_pins>; 1563 pinctrl-names = "default"; 1564 #pwm-cells = <3>; 1565 status = "disabled"; 1566 }; 1567 1568 pwm6: pwm@fe6e0020 { 1569 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1570 reg = <0x0 0xfe6e0020 0x0 0x10>; 1571 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1572 clock-names = "pwm", "pclk"; 1573 pinctrl-0 = <&pwm6_pins>; 1574 pinctrl-names = "default"; 1575 #pwm-cells = <3>; 1576 status = "disabled"; 1577 }; 1578 1579 pwm7: pwm@fe6e0030 { 1580 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1581 reg = <0x0 0xfe6e0030 0x0 0x10>; 1582 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1583 clock-names = "pwm", "pclk"; 1584 pinctrl-0 = <&pwm7_pins>; 1585 pinctrl-names = "default"; 1586 #pwm-cells = <3>; 1587 status = "disabled"; 1588 }; 1589 1590 pwm8: pwm@fe6f0000 { 1591 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1592 reg = <0x0 0xfe6f0000 0x0 0x10>; 1593 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1594 clock-names = "pwm", "pclk"; 1595 pinctrl-0 = <&pwm8m0_pins>; 1596 pinctrl-names = "default"; 1597 #pwm-cells = <3>; 1598 status = "disabled"; 1599 }; 1600 1601 pwm9: pwm@fe6f0010 { 1602 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1603 reg = <0x0 0xfe6f0010 0x0 0x10>; 1604 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1605 clock-names = "pwm", "pclk"; 1606 pinctrl-0 = <&pwm9m0_pins>; 1607 pinctrl-names = "default"; 1608 #pwm-cells = <3>; 1609 status = "disabled"; 1610 }; 1611 1612 pwm10: pwm@fe6f0020 { 1613 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1614 reg = <0x0 0xfe6f0020 0x0 0x10>; 1615 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1616 clock-names = "pwm", "pclk"; 1617 pinctrl-0 = <&pwm10m0_pins>; 1618 pinctrl-names = "default"; 1619 #pwm-cells = <3>; 1620 status = "disabled"; 1621 }; 1622 1623 pwm11: pwm@fe6f0030 { 1624 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1625 reg = <0x0 0xfe6f0030 0x0 0x10>; 1626 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1627 clock-names = "pwm", "pclk"; 1628 pinctrl-0 = <&pwm11m0_pins>; 1629 pinctrl-names = "default"; 1630 #pwm-cells = <3>; 1631 status = "disabled"; 1632 }; 1633 1634 pwm12: pwm@fe700000 { 1635 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1636 reg = <0x0 0xfe700000 0x0 0x10>; 1637 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1638 clock-names = "pwm", "pclk"; 1639 pinctrl-0 = <&pwm12m0_pins>; 1640 pinctrl-names = "default"; 1641 #pwm-cells = <3>; 1642 status = "disabled"; 1643 }; 1644 1645 pwm13: pwm@fe700010 { 1646 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1647 reg = <0x0 0xfe700010 0x0 0x10>; 1648 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1649 clock-names = "pwm", "pclk"; 1650 pinctrl-0 = <&pwm13m0_pins>; 1651 pinctrl-names = "default"; 1652 #pwm-cells = <3>; 1653 status = "disabled"; 1654 }; 1655 1656 pwm14: pwm@fe700020 { 1657 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1658 reg = <0x0 0xfe700020 0x0 0x10>; 1659 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1660 clock-names = "pwm", "pclk"; 1661 pinctrl-0 = <&pwm14m0_pins>; 1662 pinctrl-names = "default"; 1663 #pwm-cells = <3>; 1664 status = "disabled"; 1665 }; 1666 1667 pwm15: pwm@fe700030 { 1668 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1669 reg = <0x0 0xfe700030 0x0 0x10>; 1670 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1671 clock-names = "pwm", "pclk"; 1672 pinctrl-0 = <&pwm15m0_pins>; 1673 pinctrl-names = "default"; 1674 #pwm-cells = <3>; 1675 status = "disabled"; 1676 }; 1677 1678 combphy1: phy@fe830000 { 1679 compatible = "rockchip,rk3568-naneng-combphy"; 1680 reg = <0x0 0xfe830000 0x0 0x100>; 1681 clocks = <&pmucru CLK_PCIEPHY1_REF>, 1682 <&cru PCLK_PIPEPHY1>, 1683 <&cru PCLK_PIPE>; 1684 clock-names = "ref", "apb", "pipe"; 1685 assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; 1686 assigned-clock-rates = <100000000>; 1687 resets = <&cru SRST_PIPEPHY1>; 1688 reset-names = "phy"; 1689 rockchip,pipe-grf = <&pipegrf>; 1690 rockchip,pipe-phy-grf = <&pipe_phy_grf1>; 1691 #phy-cells = <1>; 1692 status = "disabled"; 1693 }; 1694 1695 combphy2: phy@fe840000 { 1696 compatible = "rockchip,rk3568-naneng-combphy"; 1697 reg = <0x0 0xfe840000 0x0 0x100>; 1698 clocks = <&pmucru CLK_PCIEPHY2_REF>, 1699 <&cru PCLK_PIPEPHY2>, 1700 <&cru PCLK_PIPE>; 1701 clock-names = "ref", "apb", "pipe"; 1702 assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; 1703 assigned-clock-rates = <100000000>; 1704 resets = <&cru SRST_PIPEPHY2>; 1705 reset-names = "phy"; 1706 rockchip,pipe-grf = <&pipegrf>; 1707 rockchip,pipe-phy-grf = <&pipe_phy_grf2>; 1708 #phy-cells = <1>; 1709 status = "disabled"; 1710 }; 1711 1712 csi_dphy: phy@fe870000 { 1713 compatible = "rockchip,rk3568-csi-dphy"; 1714 reg = <0x0 0xfe870000 0x0 0x10000>; 1715 clocks = <&cru PCLK_MIPICSIPHY>; 1716 clock-names = "pclk"; 1717 #phy-cells = <0>; 1718 resets = <&cru SRST_P_MIPICSIPHY>; 1719 reset-names = "apb"; 1720 rockchip,grf = <&grf>; 1721 status = "disabled"; 1722 }; 1723 1724 dsi_dphy0: mipi-dphy@fe850000 { 1725 compatible = "rockchip,rk3568-dsi-dphy"; 1726 reg = <0x0 0xfe850000 0x0 0x10000>; 1727 clock-names = "ref", "pclk"; 1728 clocks = <&pmucru CLK_MIPIDSIPHY0_REF>, <&cru PCLK_MIPIDSIPHY0>; 1729 #phy-cells = <0>; 1730 power-domains = <&power RK3568_PD_VO>; 1731 reset-names = "apb"; 1732 resets = <&cru SRST_P_MIPIDSIPHY0>; 1733 status = "disabled"; 1734 }; 1735 1736 dsi_dphy1: mipi-dphy@fe860000 { 1737 compatible = "rockchip,rk3568-dsi-dphy"; 1738 reg = <0x0 0xfe860000 0x0 0x10000>; 1739 clock-names = "ref", "pclk"; 1740 clocks = <&pmucru CLK_MIPIDSIPHY1_REF>, <&cru PCLK_MIPIDSIPHY1>; 1741 #phy-cells = <0>; 1742 power-domains = <&power RK3568_PD_VO>; 1743 reset-names = "apb"; 1744 resets = <&cru SRST_P_MIPIDSIPHY1>; 1745 status = "disabled"; 1746 }; 1747 1748 usb2phy0: usb2phy@fe8a0000 { 1749 compatible = "rockchip,rk3568-usb2phy"; 1750 reg = <0x0 0xfe8a0000 0x0 0x10000>; 1751 clocks = <&pmucru CLK_USBPHY0_REF>; 1752 clock-names = "phyclk"; 1753 clock-output-names = "clk_usbphy0_480m"; 1754 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 1755 rockchip,usbgrf = <&usb2phy0_grf>; 1756 #clock-cells = <0>; 1757 status = "disabled"; 1758 1759 usb2phy0_host: host-port { 1760 #phy-cells = <0>; 1761 status = "disabled"; 1762 }; 1763 1764 usb2phy0_otg: otg-port { 1765 #phy-cells = <0>; 1766 status = "disabled"; 1767 }; 1768 }; 1769 1770 usb2phy1: usb2phy@fe8b0000 { 1771 compatible = "rockchip,rk3568-usb2phy"; 1772 reg = <0x0 0xfe8b0000 0x0 0x10000>; 1773 clocks = <&pmucru CLK_USBPHY1_REF>; 1774 clock-names = "phyclk"; 1775 clock-output-names = "clk_usbphy1_480m"; 1776 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1777 rockchip,usbgrf = <&usb2phy1_grf>; 1778 #clock-cells = <0>; 1779 status = "disabled"; 1780 1781 usb2phy1_host: host-port { 1782 #phy-cells = <0>; 1783 status = "disabled"; 1784 }; 1785 1786 usb2phy1_otg: otg-port { 1787 #phy-cells = <0>; 1788 status = "disabled"; 1789 }; 1790 }; 1791 1792 pinctrl: pinctrl { 1793 compatible = "rockchip,rk3568-pinctrl"; 1794 rockchip,grf = <&grf>; 1795 rockchip,pmu = <&pmugrf>; 1796 #address-cells = <2>; 1797 #size-cells = <2>; 1798 ranges; 1799 1800 gpio0: gpio@fdd60000 { 1801 compatible = "rockchip,gpio-bank"; 1802 reg = <0x0 0xfdd60000 0x0 0x100>; 1803 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1804 clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; 1805 gpio-controller; 1806 gpio-ranges = <&pinctrl 0 0 32>; 1807 #gpio-cells = <2>; 1808 interrupt-controller; 1809 #interrupt-cells = <2>; 1810 }; 1811 1812 gpio1: gpio@fe740000 { 1813 compatible = "rockchip,gpio-bank"; 1814 reg = <0x0 0xfe740000 0x0 0x100>; 1815 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1816 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 1817 gpio-controller; 1818 gpio-ranges = <&pinctrl 0 32 32>; 1819 #gpio-cells = <2>; 1820 interrupt-controller; 1821 #interrupt-cells = <2>; 1822 }; 1823 1824 gpio2: gpio@fe750000 { 1825 compatible = "rockchip,gpio-bank"; 1826 reg = <0x0 0xfe750000 0x0 0x100>; 1827 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1828 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 1829 gpio-controller; 1830 gpio-ranges = <&pinctrl 0 64 32>; 1831 #gpio-cells = <2>; 1832 interrupt-controller; 1833 #interrupt-cells = <2>; 1834 }; 1835 1836 gpio3: gpio@fe760000 { 1837 compatible = "rockchip,gpio-bank"; 1838 reg = <0x0 0xfe760000 0x0 0x100>; 1839 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1840 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 1841 gpio-controller; 1842 gpio-ranges = <&pinctrl 0 96 32>; 1843 #gpio-cells = <2>; 1844 interrupt-controller; 1845 #interrupt-cells = <2>; 1846 }; 1847 1848 gpio4: gpio@fe770000 { 1849 compatible = "rockchip,gpio-bank"; 1850 reg = <0x0 0xfe770000 0x0 0x100>; 1851 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1852 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 1853 gpio-controller; 1854 gpio-ranges = <&pinctrl 0 128 32>; 1855 #gpio-cells = <2>; 1856 interrupt-controller; 1857 #interrupt-cells = <2>; 1858 }; 1859 }; 1860}; 1861 1862#include "rk3568-pinctrl.dtsi" 1863