xref: /freebsd/sys/contrib/device-tree/src/arm/rockchip/rk322x.dtsi (revision 8d13bc63c0e1d50bc9e47ac1f26329c999bfecf0)
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
3#include <dt-bindings/gpio/gpio.h>
4#include <dt-bindings/interrupt-controller/irq.h>
5#include <dt-bindings/interrupt-controller/arm-gic.h>
6#include <dt-bindings/pinctrl/rockchip.h>
7#include <dt-bindings/clock/rk3228-cru.h>
8#include <dt-bindings/thermal/thermal.h>
9#include <dt-bindings/power/rk3228-power.h>
10
11/ {
12	#address-cells = <1>;
13	#size-cells = <1>;
14
15	interrupt-parent = <&gic>;
16
17	aliases {
18		gpio0 = &gpio0;
19		gpio1 = &gpio1;
20		gpio2 = &gpio2;
21		gpio3 = &gpio3;
22		serial0 = &uart0;
23		serial1 = &uart1;
24		serial2 = &uart2;
25		spi0 = &spi0;
26	};
27
28	cpus {
29		#address-cells = <1>;
30		#size-cells = <0>;
31
32		cpu0: cpu@f00 {
33			device_type = "cpu";
34			compatible = "arm,cortex-a7";
35			reg = <0xf00>;
36			resets = <&cru SRST_CORE0>;
37			operating-points-v2 = <&cpu0_opp_table>;
38			#cooling-cells = <2>; /* min followed by max */
39			clock-latency = <40000>;
40			clocks = <&cru ARMCLK>;
41			enable-method = "psci";
42		};
43
44		cpu1: cpu@f01 {
45			device_type = "cpu";
46			compatible = "arm,cortex-a7";
47			reg = <0xf01>;
48			resets = <&cru SRST_CORE1>;
49			operating-points-v2 = <&cpu0_opp_table>;
50			#cooling-cells = <2>; /* min followed by max */
51			enable-method = "psci";
52		};
53
54		cpu2: cpu@f02 {
55			device_type = "cpu";
56			compatible = "arm,cortex-a7";
57			reg = <0xf02>;
58			resets = <&cru SRST_CORE2>;
59			operating-points-v2 = <&cpu0_opp_table>;
60			#cooling-cells = <2>; /* min followed by max */
61			enable-method = "psci";
62		};
63
64		cpu3: cpu@f03 {
65			device_type = "cpu";
66			compatible = "arm,cortex-a7";
67			reg = <0xf03>;
68			resets = <&cru SRST_CORE3>;
69			operating-points-v2 = <&cpu0_opp_table>;
70			#cooling-cells = <2>; /* min followed by max */
71			enable-method = "psci";
72		};
73	};
74
75	cpu0_opp_table: opp-table-0 {
76		compatible = "operating-points-v2";
77		opp-shared;
78
79		opp-408000000 {
80			opp-hz = /bits/ 64 <408000000>;
81			opp-microvolt = <950000>;
82			clock-latency-ns = <40000>;
83			opp-suspend;
84		};
85		opp-600000000 {
86			opp-hz = /bits/ 64 <600000000>;
87			opp-microvolt = <975000>;
88		};
89		opp-816000000 {
90			opp-hz = /bits/ 64 <816000000>;
91			opp-microvolt = <1000000>;
92		};
93		opp-1008000000 {
94			opp-hz = /bits/ 64 <1008000000>;
95			opp-microvolt = <1175000>;
96		};
97		opp-1200000000 {
98			opp-hz = /bits/ 64 <1200000000>;
99			opp-microvolt = <1275000>;
100		};
101	};
102
103	arm-pmu {
104		compatible = "arm,cortex-a7-pmu";
105		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
106			     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
107			     <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
108			     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
109		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
110	};
111
112	psci {
113		compatible = "arm,psci-1.0", "arm,psci-0.2";
114		method = "smc";
115	};
116
117	timer {
118		compatible = "arm,armv7-timer";
119		arm,cpu-registers-not-fw-configured;
120		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
121			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
122			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
123			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
124		clock-frequency = <24000000>;
125	};
126
127	xin24m: oscillator {
128		compatible = "fixed-clock";
129		clock-frequency = <24000000>;
130		clock-output-names = "xin24m";
131		#clock-cells = <0>;
132	};
133
134	display_subsystem: display-subsystem {
135		compatible = "rockchip,display-subsystem";
136		ports = <&vop_out>;
137	};
138
139	i2s1: i2s1@100b0000 {
140		compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
141		reg = <0x100b0000 0x4000>;
142		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
143		clock-names = "i2s_clk", "i2s_hclk";
144		clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
145		dmas = <&pdma 14>, <&pdma 15>;
146		dma-names = "tx", "rx";
147		pinctrl-names = "default";
148		pinctrl-0 = <&i2s1_bus>;
149		status = "disabled";
150	};
151
152	i2s0: i2s0@100c0000 {
153		compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
154		reg = <0x100c0000 0x4000>;
155		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
156		clock-names = "i2s_clk", "i2s_hclk";
157		clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
158		dmas = <&pdma 11>, <&pdma 12>;
159		dma-names = "tx", "rx";
160		status = "disabled";
161	};
162
163	spdif: spdif@100d0000 {
164		compatible = "rockchip,rk3228-spdif";
165		reg = <0x100d0000 0x1000>;
166		interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
167		clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
168		clock-names = "mclk", "hclk";
169		dmas = <&pdma 10>;
170		dma-names = "tx";
171		pinctrl-names = "default";
172		pinctrl-0 = <&spdif_tx>;
173		status = "disabled";
174	};
175
176	i2s2: i2s2@100e0000 {
177		compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
178		reg = <0x100e0000 0x4000>;
179		interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
180		clock-names = "i2s_clk", "i2s_hclk";
181		clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
182		dmas = <&pdma 0>, <&pdma 1>;
183		dma-names = "tx", "rx";
184		status = "disabled";
185	};
186
187	grf: syscon@11000000 {
188		compatible = "rockchip,rk3228-grf", "syscon", "simple-mfd";
189		reg = <0x11000000 0x1000>;
190		#address-cells = <1>;
191		#size-cells = <1>;
192
193		io_domains: io-domains {
194			compatible = "rockchip,rk3228-io-voltage-domain";
195			status = "disabled";
196		};
197
198		power: power-controller {
199			compatible = "rockchip,rk3228-power-controller";
200			#power-domain-cells = <1>;
201			#address-cells = <1>;
202			#size-cells = <0>;
203
204			power-domain@RK3228_PD_VIO {
205				reg = <RK3228_PD_VIO>;
206				clocks = <&cru ACLK_HDCP>,
207					 <&cru SCLK_HDCP>,
208					 <&cru ACLK_IEP>,
209					 <&cru HCLK_IEP>,
210					 <&cru ACLK_RGA>,
211					 <&cru HCLK_RGA>,
212					 <&cru SCLK_RGA>;
213				pm_qos = <&qos_hdcp>,
214					 <&qos_iep>,
215					 <&qos_rga_r>,
216					 <&qos_rga_w>;
217				#power-domain-cells = <0>;
218			};
219
220			power-domain@RK3228_PD_VOP {
221				reg = <RK3228_PD_VOP>;
222				clocks = <&cru ACLK_VOP>,
223					 <&cru DCLK_VOP>,
224					 <&cru HCLK_VOP>;
225				pm_qos = <&qos_vop>;
226				#power-domain-cells = <0>;
227			};
228
229			power-domain@RK3228_PD_VPU {
230				reg = <RK3228_PD_VPU>;
231				clocks = <&cru ACLK_VPU>,
232					 <&cru HCLK_VPU>;
233				pm_qos = <&qos_vpu>;
234				#power-domain-cells = <0>;
235			};
236
237			power-domain@RK3228_PD_RKVDEC {
238				reg = <RK3228_PD_RKVDEC>;
239				clocks = <&cru ACLK_RKVDEC>,
240					 <&cru HCLK_RKVDEC>,
241					 <&cru SCLK_VDEC_CABAC>,
242					 <&cru SCLK_VDEC_CORE>;
243				pm_qos = <&qos_rkvdec_r>,
244					 <&qos_rkvdec_w>;
245				#power-domain-cells = <0>;
246			};
247
248			power-domain@RK3228_PD_GPU {
249				reg = <RK3228_PD_GPU>;
250				clocks = <&cru ACLK_GPU>;
251				pm_qos = <&qos_gpu>;
252				#power-domain-cells = <0>;
253			};
254		};
255
256		u2phy0: usb2phy@760 {
257			compatible = "rockchip,rk3228-usb2phy";
258			reg = <0x0760 0x0c>;
259			clocks = <&cru SCLK_OTGPHY0>;
260			clock-names = "phyclk";
261			clock-output-names = "usb480m_phy0";
262			#clock-cells = <0>;
263			status = "disabled";
264
265			u2phy0_otg: otg-port {
266				interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
267					     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
268					     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
269				interrupt-names = "otg-bvalid", "otg-id",
270						  "linestate";
271				#phy-cells = <0>;
272				status = "disabled";
273			};
274
275			u2phy0_host: host-port {
276				interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
277				interrupt-names = "linestate";
278				#phy-cells = <0>;
279				status = "disabled";
280			};
281		};
282
283		u2phy1: usb2phy@800 {
284			compatible = "rockchip,rk3228-usb2phy";
285			reg = <0x0800 0x0c>;
286			clocks = <&cru SCLK_OTGPHY1>;
287			clock-names = "phyclk";
288			clock-output-names = "usb480m_phy1";
289			#clock-cells = <0>;
290			status = "disabled";
291
292			u2phy1_otg: otg-port {
293				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
294				interrupt-names = "linestate";
295				#phy-cells = <0>;
296				status = "disabled";
297			};
298
299			u2phy1_host: host-port {
300				interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
301				interrupt-names = "linestate";
302				#phy-cells = <0>;
303				status = "disabled";
304			};
305		};
306	};
307
308	uart0: serial@11010000 {
309		compatible = "snps,dw-apb-uart";
310		reg = <0x11010000 0x100>;
311		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
312		clock-frequency = <24000000>;
313		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
314		clock-names = "baudclk", "apb_pclk";
315		pinctrl-names = "default";
316		pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
317		reg-shift = <2>;
318		reg-io-width = <4>;
319		status = "disabled";
320	};
321
322	uart1: serial@11020000 {
323		compatible = "snps,dw-apb-uart";
324		reg = <0x11020000 0x100>;
325		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
326		clock-frequency = <24000000>;
327		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
328		clock-names = "baudclk", "apb_pclk";
329		pinctrl-names = "default";
330		pinctrl-0 = <&uart1_xfer>;
331		reg-shift = <2>;
332		reg-io-width = <4>;
333		status = "disabled";
334	};
335
336	uart2: serial@11030000 {
337		compatible = "snps,dw-apb-uart";
338		reg = <0x11030000 0x100>;
339		interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
340		clock-frequency = <24000000>;
341		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
342		clock-names = "baudclk", "apb_pclk";
343		pinctrl-names = "default";
344		pinctrl-0 = <&uart2_xfer>;
345		reg-shift = <2>;
346		reg-io-width = <4>;
347		status = "disabled";
348	};
349
350	efuse: efuse@11040000 {
351		compatible = "rockchip,rk3228-efuse";
352		reg = <0x11040000 0x20>;
353		clocks = <&cru PCLK_EFUSE_256>;
354		clock-names = "pclk_efuse";
355		#address-cells = <1>;
356		#size-cells = <1>;
357
358		/* Data cells */
359		efuse_id: id@7 {
360			reg = <0x7 0x10>;
361		};
362		cpu_leakage: cpu_leakage@17 {
363			reg = <0x17 0x1>;
364		};
365	};
366
367	i2c0: i2c@11050000 {
368		compatible = "rockchip,rk3228-i2c";
369		reg = <0x11050000 0x1000>;
370		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
371		#address-cells = <1>;
372		#size-cells = <0>;
373		clock-names = "i2c";
374		clocks = <&cru PCLK_I2C0>;
375		pinctrl-names = "default";
376		pinctrl-0 = <&i2c0_xfer>;
377		status = "disabled";
378	};
379
380	i2c1: i2c@11060000 {
381		compatible = "rockchip,rk3228-i2c";
382		reg = <0x11060000 0x1000>;
383		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
384		#address-cells = <1>;
385		#size-cells = <0>;
386		clock-names = "i2c";
387		clocks = <&cru PCLK_I2C1>;
388		pinctrl-names = "default";
389		pinctrl-0 = <&i2c1_xfer>;
390		status = "disabled";
391	};
392
393	i2c2: i2c@11070000 {
394		compatible = "rockchip,rk3228-i2c";
395		reg = <0x11070000 0x1000>;
396		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
397		#address-cells = <1>;
398		#size-cells = <0>;
399		clock-names = "i2c";
400		clocks = <&cru PCLK_I2C2>;
401		pinctrl-names = "default";
402		pinctrl-0 = <&i2c2_xfer>;
403		status = "disabled";
404	};
405
406	i2c3: i2c@11080000 {
407		compatible = "rockchip,rk3228-i2c";
408		reg = <0x11080000 0x1000>;
409		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
410		#address-cells = <1>;
411		#size-cells = <0>;
412		clock-names = "i2c";
413		clocks = <&cru PCLK_I2C3>;
414		pinctrl-names = "default";
415		pinctrl-0 = <&i2c3_xfer>;
416		status = "disabled";
417	};
418
419	spi0: spi@11090000 {
420		compatible = "rockchip,rk3228-spi";
421		reg = <0x11090000 0x1000>;
422		interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
423		#address-cells = <1>;
424		#size-cells = <0>;
425		clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
426		clock-names = "spiclk", "apb_pclk";
427		pinctrl-names = "default";
428		pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
429		status = "disabled";
430	};
431
432	wdt: watchdog@110a0000 {
433		compatible = "rockchip,rk3228-wdt", "snps,dw-wdt";
434		reg = <0x110a0000 0x100>;
435		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
436		clocks = <&cru PCLK_CPU>;
437		status = "disabled";
438	};
439
440	pwm0: pwm@110b0000 {
441		compatible = "rockchip,rk3288-pwm";
442		reg = <0x110b0000 0x10>;
443		#pwm-cells = <3>;
444		clocks = <&cru PCLK_PWM>;
445		pinctrl-names = "default";
446		pinctrl-0 = <&pwm0_pin>;
447		status = "disabled";
448	};
449
450	pwm1: pwm@110b0010 {
451		compatible = "rockchip,rk3288-pwm";
452		reg = <0x110b0010 0x10>;
453		#pwm-cells = <3>;
454		clocks = <&cru PCLK_PWM>;
455		pinctrl-names = "default";
456		pinctrl-0 = <&pwm1_pin>;
457		status = "disabled";
458	};
459
460	pwm2: pwm@110b0020 {
461		compatible = "rockchip,rk3288-pwm";
462		reg = <0x110b0020 0x10>;
463		#pwm-cells = <3>;
464		clocks = <&cru PCLK_PWM>;
465		pinctrl-names = "default";
466		pinctrl-0 = <&pwm2_pin>;
467		status = "disabled";
468	};
469
470	pwm3: pwm@110b0030 {
471		compatible = "rockchip,rk3288-pwm";
472		reg = <0x110b0030 0x10>;
473		#pwm-cells = <2>;
474		clocks = <&cru PCLK_PWM>;
475		pinctrl-names = "default";
476		pinctrl-0 = <&pwm3_pin>;
477		status = "disabled";
478	};
479
480	timer: timer@110c0000 {
481		compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer";
482		reg = <0x110c0000 0x20>;
483		interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
484		clocks = <&cru PCLK_TIMER>, <&xin24m>;
485		clock-names = "pclk", "timer";
486	};
487
488	cru: clock-controller@110e0000 {
489		compatible = "rockchip,rk3228-cru";
490		reg = <0x110e0000 0x1000>;
491		clocks = <&xin24m>;
492		clock-names = "xin24m";
493		rockchip,grf = <&grf>;
494		#clock-cells = <1>;
495		#reset-cells = <1>;
496		assigned-clocks =
497			<&cru PLL_GPLL>, <&cru ARMCLK>,
498			<&cru PLL_CPLL>, <&cru ACLK_PERI>,
499			<&cru HCLK_PERI>, <&cru PCLK_PERI>,
500			<&cru ACLK_CPU>, <&cru HCLK_CPU>,
501			<&cru PCLK_CPU>;
502		assigned-clock-rates =
503			<594000000>, <816000000>,
504			<500000000>, <150000000>,
505			<150000000>, <75000000>,
506			<150000000>, <150000000>,
507			<75000000>;
508	};
509
510	pdma: dma-controller@110f0000 {
511		compatible = "arm,pl330", "arm,primecell";
512		reg = <0x110f0000 0x4000>;
513		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
514			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
515		#dma-cells = <1>;
516		arm,pl330-periph-burst;
517		clocks = <&cru ACLK_DMAC>;
518		clock-names = "apb_pclk";
519	};
520
521	thermal-zones {
522		cpu_thermal: cpu-thermal {
523			polling-delay-passive = <100>; /* milliseconds */
524			polling-delay = <5000>; /* milliseconds */
525
526			thermal-sensors = <&tsadc 0>;
527
528			trips {
529				cpu_alert0: cpu_alert0 {
530					temperature = <70000>; /* millicelsius */
531					hysteresis = <2000>; /* millicelsius */
532					type = "passive";
533				};
534				cpu_alert1: cpu_alert1 {
535					temperature = <75000>; /* millicelsius */
536					hysteresis = <2000>; /* millicelsius */
537					type = "passive";
538				};
539				cpu_crit: cpu_crit {
540					temperature = <90000>; /* millicelsius */
541					hysteresis = <2000>; /* millicelsius */
542					type = "critical";
543				};
544			};
545
546			cooling-maps {
547				map0 {
548					trip = <&cpu_alert0>;
549					cooling-device =
550						<&cpu0 THERMAL_NO_LIMIT 6>,
551						<&cpu1 THERMAL_NO_LIMIT 6>,
552						<&cpu2 THERMAL_NO_LIMIT 6>,
553						<&cpu3 THERMAL_NO_LIMIT 6>;
554				};
555				map1 {
556					trip = <&cpu_alert1>;
557					cooling-device =
558						<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
559						<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
560						<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
561						<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
562				};
563			};
564		};
565	};
566
567	tsadc: tsadc@11150000 {
568		compatible = "rockchip,rk3228-tsadc";
569		reg = <0x11150000 0x100>;
570		interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
571		clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
572		clock-names = "tsadc", "apb_pclk";
573		assigned-clocks = <&cru SCLK_TSADC>;
574		assigned-clock-rates = <32768>;
575		resets = <&cru SRST_TSADC>;
576		reset-names = "tsadc-apb";
577		pinctrl-names = "init", "default", "sleep";
578		pinctrl-0 = <&otp_pin>;
579		pinctrl-1 = <&otp_out>;
580		pinctrl-2 = <&otp_pin>;
581		#thermal-sensor-cells = <1>;
582		rockchip,hw-tshut-temp = <95000>;
583		status = "disabled";
584	};
585
586	hdmi_phy: hdmi-phy@12030000 {
587		compatible = "rockchip,rk3228-hdmi-phy";
588		reg = <0x12030000 0x10000>;
589		clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>, <&cru DCLK_HDMI_PHY>;
590		clock-names = "sysclk", "refoclk", "refpclk";
591		#clock-cells = <0>;
592		clock-output-names = "hdmiphy_phy";
593		#phy-cells = <0>;
594		status = "disabled";
595	};
596
597	gpu: gpu@20000000 {
598		compatible = "rockchip,rk3228-mali", "arm,mali-400";
599		reg = <0x20000000 0x10000>;
600		interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
601			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
602			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
603			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
604			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
605			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
606		interrupt-names = "gp",
607				  "gpmmu",
608				  "pp0",
609				  "ppmmu0",
610				  "pp1",
611				  "ppmmu1";
612		clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
613		clock-names = "bus", "core";
614		power-domains = <&power RK3228_PD_GPU>;
615		resets = <&cru SRST_GPU_A>;
616		status = "disabled";
617	};
618
619	vpu: video-codec@20020000 {
620		compatible = "rockchip,rk3228-vpu", "rockchip,rk3399-vpu";
621		reg = <0x20020000 0x800>;
622		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
623			     <GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>;
624		interrupt-names = "vepu", "vdpu";
625		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
626		clock-names = "aclk", "hclk";
627		iommus = <&vpu_mmu>;
628		power-domains = <&power RK3228_PD_VPU>;
629	};
630
631	vpu_mmu: iommu@20020800 {
632		compatible = "rockchip,iommu";
633		reg = <0x20020800 0x100>;
634		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
635		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
636		clock-names = "aclk", "iface";
637		power-domains = <&power RK3228_PD_VPU>;
638		#iommu-cells = <0>;
639	};
640
641	vdec: video-codec@20030000 {
642		compatible = "rockchip,rk3228-vdec", "rockchip,rk3399-vdec";
643		reg = <0x20030000 0x480>;
644		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
645		clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,
646			 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
647		clock-names = "axi", "ahb", "cabac", "core";
648		assigned-clocks = <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
649		assigned-clock-rates = <300000000>, <300000000>;
650		iommus = <&vdec_mmu>;
651		power-domains = <&power RK3228_PD_RKVDEC>;
652	};
653
654	vdec_mmu: iommu@20030480 {
655		compatible = "rockchip,iommu";
656		reg = <0x20030480 0x40>, <0x200304c0 0x40>;
657		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
658		clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
659		clock-names = "aclk", "iface";
660		power-domains = <&power RK3228_PD_RKVDEC>;
661		#iommu-cells = <0>;
662	};
663
664	vop: vop@20050000 {
665		compatible = "rockchip,rk3228-vop";
666		reg = <0x20050000 0x1ffc>;
667		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
668		clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
669		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
670		resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
671		reset-names = "axi", "ahb", "dclk";
672		iommus = <&vop_mmu>;
673		power-domains = <&power RK3228_PD_VOP>;
674		status = "disabled";
675
676		vop_out: port {
677			#address-cells = <1>;
678			#size-cells = <0>;
679
680			vop_out_hdmi: endpoint@0 {
681				reg = <0>;
682				remote-endpoint = <&hdmi_in_vop>;
683			};
684		};
685	};
686
687	vop_mmu: iommu@20053f00 {
688		compatible = "rockchip,iommu";
689		reg = <0x20053f00 0x100>;
690		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
691		clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
692		clock-names = "aclk", "iface";
693		power-domains = <&power RK3228_PD_VOP>;
694		#iommu-cells = <0>;
695		status = "disabled";
696	};
697
698	rga: rga@20060000 {
699		compatible = "rockchip,rk3228-rga", "rockchip,rk3288-rga";
700		reg = <0x20060000 0x1000>;
701		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
702		clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
703		clock-names = "aclk", "hclk", "sclk";
704		power-domains = <&power RK3228_PD_VIO>;
705		resets = <&cru SRST_RGA>, <&cru SRST_RGA_A>, <&cru SRST_RGA_H>;
706		reset-names = "core", "axi", "ahb";
707	};
708
709	iep_mmu: iommu@20070800 {
710		compatible = "rockchip,iommu";
711		reg = <0x20070800 0x100>;
712		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
713		clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
714		clock-names = "aclk", "iface";
715		power-domains = <&power RK3228_PD_VIO>;
716		#iommu-cells = <0>;
717		status = "disabled";
718	};
719
720	hdmi: hdmi@200a0000 {
721		compatible = "rockchip,rk3228-dw-hdmi";
722		reg = <0x200a0000 0x20000>;
723		reg-io-width = <4>;
724		interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
725		assigned-clocks = <&cru SCLK_HDMI_PHY>;
726		assigned-clock-parents = <&hdmi_phy>;
727		clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
728		clock-names = "iahb", "isfr", "cec";
729		pinctrl-names = "default";
730		pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>;
731		resets = <&cru SRST_HDMI_P>;
732		reset-names = "hdmi";
733		phys = <&hdmi_phy>;
734		phy-names = "hdmi";
735		rockchip,grf = <&grf>;
736		status = "disabled";
737
738		ports {
739			hdmi_in: port {
740				#address-cells = <1>;
741				#size-cells = <0>;
742				hdmi_in_vop: endpoint@0 {
743					reg = <0>;
744					remote-endpoint = <&vop_out_hdmi>;
745				};
746			};
747		};
748	};
749
750	sdmmc: mmc@30000000 {
751		compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
752		reg = <0x30000000 0x4000>;
753		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
754		clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
755			 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
756		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
757		fifo-depth = <0x100>;
758		pinctrl-names = "default";
759		pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
760		status = "disabled";
761	};
762
763	sdio: mmc@30010000 {
764		compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
765		reg = <0x30010000 0x4000>;
766		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
767		clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
768			 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
769		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
770		fifo-depth = <0x100>;
771		pinctrl-names = "default";
772		pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
773		status = "disabled";
774	};
775
776	emmc: mmc@30020000 {
777		compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
778		reg = <0x30020000 0x4000>;
779		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
780		clock-frequency = <37500000>;
781		max-frequency = <37500000>;
782		clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
783			 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
784		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
785		bus-width = <8>;
786		rockchip,default-sample-phase = <158>;
787		fifo-depth = <0x100>;
788		pinctrl-names = "default";
789		pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
790		resets = <&cru SRST_EMMC>;
791		reset-names = "reset";
792		status = "disabled";
793	};
794
795	usb_otg: usb@30040000 {
796		compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb",
797			     "snps,dwc2";
798		reg = <0x30040000 0x40000>;
799		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
800		clocks = <&cru HCLK_OTG>;
801		clock-names = "otg";
802		dr_mode = "otg";
803		g-np-tx-fifo-size = <16>;
804		g-rx-fifo-size = <280>;
805		g-tx-fifo-size = <256 128 128 64 32 16>;
806		phys = <&u2phy0_otg>;
807		phy-names = "usb2-phy";
808		status = "disabled";
809	};
810
811	usb_host0_ehci: usb@30080000 {
812		compatible = "generic-ehci";
813		reg = <0x30080000 0x20000>;
814		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
815		clocks = <&cru HCLK_HOST0>, <&u2phy0>;
816		phys = <&u2phy0_host>;
817		phy-names = "usb";
818		status = "disabled";
819	};
820
821	usb_host0_ohci: usb@300a0000 {
822		compatible = "generic-ohci";
823		reg = <0x300a0000 0x20000>;
824		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
825		clocks = <&cru HCLK_HOST0>, <&u2phy0>;
826		phys = <&u2phy0_host>;
827		phy-names = "usb";
828		status = "disabled";
829	};
830
831	usb_host1_ehci: usb@300c0000 {
832		compatible = "generic-ehci";
833		reg = <0x300c0000 0x20000>;
834		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
835		clocks = <&cru HCLK_HOST1>, <&u2phy1>;
836		phys = <&u2phy1_otg>;
837		phy-names = "usb";
838		status = "disabled";
839	};
840
841	usb_host1_ohci: usb@300e0000 {
842		compatible = "generic-ohci";
843		reg = <0x300e0000 0x20000>;
844		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
845		clocks = <&cru HCLK_HOST1>, <&u2phy1>;
846		phys = <&u2phy1_otg>;
847		phy-names = "usb";
848		status = "disabled";
849	};
850
851	usb_host2_ehci: usb@30100000 {
852		compatible = "generic-ehci";
853		reg = <0x30100000 0x20000>;
854		interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
855		clocks = <&cru HCLK_HOST2>, <&u2phy1>;
856		phys = <&u2phy1_host>;
857		phy-names = "usb";
858		status = "disabled";
859	};
860
861	usb_host2_ohci: usb@30120000 {
862		compatible = "generic-ohci";
863		reg = <0x30120000 0x20000>;
864		interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
865		clocks = <&cru HCLK_HOST2>, <&u2phy1>;
866		phys = <&u2phy1_host>;
867		phy-names = "usb";
868		status = "disabled";
869	};
870
871	gmac: ethernet@30200000 {
872		compatible = "rockchip,rk3228-gmac";
873		reg = <0x30200000 0x10000>;
874		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
875		interrupt-names = "macirq";
876		clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
877			<&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
878			<&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
879			<&cru PCLK_GMAC>;
880		clock-names = "stmmaceth", "mac_clk_rx",
881			"mac_clk_tx", "clk_mac_ref",
882			"clk_mac_refout", "aclk_mac",
883			"pclk_mac";
884		resets = <&cru SRST_GMAC>;
885		reset-names = "stmmaceth";
886		rockchip,grf = <&grf>;
887		status = "disabled";
888	};
889
890	qos_iep: qos@31030080 {
891		compatible = "rockchip,rk3228-qos", "syscon";
892		reg = <0x31030080 0x20>;
893	};
894
895	qos_rga_w: qos@31030100 {
896		compatible = "rockchip,rk3228-qos", "syscon";
897		reg = <0x31030100 0x20>;
898	};
899
900	qos_hdcp: qos@31030180 {
901		compatible = "rockchip,rk3228-qos", "syscon";
902		reg = <0x31030180 0x20>;
903	};
904
905	qos_rga_r: qos@31030200 {
906		compatible = "rockchip,rk3228-qos", "syscon";
907		reg = <0x31030200 0x20>;
908	};
909
910	qos_vpu: qos@31040000 {
911		compatible = "rockchip,rk3228-qos", "syscon";
912		reg = <0x31040000 0x20>;
913	};
914
915	qos_gpu: qos@31050000 {
916		compatible = "rockchip,rk3228-qos", "syscon";
917		reg = <0x31050000 0x20>;
918	};
919
920	qos_vop: qos@31060000 {
921		compatible = "rockchip,rk3228-qos", "syscon";
922		reg = <0x31060000 0x20>;
923	};
924
925	qos_rkvdec_r: qos@31070000 {
926		compatible = "rockchip,rk3228-qos", "syscon";
927		reg = <0x31070000 0x20>;
928	};
929
930	qos_rkvdec_w: qos@31070080 {
931		compatible = "rockchip,rk3228-qos", "syscon";
932		reg = <0x31070080 0x20>;
933	};
934
935	gic: interrupt-controller@32010000 {
936		compatible = "arm,gic-400";
937		interrupt-controller;
938		#interrupt-cells = <3>;
939		#address-cells = <0>;
940
941		reg = <0x32011000 0x1000>,
942		      <0x32012000 0x2000>,
943		      <0x32014000 0x2000>,
944		      <0x32016000 0x2000>;
945		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
946	};
947
948	pinctrl: pinctrl {
949		compatible = "rockchip,rk3228-pinctrl";
950		rockchip,grf = <&grf>;
951		#address-cells = <1>;
952		#size-cells = <1>;
953		ranges;
954
955		gpio0: gpio@11110000 {
956			compatible = "rockchip,gpio-bank";
957			reg = <0x11110000 0x100>;
958			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
959			clocks = <&cru PCLK_GPIO0>;
960
961			gpio-controller;
962			#gpio-cells = <2>;
963
964			interrupt-controller;
965			#interrupt-cells = <2>;
966		};
967
968		gpio1: gpio@11120000 {
969			compatible = "rockchip,gpio-bank";
970			reg = <0x11120000 0x100>;
971			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
972			clocks = <&cru PCLK_GPIO1>;
973
974			gpio-controller;
975			#gpio-cells = <2>;
976
977			interrupt-controller;
978			#interrupt-cells = <2>;
979		};
980
981		gpio2: gpio@11130000 {
982			compatible = "rockchip,gpio-bank";
983			reg = <0x11130000 0x100>;
984			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
985			clocks = <&cru PCLK_GPIO2>;
986
987			gpio-controller;
988			#gpio-cells = <2>;
989
990			interrupt-controller;
991			#interrupt-cells = <2>;
992		};
993
994		gpio3: gpio@11140000 {
995			compatible = "rockchip,gpio-bank";
996			reg = <0x11140000 0x100>;
997			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
998			clocks = <&cru PCLK_GPIO3>;
999
1000			gpio-controller;
1001			#gpio-cells = <2>;
1002
1003			interrupt-controller;
1004			#interrupt-cells = <2>;
1005		};
1006
1007		pcfg_pull_up: pcfg-pull-up {
1008			bias-pull-up;
1009		};
1010
1011		pcfg_pull_down: pcfg-pull-down {
1012			bias-pull-down;
1013		};
1014
1015		pcfg_pull_none: pcfg-pull-none {
1016			bias-disable;
1017		};
1018
1019		pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
1020			drive-strength = <12>;
1021		};
1022
1023		sdmmc {
1024			sdmmc_clk: sdmmc-clk {
1025				rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none_drv_12ma>;
1026			};
1027
1028			sdmmc_cmd: sdmmc-cmd {
1029				rockchip,pins = <1 RK_PB7 1 &pcfg_pull_none_drv_12ma>;
1030			};
1031
1032			sdmmc_bus4: sdmmc-bus4 {
1033				rockchip,pins = <1 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
1034						<1 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
1035						<1 RK_PC4 1 &pcfg_pull_none_drv_12ma>,
1036						<1 RK_PC5 1 &pcfg_pull_none_drv_12ma>;
1037			};
1038		};
1039
1040		sdio {
1041			sdio_clk: sdio-clk {
1042				rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none_drv_12ma>;
1043			};
1044
1045			sdio_cmd: sdio-cmd {
1046				rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none_drv_12ma>;
1047			};
1048
1049			sdio_bus4: sdio-bus4 {
1050				rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none_drv_12ma>,
1051						<3 RK_PA3 1 &pcfg_pull_none_drv_12ma>,
1052						<3 RK_PA4 1 &pcfg_pull_none_drv_12ma>,
1053						<3 RK_PA5 1 &pcfg_pull_none_drv_12ma>;
1054			};
1055		};
1056
1057		emmc {
1058			emmc_clk: emmc-clk {
1059				rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>;
1060			};
1061
1062			emmc_cmd: emmc-cmd {
1063				rockchip,pins = <1 RK_PC6 2 &pcfg_pull_none>;
1064			};
1065
1066			emmc_bus8: emmc-bus8 {
1067				rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>,
1068						<1 RK_PD1 2 &pcfg_pull_none>,
1069						<1 RK_PD2 2 &pcfg_pull_none>,
1070						<1 RK_PD3 2 &pcfg_pull_none>,
1071						<1 RK_PD4 2 &pcfg_pull_none>,
1072						<1 RK_PD5 2 &pcfg_pull_none>,
1073						<1 RK_PD6 2 &pcfg_pull_none>,
1074						<1 RK_PD7 2 &pcfg_pull_none>;
1075			};
1076		};
1077
1078		gmac {
1079			rgmii_pins: rgmii-pins {
1080				rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>,
1081						<2 RK_PB4 1 &pcfg_pull_none>,
1082						<2 RK_PD1 1 &pcfg_pull_none>,
1083						<2 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
1084						<2 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
1085						<2 RK_PC6 1 &pcfg_pull_none_drv_12ma>,
1086						<2 RK_PC7 1 &pcfg_pull_none_drv_12ma>,
1087						<2 RK_PB1 1 &pcfg_pull_none_drv_12ma>,
1088						<2 RK_PB5 1 &pcfg_pull_none_drv_12ma>,
1089						<2 RK_PC1 1 &pcfg_pull_none>,
1090						<2 RK_PC0 1 &pcfg_pull_none>,
1091						<2 RK_PC5 2 &pcfg_pull_none>,
1092						<2 RK_PC4 2 &pcfg_pull_none>,
1093						<2 RK_PB3 1 &pcfg_pull_none>,
1094						<2 RK_PB0 1 &pcfg_pull_none>;
1095			};
1096
1097			rmii_pins: rmii-pins {
1098				rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>,
1099						<2 RK_PB4 1 &pcfg_pull_none>,
1100						<2 RK_PD1 1 &pcfg_pull_none>,
1101						<2 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
1102						<2 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
1103						<2 RK_PB5 1 &pcfg_pull_none_drv_12ma>,
1104						<2 RK_PC1 1 &pcfg_pull_none>,
1105						<2 RK_PC0 1 &pcfg_pull_none>,
1106						<2 RK_PB0 1 &pcfg_pull_none>,
1107						<2 RK_PB7 1 &pcfg_pull_none>;
1108			};
1109
1110			phy_pins: phy-pins {
1111				rockchip,pins = <2 RK_PB6 2 &pcfg_pull_none>,
1112						<2 RK_PB0 2 &pcfg_pull_none>;
1113			};
1114		};
1115
1116		hdmi {
1117			hdmi_hpd: hdmi-hpd {
1118				rockchip,pins = <0 RK_PB7 1 &pcfg_pull_down>;
1119			};
1120
1121			hdmii2c_xfer: hdmii2c-xfer {
1122				rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>,
1123						<0 RK_PA7 2 &pcfg_pull_none>;
1124			};
1125
1126			hdmi_cec: hdmi-cec {
1127				rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
1128			};
1129		};
1130
1131		i2c0 {
1132			i2c0_xfer: i2c0-xfer {
1133				rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
1134						<0 RK_PA1 1 &pcfg_pull_none>;
1135			};
1136		};
1137
1138		i2c1 {
1139			i2c1_xfer: i2c1-xfer {
1140				rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
1141						<0 RK_PA3 1 &pcfg_pull_none>;
1142			};
1143		};
1144
1145		i2c2 {
1146			i2c2_xfer: i2c2-xfer {
1147				rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>,
1148						<2 RK_PC5 1 &pcfg_pull_none>;
1149			};
1150		};
1151
1152		i2c3 {
1153			i2c3_xfer: i2c3-xfer {
1154				rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
1155						<0 RK_PA7 1 &pcfg_pull_none>;
1156			};
1157		};
1158
1159		spi0 {
1160			spi0_clk: spi0-clk {
1161				rockchip,pins = <0 RK_PB1 2 &pcfg_pull_up>;
1162			};
1163			spi0_cs0: spi0-cs0 {
1164				rockchip,pins = <0 RK_PB6 2 &pcfg_pull_up>;
1165			};
1166			spi0_tx: spi0-tx {
1167				rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>;
1168			};
1169			spi0_rx: spi0-rx {
1170				rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>;
1171			};
1172			spi0_cs1: spi0-cs1 {
1173				rockchip,pins = <1 RK_PB4 1 &pcfg_pull_up>;
1174			};
1175		};
1176
1177		spi1 {
1178			spi1_clk: spi1-clk {
1179				rockchip,pins = <0 RK_PC7 2 &pcfg_pull_up>;
1180			};
1181			spi1_cs0: spi1-cs0 {
1182				rockchip,pins = <2 RK_PA2 2 &pcfg_pull_up>;
1183			};
1184			spi1_rx: spi1-rx {
1185				rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up>;
1186			};
1187			spi1_tx: spi1-tx {
1188				rockchip,pins = <2 RK_PA1 2 &pcfg_pull_up>;
1189			};
1190			spi1_cs1: spi1-cs1 {
1191				rockchip,pins = <2 RK_PA3 2 &pcfg_pull_up>;
1192			};
1193		};
1194
1195		i2s1 {
1196			i2s1_bus: i2s1-bus {
1197				rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>,
1198						<0 RK_PB1 1 &pcfg_pull_none>,
1199						<0 RK_PB3 1 &pcfg_pull_none>,
1200						<0 RK_PB4 1 &pcfg_pull_none>,
1201						<0 RK_PB5 1 &pcfg_pull_none>,
1202						<0 RK_PB6 1 &pcfg_pull_none>,
1203						<1 RK_PA2 2 &pcfg_pull_none>,
1204						<1 RK_PA4 2 &pcfg_pull_none>,
1205						<1 RK_PA5 2 &pcfg_pull_none>;
1206			};
1207		};
1208
1209		pwm0 {
1210			pwm0_pin: pwm0-pin {
1211				rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>;
1212			};
1213		};
1214
1215		pwm1 {
1216			pwm1_pin: pwm1-pin {
1217				rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
1218			};
1219		};
1220
1221		pwm2 {
1222			pwm2_pin: pwm2-pin {
1223				rockchip,pins = <1 RK_PB4 2 &pcfg_pull_none>;
1224			};
1225		};
1226
1227		pwm3 {
1228			pwm3_pin: pwm3-pin {
1229				rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>;
1230			};
1231		};
1232
1233		spdif {
1234			spdif_tx: spdif-tx {
1235				rockchip,pins = <3 RK_PD7 2 &pcfg_pull_none>;
1236			};
1237		};
1238
1239		tsadc {
1240			otp_pin: otp-pin {
1241				rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
1242			};
1243
1244			otp_out: otp-out {
1245				rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>;
1246			};
1247		};
1248
1249		uart0 {
1250			uart0_xfer: uart0-xfer {
1251				rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>,
1252						<2 RK_PD3 1 &pcfg_pull_none>;
1253			};
1254
1255			uart0_cts: uart0-cts {
1256				rockchip,pins = <2 RK_PD5 1 &pcfg_pull_none>;
1257			};
1258
1259			uart0_rts: uart0-rts {
1260				rockchip,pins = <0 RK_PC1 1 &pcfg_pull_none>;
1261			};
1262		};
1263
1264		uart1 {
1265			uart1_xfer: uart1-xfer {
1266				rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>,
1267						<1 RK_PB2 1 &pcfg_pull_none>;
1268			};
1269
1270			uart1_cts: uart1-cts {
1271				rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>;
1272			};
1273
1274			uart1_rts: uart1-rts {
1275				rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
1276			};
1277		};
1278
1279		uart2 {
1280			uart2_xfer: uart2-xfer {
1281				rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
1282						<1 RK_PC3 2 &pcfg_pull_none>;
1283			};
1284
1285			uart21_xfer: uart21-xfer {
1286				rockchip,pins = <1 RK_PB2 2 &pcfg_pull_up>,
1287						<1 RK_PB1 2 &pcfg_pull_none>;
1288			};
1289
1290			uart2_cts: uart2-cts {
1291				rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>;
1292			};
1293
1294			uart2_rts: uart2-rts {
1295				rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>;
1296			};
1297		};
1298	};
1299};
1300