xref: /freebsd/sys/riscv/riscv/cbo.c (revision 81e2d24bc6ea3edaa0338ea6020c2eb9f93de0ed)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
3  *
4  * Copyright (c) 2025 Ruslan Bukin <br@bsdpad.com>
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  */
27 
28 /* Cache Block Operations. */
29 
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 
33 #include <machine/cbo.h>
34 
35 static void
cbo_zicbom_cpu_dcache_wbinv_range(vm_offset_t va,vm_size_t len)36 cbo_zicbom_cpu_dcache_wbinv_range(vm_offset_t va, vm_size_t len)
37 {
38 	vm_offset_t addr;
39 
40 	/*
41 	 * A flush operation atomically performs a clean operation followed by
42 	 * an invalidate operation.
43 	 */
44 
45 	va &= ~(dcache_line_size - 1);
46 	for (addr = va; addr < va + len; addr += dcache_line_size)
47 		__asm __volatile(".option push; .option arch, +zicbom\n"
48 				 "cbo.flush (%0); .option pop\n" :: "r"(addr));
49 }
50 
51 static void
cbo_zicbom_cpu_dcache_inv_range(vm_offset_t va,vm_size_t len)52 cbo_zicbom_cpu_dcache_inv_range(vm_offset_t va, vm_size_t len)
53 {
54 	vm_offset_t addr;
55 
56 	/*
57 	 * An invalidate operation makes data from store operations performed by
58 	 * a set of non-coherent agents visible to the set of coherent agents at
59 	 * a point common to both sets by deallocating all copies of a cache
60 	 * block from the set of coherent caches up to that point.
61 	 */
62 
63 	va &= ~(dcache_line_size - 1);
64 	for (addr = va; addr < va + len; addr += dcache_line_size)
65 		__asm __volatile(".option push; .option arch, +zicbom\n"
66 				 "cbo.inval (%0); .option pop\n" :: "r"(addr));
67 }
68 
69 static void
cbo_zicbom_cpu_dcache_wb_range(vm_offset_t va,vm_size_t len)70 cbo_zicbom_cpu_dcache_wb_range(vm_offset_t va, vm_size_t len)
71 {
72 	vm_offset_t addr;
73 
74 	/*
75 	 * A clean operation makes data from store operations performed by the
76 	 * set of coherent agents visible to a set of non-coherent agents at a
77 	 * point common to both sets by performing a write transfer of a copy of
78 	 * a cache block to that point provided a coherent agent performed a
79 	 * store operation that modified the data in the cache block since the
80 	 * previous invalidate, clean, or flush operation on the cache block.
81 	 */
82 
83 	va &= ~(dcache_line_size - 1);
84 	for (addr = va; addr < va + len; addr += dcache_line_size)
85 		__asm __volatile(".option push; .option arch, +zicbom\n"
86 				 "cbo.clean (%0); .option pop\n" :: "r"(addr));
87 }
88 
89 void
cbo_zicbom_setup_cache(int cbom_block_size)90 cbo_zicbom_setup_cache(int cbom_block_size)
91 {
92 	struct riscv_cache_ops zicbom_ops;
93 
94 	if (cbom_block_size <= 0 || !powerof2(cbom_block_size)) {
95 		printf("Zicbom: could not initialise (invalid cache line %d)\n",
96 		    cbom_block_size);
97 		return;
98 	}
99 
100 	zicbom_ops.dcache_wbinv_range = cbo_zicbom_cpu_dcache_wbinv_range;
101 	zicbom_ops.dcache_inv_range = cbo_zicbom_cpu_dcache_inv_range;
102 	zicbom_ops.dcache_wb_range = cbo_zicbom_cpu_dcache_wb_range;
103 	riscv_cache_install_hooks(&zicbom_ops, cbom_block_size);
104 }
105