1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/T2H SoC 4 * 5 * Copyright (C) 2025 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 compatible = "renesas,r9a09g077"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 interrupt-parent = <&gic>; 16 17 cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 21 cpu0: cpu@0 { 22 compatible = "arm,cortex-a55"; 23 reg = <0>; 24 device_type = "cpu"; 25 next-level-cache = <&L3_CA55>; 26 enable-method = "psci"; 27 }; 28 29 cpu1: cpu@100 { 30 compatible = "arm,cortex-a55"; 31 reg = <0x100>; 32 device_type = "cpu"; 33 next-level-cache = <&L3_CA55>; 34 enable-method = "psci"; 35 }; 36 37 cpu2: cpu@200 { 38 compatible = "arm,cortex-a55"; 39 reg = <0x200>; 40 device_type = "cpu"; 41 next-level-cache = <&L3_CA55>; 42 enable-method = "psci"; 43 }; 44 45 cpu3: cpu@300 { 46 compatible = "arm,cortex-a55"; 47 reg = <0x300>; 48 device_type = "cpu"; 49 next-level-cache = <&L3_CA55>; 50 enable-method = "psci"; 51 }; 52 53 L3_CA55: cache-controller-0 { 54 compatible = "cache"; 55 cache-unified; 56 cache-size = <0x100000>; 57 cache-level = <3>; 58 }; 59 }; 60 61 extal_clk: extal { 62 compatible = "fixed-clock"; 63 #clock-cells = <0>; 64 /* This value must be overridden by the board */ 65 clock-frequency = <0>; 66 }; 67 68 pmu { 69 compatible = "arm,cortex-a55-pmu"; 70 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 71 }; 72 73 psci { 74 compatible = "arm,psci-1.0", "arm,psci-0.2"; 75 method = "smc"; 76 }; 77 78 soc: soc { 79 compatible = "simple-bus"; 80 #address-cells = <2>; 81 #size-cells = <2>; 82 ranges; 83 84 sci0: serial@80005000 { 85 compatible = "renesas,r9a09g077-rsci"; 86 reg = <0 0x80005000 0 0x400>; 87 interrupts = <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 591 IRQ_TYPE_EDGE_RISING>, 89 <GIC_SPI 592 IRQ_TYPE_EDGE_RISING>, 90 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>; 91 interrupt-names = "eri", "rxi", "txi", "tei"; 92 clocks = <&cpg CPG_MOD 8>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; 93 clock-names = "operation", "bus"; 94 power-domains = <&cpg>; 95 status = "disabled"; 96 }; 97 98 sci1: serial@80005400 { 99 compatible = "renesas,r9a09g077-rsci"; 100 reg = <0 0x80005400 0 0x400>; 101 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 595 IRQ_TYPE_EDGE_RISING>, 103 <GIC_SPI 596 IRQ_TYPE_EDGE_RISING>, 104 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>; 105 interrupt-names = "eri", "rxi", "txi", "tei"; 106 clocks = <&cpg CPG_MOD 9>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; 107 clock-names = "operation", "bus"; 108 power-domains = <&cpg>; 109 status = "disabled"; 110 }; 111 112 sci2: serial@80005800 { 113 compatible = "renesas,r9a09g077-rsci"; 114 reg = <0 0x80005800 0 0x400>; 115 interrupts = <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 116 <GIC_SPI 599 IRQ_TYPE_EDGE_RISING>, 117 <GIC_SPI 600 IRQ_TYPE_EDGE_RISING>, 118 <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 119 interrupt-names = "eri", "rxi", "txi", "tei"; 120 clocks = <&cpg CPG_MOD 10>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; 121 clock-names = "operation", "bus"; 122 power-domains = <&cpg>; 123 status = "disabled"; 124 }; 125 126 sci3: serial@80005c00 { 127 compatible = "renesas,r9a09g077-rsci"; 128 reg = <0 0x80005c00 0 0x400>; 129 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, 130 <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>, 131 <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>, 132 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 133 interrupt-names = "eri", "rxi", "txi", "tei"; 134 clocks = <&cpg CPG_MOD 11>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; 135 clock-names = "operation", "bus"; 136 power-domains = <&cpg>; 137 status = "disabled"; 138 }; 139 140 sci4: serial@80006000 { 141 compatible = "renesas,r9a09g077-rsci"; 142 reg = <0 0x80006000 0 0x400>; 143 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 607 IRQ_TYPE_EDGE_RISING>, 145 <GIC_SPI 608 IRQ_TYPE_EDGE_RISING>, 146 <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>; 147 interrupt-names = "eri", "rxi", "txi", "tei"; 148 clocks = <&cpg CPG_MOD 12>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; 149 clock-names = "operation", "bus"; 150 power-domains = <&cpg>; 151 status = "disabled"; 152 }; 153 154 sci5: serial@81005000 { 155 compatible = "renesas,r9a09g077-rsci"; 156 reg = <0 0x81005000 0 0x400>; 157 interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 611 IRQ_TYPE_EDGE_RISING>, 159 <GIC_SPI 612 IRQ_TYPE_EDGE_RISING>, 160 <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>; 161 interrupt-names = "eri", "rxi", "txi", "tei"; 162 clocks = <&cpg CPG_MOD 600>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; 163 clock-names = "operation", "bus"; 164 power-domains = <&cpg>; 165 status = "disabled"; 166 }; 167 168 wdt0: watchdog@80082000 { 169 compatible = "renesas,r9a09g077-wdt"; 170 reg = <0 0x80082000 0 0x400>, 171 <0 0x81295100 0 0x04>; 172 clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>; 173 clock-names = "pclk"; 174 power-domains = <&cpg>; 175 status = "disabled"; 176 }; 177 178 wdt1: watchdog@80082400 { 179 compatible = "renesas,r9a09g077-wdt"; 180 reg = <0 0x80082400 0 0x400>, 181 <0 0x81295104 0 0x04>; 182 clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>; 183 clock-names = "pclk"; 184 power-domains = <&cpg>; 185 status = "disabled"; 186 }; 187 188 wdt2: watchdog@80082800 { 189 compatible = "renesas,r9a09g077-wdt"; 190 reg = <0 0x80082800 0 0x400>, 191 <0 0x81295108 0 0x04>; 192 clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>; 193 clock-names = "pclk"; 194 power-domains = <&cpg>; 195 status = "disabled"; 196 }; 197 198 wdt3: watchdog@80082c00 { 199 compatible = "renesas,r9a09g077-wdt"; 200 reg = <0 0x80082c00 0 0x400>, 201 <0 0x8129510c 0 0x04>; 202 clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>; 203 clock-names = "pclk"; 204 power-domains = <&cpg>; 205 status = "disabled"; 206 }; 207 208 wdt4: watchdog@80083000 { 209 compatible = "renesas,r9a09g077-wdt"; 210 reg = <0 0x80083000 0 0x400>, 211 <0 0x81295110 0 0x04>; 212 clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>; 213 clock-names = "pclk"; 214 power-domains = <&cpg>; 215 status = "disabled"; 216 }; 217 218 wdt5: watchdog@80083400 { 219 compatible = "renesas,r9a09g077-wdt"; 220 reg = <0 0x80083400 0 0x400>, 221 <0 0x81295114 0 0x04>; 222 clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>; 223 clock-names = "pclk"; 224 power-domains = <&cpg>; 225 status = "disabled"; 226 }; 227 228 i2c0: i2c@80088000 { 229 compatible = "renesas,riic-r9a09g077"; 230 reg = <0 0x80088000 0 0x400>; 231 interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 615 IRQ_TYPE_EDGE_RISING>, 233 <GIC_SPI 616 IRQ_TYPE_EDGE_RISING>, 234 <GIC_SPI 617 IRQ_TYPE_LEVEL_HIGH>; 235 interrupt-names = "eei", "rxi", "txi", "tei"; 236 clocks = <&cpg CPG_MOD 100>; 237 power-domains = <&cpg>; 238 #address-cells = <1>; 239 #size-cells = <0>; 240 status = "disabled"; 241 }; 242 243 i2c1: i2c@80088400 { 244 compatible = "renesas,riic-r9a09g077"; 245 reg = <0 0x80088400 0 0x400>; 246 interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH>, 247 <GIC_SPI 619 IRQ_TYPE_EDGE_RISING>, 248 <GIC_SPI 620 IRQ_TYPE_EDGE_RISING>, 249 <GIC_SPI 621 IRQ_TYPE_LEVEL_HIGH>; 250 interrupt-names = "eei", "rxi", "txi", "tei"; 251 clocks = <&cpg CPG_MOD 101>; 252 power-domains = <&cpg>; 253 #address-cells = <1>; 254 #size-cells = <0>; 255 status = "disabled"; 256 }; 257 258 i2c2: i2c@81008000 { 259 compatible = "renesas,riic-r9a09g077"; 260 reg = <0 0x81008000 0 0x400>; 261 interrupts = <GIC_SPI 622 IRQ_TYPE_LEVEL_HIGH>, 262 <GIC_SPI 623 IRQ_TYPE_EDGE_RISING>, 263 <GIC_SPI 624 IRQ_TYPE_EDGE_RISING>, 264 <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH>; 265 interrupt-names = "eei", "rxi", "txi", "tei"; 266 clocks = <&cpg CPG_MOD 601>; 267 power-domains = <&cpg>; 268 #address-cells = <1>; 269 #size-cells = <0>; 270 status = "disabled"; 271 }; 272 273 gmac0: ethernet@80100000 { 274 compatible = "renesas,r9a09g077-gbeth", "snps,dwmac-5.20"; 275 reg = <0 0x80100000 0 0x10000>; 276 interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>, 277 <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>, 278 <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>, 280 <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>, 286 <GIC_SPI 516 IRQ_TYPE_LEVEL_HIGH>, 287 <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>, 288 <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>, 289 <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH>, 290 <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 293 <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 294 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 295 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", 296 "rx-queue-0", "rx-queue-1", "rx-queue-2", 297 "rx-queue-3", "rx-queue-4", "rx-queue-5", 298 "rx-queue-6", "rx-queue-7", "tx-queue-0", 299 "tx-queue-1", "tx-queue-2", "tx-queue-3", 300 "tx-queue-4", "tx-queue-5", "tx-queue-6", 301 "tx-queue-7"; 302 clocks = <&cpg CPG_MOD 400>, 303 <&cpg CPG_CORE R9A09G077_CLK_PCLKH>, 304 <&cpg CPG_CORE R9A09G077_ETCLKB>; 305 clock-names = "stmmaceth", "pclk", "tx"; 306 resets = <&cpg 400>, <&cpg 401>; 307 reset-names = "stmmaceth", "ahb"; 308 power-domains = <&cpg>; 309 snps,multicast-filter-bins = <256>; 310 snps,perfect-filter-entries = <32>; 311 rx-fifo-depth = <8192>; 312 tx-fifo-depth = <8192>; 313 snps,fixed-burst; 314 snps,no-pbl-x8; 315 snps,force_thresh_dma_mode; 316 snps,axi-config = <&stmmac_axi_setup>; 317 snps,mtl-rx-config = <&mtl_rx_setup0>; 318 snps,mtl-tx-config = <&mtl_tx_setup0>; 319 snps,txpbl = <16>; 320 snps,rxpbl = <16>; 321 status = "disabled"; 322 323 mdio0: mdio { 324 compatible = "snps,dwmac-mdio"; 325 #address-cells = <1>; 326 #size-cells = <0>; 327 }; 328 329 mtl_rx_setup0: rx-queues-config { 330 snps,rx-queues-to-use = <8>; 331 snps,rx-sched-sp; 332 333 queue0 { 334 snps,dcb-algorithm; 335 snps,priority = <0x1>; 336 snps,map-to-dma-channel = <0>; 337 }; 338 339 queue1 { 340 snps,dcb-algorithm; 341 snps,priority = <0x2>; 342 snps,map-to-dma-channel = <1>; 343 }; 344 345 queue2 { 346 snps,dcb-algorithm; 347 snps,priority = <0x4>; 348 snps,map-to-dma-channel = <2>; 349 }; 350 351 queue3 { 352 snps,dcb-algorithm; 353 snps,priority = <0x8>; 354 snps,map-to-dma-channel = <3>; 355 }; 356 357 queue4 { 358 snps,dcb-algorithm; 359 snps,priority = <0x10>; 360 snps,map-to-dma-channel = <4>; 361 }; 362 363 queue5 { 364 snps,dcb-algorithm; 365 snps,priority = <0x20>; 366 snps,map-to-dma-channel = <5>; 367 }; 368 369 queue6 { 370 snps,dcb-algorithm; 371 snps,priority = <0x40>; 372 snps,map-to-dma-channel = <6>; 373 }; 374 375 queue7 { 376 snps,dcb-algorithm; 377 snps,priority = <0x80>; 378 snps,map-to-dma-channel = <7>; 379 }; 380 }; 381 382 mtl_tx_setup0: tx-queues-config { 383 snps,tx-queues-to-use = <8>; 384 385 queue0 { 386 snps,dcb-algorithm; 387 }; 388 389 queue1 { 390 snps,dcb-algorithm; 391 }; 392 393 queue2 { 394 snps,dcb-algorithm; 395 }; 396 397 queue3 { 398 snps,dcb-algorithm; 399 }; 400 401 queue4 { 402 snps,dcb-algorithm; 403 }; 404 405 queue5 { 406 snps,dcb-algorithm; 407 }; 408 409 queue6 { 410 snps,dcb-algorithm; 411 }; 412 413 queue7 { 414 snps,dcb-algorithm; 415 }; 416 }; 417 }; 418 419 gmac1: ethernet@92000000 { 420 compatible = "renesas,r9a09g077-gbeth", "snps,dwmac-5.20"; 421 reg = <0 0x92000000 0 0x10000>; 422 interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH>, 423 <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>, 424 <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>, 425 <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>, 426 <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>, 427 <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, 428 <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, 429 <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, 430 <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>, 431 <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>, 432 <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>, 433 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>, 434 <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>, 435 <GIC_SPI 522 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>; 441 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", 442 "rx-queue-0", "rx-queue-1", "rx-queue-2", 443 "rx-queue-3", "rx-queue-4", "rx-queue-5", 444 "rx-queue-6", "rx-queue-7", "tx-queue-0", 445 "tx-queue-1", "tx-queue-2", "tx-queue-3", 446 "tx-queue-4", "tx-queue-5", "tx-queue-6", 447 "tx-queue-7"; 448 clocks = <&cpg CPG_MOD 416>, 449 <&cpg CPG_CORE R9A09G077_CLK_PCLKAH>, 450 <&cpg CPG_CORE R9A09G077_ETCLKB>; 451 clock-names = "stmmaceth", "pclk", "tx"; 452 resets = <&cpg 416>, <&cpg 417>; 453 reset-names = "stmmaceth", "ahb"; 454 power-domains = <&cpg>; 455 snps,multicast-filter-bins = <256>; 456 snps,perfect-filter-entries = <32>; 457 rx-fifo-depth = <8192>; 458 tx-fifo-depth = <8192>; 459 snps,fixed-burst; 460 snps,no-pbl-x8; 461 snps,force_thresh_dma_mode; 462 snps,axi-config = <&stmmac_axi_setup>; 463 snps,mtl-rx-config = <&mtl_rx_setup1>; 464 snps,mtl-tx-config = <&mtl_tx_setup1>; 465 snps,txpbl = <16>; 466 snps,rxpbl = <16>; 467 status = "disabled"; 468 469 mdio1: mdio { 470 compatible = "snps,dwmac-mdio"; 471 #address-cells = <1>; 472 #size-cells = <0>; 473 }; 474 475 mtl_rx_setup1: rx-queues-config { 476 snps,rx-queues-to-use = <8>; 477 snps,rx-sched-sp; 478 479 queue0 { 480 snps,dcb-algorithm; 481 snps,priority = <0x1>; 482 snps,map-to-dma-channel = <0>; 483 }; 484 485 queue1 { 486 snps,dcb-algorithm; 487 snps,priority = <0x2>; 488 snps,map-to-dma-channel = <1>; 489 }; 490 491 queue2 { 492 snps,dcb-algorithm; 493 snps,priority = <0x4>; 494 snps,map-to-dma-channel = <2>; 495 }; 496 497 queue3 { 498 snps,dcb-algorithm; 499 snps,priority = <0x8>; 500 snps,map-to-dma-channel = <3>; 501 }; 502 503 queue4 { 504 snps,dcb-algorithm; 505 snps,priority = <0x10>; 506 snps,map-to-dma-channel = <4>; 507 }; 508 509 queue5 { 510 snps,dcb-algorithm; 511 snps,priority = <0x20>; 512 snps,map-to-dma-channel = <5>; 513 }; 514 515 queue6 { 516 snps,dcb-algorithm; 517 snps,priority = <0x40>; 518 snps,map-to-dma-channel = <6>; 519 }; 520 521 queue7 { 522 snps,dcb-algorithm; 523 snps,priority = <0x80>; 524 snps,map-to-dma-channel = <7>; 525 }; 526 }; 527 528 mtl_tx_setup1: tx-queues-config { 529 snps,tx-queues-to-use = <8>; 530 531 queue0 { 532 snps,dcb-algorithm; 533 }; 534 535 queue1 { 536 snps,dcb-algorithm; 537 }; 538 539 queue2 { 540 snps,dcb-algorithm; 541 }; 542 543 queue3 { 544 snps,dcb-algorithm; 545 }; 546 547 queue4 { 548 snps,dcb-algorithm; 549 }; 550 551 queue5 { 552 snps,dcb-algorithm; 553 }; 554 555 queue6 { 556 snps,dcb-algorithm; 557 }; 558 559 queue7 { 560 snps,dcb-algorithm; 561 }; 562 }; 563 }; 564 565 gmac2: ethernet@92010000 { 566 compatible = "renesas,r9a09g077-gbeth", "snps,dwmac-5.20"; 567 reg = <0 0x92010000 0 0x10000>; 568 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 538 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 537 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>, 574 <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>, 575 <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>, 576 <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>, 577 <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>, 579 <GIC_SPI 539 IRQ_TYPE_LEVEL_HIGH>, 580 <GIC_SPI 540 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>, 583 <GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>; 587 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", 588 "rx-queue-0", "rx-queue-1", "rx-queue-2", 589 "rx-queue-3", "rx-queue-4", "rx-queue-5", 590 "rx-queue-6", "rx-queue-7", "tx-queue-0", 591 "tx-queue-1", "tx-queue-2", "tx-queue-3", 592 "tx-queue-4", "tx-queue-5", "tx-queue-6", 593 "tx-queue-7"; 594 clocks = <&cpg CPG_MOD 417>, 595 <&cpg CPG_CORE R9A09G077_CLK_PCLKAH>, 596 <&cpg CPG_CORE R9A09G077_ETCLKB>; 597 clock-names = "stmmaceth", "pclk", "tx"; 598 resets = <&cpg 418>, <&cpg 419>; 599 reset-names = "stmmaceth", "ahb"; 600 power-domains = <&cpg>; 601 snps,multicast-filter-bins = <256>; 602 snps,perfect-filter-entries = <32>; 603 rx-fifo-depth = <8192>; 604 tx-fifo-depth = <8192>; 605 snps,fixed-burst; 606 snps,no-pbl-x8; 607 snps,force_thresh_dma_mode; 608 snps,axi-config = <&stmmac_axi_setup>; 609 snps,mtl-rx-config = <&mtl_rx_setup2>; 610 snps,mtl-tx-config = <&mtl_tx_setup2>; 611 snps,txpbl = <16>; 612 snps,rxpbl = <16>; 613 status = "disabled"; 614 615 mdio2: mdio { 616 compatible = "snps,dwmac-mdio"; 617 #address-cells = <1>; 618 #size-cells = <0>; 619 }; 620 621 mtl_rx_setup2: rx-queues-config { 622 snps,rx-queues-to-use = <8>; 623 snps,rx-sched-sp; 624 625 queue0 { 626 snps,dcb-algorithm; 627 snps,priority = <0x1>; 628 snps,map-to-dma-channel = <0>; 629 }; 630 631 queue1 { 632 snps,dcb-algorithm; 633 snps,priority = <0x2>; 634 snps,map-to-dma-channel = <1>; 635 }; 636 637 queue2 { 638 snps,dcb-algorithm; 639 snps,priority = <0x4>; 640 snps,map-to-dma-channel = <2>; 641 }; 642 643 queue3 { 644 snps,dcb-algorithm; 645 snps,priority = <0x8>; 646 snps,map-to-dma-channel = <3>; 647 }; 648 649 queue4 { 650 snps,dcb-algorithm; 651 snps,priority = <0x10>; 652 snps,map-to-dma-channel = <4>; 653 }; 654 655 queue5 { 656 snps,dcb-algorithm; 657 snps,priority = <0x20>; 658 snps,map-to-dma-channel = <5>; 659 }; 660 661 queue6 { 662 snps,dcb-algorithm; 663 snps,priority = <0x40>; 664 snps,map-to-dma-channel = <6>; 665 }; 666 667 queue7 { 668 snps,dcb-algorithm; 669 snps,priority = <0x80>; 670 snps,map-to-dma-channel = <7>; 671 }; 672 }; 673 674 mtl_tx_setup2: tx-queues-config { 675 snps,tx-queues-to-use = <8>; 676 677 queue0 { 678 snps,dcb-algorithm; 679 }; 680 681 queue1 { 682 snps,dcb-algorithm; 683 }; 684 685 queue2 { 686 snps,dcb-algorithm; 687 }; 688 689 queue3 { 690 snps,dcb-algorithm; 691 }; 692 693 queue4 { 694 snps,dcb-algorithm; 695 }; 696 697 queue5 { 698 snps,dcb-algorithm; 699 }; 700 701 queue6 { 702 snps,dcb-algorithm; 703 }; 704 705 queue7 { 706 snps,dcb-algorithm; 707 }; 708 }; 709 }; 710 711 ethss: ethss@80110000 { 712 compatible = "renesas,r9a09g077-miic"; 713 reg = <0 0x80110000 0 0x10000>; 714 clocks = <&cpg CPG_CORE R9A09G077_ETCLKE>, 715 <&cpg CPG_CORE R9A09G077_ETCLKB>, 716 <&cpg CPG_CORE R9A09G077_ETCLKD>, 717 <&cpg CPG_MOD 403>; 718 clock-names = "mii_ref", "rgmii_ref", "rmii_ref", "hclk"; 719 resets = <&cpg 405>, <&cpg 406>; 720 reset-names = "rst", "crst"; 721 power-domains = <&cpg>; 722 status = "disabled"; 723 724 #address-cells = <1>; 725 #size-cells = <0>; 726 727 mii_conv0: mii-conv@0 { 728 reg = <0>; 729 status = "disabled"; 730 }; 731 732 mii_conv1: mii-conv@1 { 733 reg = <1>; 734 status = "disabled"; 735 }; 736 737 mii_conv2: mii-conv@2 { 738 reg = <2>; 739 status = "disabled"; 740 }; 741 742 mii_conv3: mii-conv@3 { 743 reg = <3>; 744 status = "disabled"; 745 }; 746 }; 747 748 cpg: clock-controller@80280000 { 749 compatible = "renesas,r9a09g077-cpg-mssr"; 750 reg = <0 0x80280000 0 0x1000>, 751 <0 0x81280000 0 0x9000>; 752 clocks = <&extal_clk>; 753 clock-names = "extal"; 754 #clock-cells = <2>; 755 #reset-cells = <1>; 756 #power-domain-cells = <0>; 757 }; 758 759 pinctrl: pinctrl@802c0000 { 760 compatible = "renesas,r9a09g077-pinctrl"; 761 reg = <0 0x802c0000 0 0x10000>, 762 <0 0x812c0000 0 0x10000>, 763 <0 0x802b0000 0 0x10000>; 764 reg-names = "nsr", "srs", "srn"; 765 clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; 766 gpio-controller; 767 #gpio-cells = <2>; 768 gpio-ranges = <&pinctrl 0 0 288>; 769 power-domains = <&cpg>; 770 }; 771 772 gic: interrupt-controller@83000000 { 773 compatible = "arm,gic-v3"; 774 reg = <0x0 0x83000000 0 0x40000>, 775 <0x0 0x83040000 0 0x160000>; 776 #interrupt-cells = <3>; 777 #address-cells = <0>; 778 interrupt-controller; 779 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 780 }; 781 782 adc0: adc@90014000 { 783 compatible = "renesas,r9a09g077-adc"; 784 reg = <0 0x90014000 0 0x400>; 785 interrupts = <GIC_SPI 698 IRQ_TYPE_EDGE_RISING>, 786 <GIC_SPI 699 IRQ_TYPE_EDGE_RISING>, 787 <GIC_SPI 700 IRQ_TYPE_EDGE_RISING>, 788 <GIC_SPI 701 IRQ_TYPE_LEVEL_HIGH>, 789 <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH>, 790 <GIC_SPI 851 IRQ_TYPE_EDGE_RISING>, 791 <GIC_SPI 852 IRQ_TYPE_EDGE_RISING>; 792 interrupt-names = "adi", "gbadi", "gcadi", 793 "cmpai", "cmpbi", "wcmpm", "wcmpum"; 794 clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>, 795 <&cpg CPG_MOD 206>; 796 clock-names = "adclk", "pclk"; 797 power-domains = <&cpg>; 798 #address-cells = <1>; 799 #size-cells = <0>; 800 #io-channel-cells = <1>; 801 status = "disabled"; 802 }; 803 804 adc1: adc@90014400 { 805 compatible = "renesas,r9a09g077-adc"; 806 reg = <0 0x90014400 0 0x400>; 807 interrupts = <GIC_SPI 703 IRQ_TYPE_EDGE_RISING>, 808 <GIC_SPI 704 IRQ_TYPE_EDGE_RISING>, 809 <GIC_SPI 705 IRQ_TYPE_EDGE_RISING>, 810 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 811 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 812 <GIC_SPI 853 IRQ_TYPE_EDGE_RISING>, 813 <GIC_SPI 854 IRQ_TYPE_EDGE_RISING>; 814 interrupt-names = "adi", "gbadi", "gcadi", 815 "cmpai", "cmpbi", "wcmpm", "wcmpum"; 816 clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>, 817 <&cpg CPG_MOD 207>; 818 clock-names = "adclk", "pclk"; 819 power-domains = <&cpg>; 820 #address-cells = <1>; 821 #size-cells = <0>; 822 #io-channel-cells = <1>; 823 status = "disabled"; 824 }; 825 826 adc2: adc@80008000 { 827 compatible = "renesas,r9a09g077-adc"; 828 reg = <0 0x80008000 0 0x400>; 829 interrupts = <GIC_SPI 708 IRQ_TYPE_EDGE_RISING>, 830 <GIC_SPI 709 IRQ_TYPE_EDGE_RISING>, 831 <GIC_SPI 710 IRQ_TYPE_EDGE_RISING>, 832 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 833 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 834 <GIC_SPI 855 IRQ_TYPE_EDGE_RISING>, 835 <GIC_SPI 856 IRQ_TYPE_EDGE_RISING>; 836 interrupt-names = "adi", "gbadi", "gcadi", 837 "cmpai", "cmpbi", "wcmpm", "wcmpum"; 838 clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>, 839 <&cpg CPG_MOD 225>; 840 clock-names = "adclk", "pclk"; 841 power-domains = <&cpg>; 842 #address-cells = <1>; 843 #size-cells = <0>; 844 #io-channel-cells = <1>; 845 status = "disabled"; 846 }; 847 848 ohci: usb@92040000 { 849 compatible = "generic-ohci"; 850 reg = <0 0x92040000 0 0x100>; 851 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 852 clocks = <&cpg CPG_MOD 408>; 853 phys = <&usb2_phy 1>; 854 phy-names = "usb"; 855 power-domains = <&cpg>; 856 status = "disabled"; 857 }; 858 859 ehci: usb@92040100 { 860 compatible = "generic-ehci"; 861 reg = <0 0x92040100 0 0x100>; 862 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 863 clocks = <&cpg CPG_MOD 408>; 864 phys = <&usb2_phy 2>; 865 phy-names = "usb"; 866 companion = <&ohci>; 867 power-domains = <&cpg>; 868 status = "disabled"; 869 }; 870 871 usb2_phy: usb-phy@92040200 { 872 compatible = "renesas,usb2-phy-r9a09g077"; 873 reg = <0 0x92040200 0 0x700>; 874 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 875 clocks = <&cpg CPG_MOD 408>, 876 <&cpg CPG_CORE R9A09G077_USB_CLK>; 877 #phy-cells = <1>; 878 power-domains = <&cpg>; 879 status = "disabled"; 880 }; 881 882 hsusb: usb@92041000 { 883 compatible = "renesas,usbhs-r9a09g077"; 884 reg = <0 0x92041000 0 0x1000>; 885 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>, 886 <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 887 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>; 888 clocks = <&cpg CPG_MOD 408>; 889 phys = <&usb2_phy 3>; 890 phy-names = "usb"; 891 power-domains = <&cpg>; 892 status = "disabled"; 893 }; 894 895 sdhi0: mmc@92080000 { 896 compatible = "renesas,sdhi-r9a09g077", 897 "renesas,sdhi-r9a09g057"; 898 reg = <0x0 0x92080000 0 0x10000>; 899 interrupts = <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>, 900 <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>; 901 clocks = <&cpg CPG_MOD 1212>, 902 <&cpg CPG_CORE R9A09G077_SDHI_CLKHS>; 903 clock-names = "aclk", "clkh"; 904 power-domains = <&cpg>; 905 status = "disabled"; 906 907 sdhi0_vqmmc: vqmmc-regulator { 908 regulator-name = "SDHI0-VQMMC"; 909 regulator-min-microvolt = <1800000>; 910 regulator-max-microvolt = <3300000>; 911 status = "disabled"; 912 }; 913 }; 914 915 sdhi1: mmc@92090000 { 916 compatible = "renesas,sdhi-r9a09g077", 917 "renesas,sdhi-r9a09g057"; 918 reg = <0x0 0x92090000 0 0x10000>; 919 interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 920 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>; 921 clocks = <&cpg CPG_MOD 1213>, 922 <&cpg CPG_CORE R9A09G077_SDHI_CLKHS>; 923 clock-names = "aclk", "clkh"; 924 power-domains = <&cpg>; 925 status = "disabled"; 926 927 sdhi1_vqmmc: vqmmc-regulator { 928 regulator-name = "SDHI1-VQMMC"; 929 regulator-min-microvolt = <1800000>; 930 regulator-max-microvolt = <3300000>; 931 status = "disabled"; 932 }; 933 }; 934 }; 935 936 stmmac_axi_setup: stmmac-axi-config { 937 snps,lpi_en; 938 snps,wr_osr_lmt = <0xf>; 939 snps,rd_osr_lmt = <0xf>; 940 snps,blen = <16 8 4 0 0 0 0>; 941 }; 942 943 timer { 944 compatible = "arm,armv8-timer"; 945 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 946 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 947 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 948 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 949 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 950 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 951 }; 952}; 953