1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/G3S SoC 4 * 5 * Copyright (C) 2023 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/r9a08g045-cpg.h> 10#include <dt-bindings/clock/renesas,r9a08g045-vbattb.h> 11 12/ { 13 compatible = "renesas,r9a08g045"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 audio_clk1: audio1-clk { 18 compatible = "fixed-clock"; 19 #clock-cells = <0>; 20 /* This value must be overridden by boards that provide it. */ 21 clock-frequency = <0>; 22 }; 23 24 audio_clk2: audio2-clk { 25 compatible = "fixed-clock"; 26 #clock-cells = <0>; 27 /* This value must be overridden by boards that provide it. */ 28 clock-frequency = <0>; 29 }; 30 31 cluster0_opp: opp-table-0 { 32 compatible = "operating-points-v2"; 33 opp-shared; 34 35 opp-137500000 { 36 opp-hz = /bits/ 64 <137500000>; 37 opp-microvolt = <940000>; 38 clock-latency-ns = <300000>; 39 }; 40 opp-275000000 { 41 opp-hz = /bits/ 64 <275000000>; 42 opp-microvolt = <940000>; 43 clock-latency-ns = <300000>; 44 }; 45 opp-550000000 { 46 opp-hz = /bits/ 64 <550000000>; 47 opp-microvolt = <940000>; 48 clock-latency-ns = <300000>; 49 }; 50 opp-1100000000 { 51 opp-hz = /bits/ 64 <1100000000>; 52 opp-microvolt = <940000>; 53 clock-latency-ns = <300000>; 54 opp-suspend; 55 }; 56 }; 57 58 cpus { 59 #address-cells = <1>; 60 #size-cells = <0>; 61 62 cpu0: cpu@0 { 63 compatible = "arm,cortex-a55"; 64 reg = <0>; 65 device_type = "cpu"; 66 #cooling-cells = <2>; 67 next-level-cache = <&L3_CA55>; 68 enable-method = "psci"; 69 clocks = <&cpg CPG_CORE R9A08G045_CLK_I>; 70 operating-points-v2 = <&cluster0_opp>; 71 }; 72 73 L3_CA55: cache-controller-0 { 74 compatible = "cache"; 75 cache-level = <3>; 76 cache-unified; 77 cache-size = <0x40000>; 78 }; 79 }; 80 81 extal_clk: extal-clk { 82 compatible = "fixed-clock"; 83 #clock-cells = <0>; 84 /* This value must be overridden by the board. */ 85 clock-frequency = <0>; 86 }; 87 88 psci { 89 compatible = "arm,psci-1.0", "arm,psci-0.2"; 90 method = "smc"; 91 }; 92 93 soc: soc { 94 compatible = "simple-bus"; 95 interrupt-parent = <&gic>; 96 #address-cells = <2>; 97 #size-cells = <2>; 98 ranges; 99 100 scif0: serial@1004b800 { 101 compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044"; 102 reg = <0 0x1004b800 0 0x400>; 103 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>; 109 interrupt-names = "eri", "rxi", "txi", 110 "bri", "dri", "tei"; 111 clocks = <&cpg CPG_MOD R9A08G045_SCIF0_CLK_PCK>; 112 clock-names = "fck"; 113 power-domains = <&cpg>; 114 resets = <&cpg R9A08G045_SCIF0_RST_SYSTEM_N>; 115 status = "disabled"; 116 }; 117 118 scif1: serial@1004bc00 { 119 compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044"; 120 reg = <0 0x1004bc00 0 0x400>; 121 interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 122 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 123 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 124 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 125 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 126 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 127 interrupt-names = "eri", "rxi", "txi", 128 "bri", "dri", "tei"; 129 clocks = <&cpg CPG_MOD R9A08G045_SCIF1_CLK_PCK>; 130 clock-names = "fck"; 131 power-domains = <&cpg>; 132 resets = <&cpg R9A08G045_SCIF1_RST_SYSTEM_N>; 133 status = "disabled"; 134 }; 135 136 scif2: serial@1004c000 { 137 compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044"; 138 reg = <0 0x1004c000 0 0x400>; 139 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>; 145 interrupt-names = "eri", "rxi", "txi", 146 "bri", "dri", "tei"; 147 clocks = <&cpg CPG_MOD R9A08G045_SCIF2_CLK_PCK>; 148 clock-names = "fck"; 149 power-domains = <&cpg>; 150 resets = <&cpg R9A08G045_SCIF2_RST_SYSTEM_N>; 151 status = "disabled"; 152 }; 153 154 scif3: serial@1004c400 { 155 compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044"; 156 reg = <0 0x1004c400 0 0x400>; 157 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 160 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 162 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; 163 interrupt-names = "eri", "rxi", "txi", 164 "bri", "dri", "tei"; 165 clocks = <&cpg CPG_MOD R9A08G045_SCIF3_CLK_PCK>; 166 clock-names = "fck"; 167 power-domains = <&cpg>; 168 resets = <&cpg R9A08G045_SCIF3_RST_SYSTEM_N>; 169 status = "disabled"; 170 }; 171 172 scif4: serial@1004c800 { 173 compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044"; 174 reg = <0 0x1004c800 0 0x400>; 175 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 181 interrupt-names = "eri", "rxi", "txi", 182 "bri", "dri", "tei"; 183 clocks = <&cpg CPG_MOD R9A08G045_SCIF4_CLK_PCK>; 184 clock-names = "fck"; 185 power-domains = <&cpg>; 186 resets = <&cpg R9A08G045_SCIF4_RST_SYSTEM_N>; 187 status = "disabled"; 188 }; 189 190 scif5: serial@1004e000 { 191 compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044"; 192 reg = <0 0x1004e000 0 0x400>; 193 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; 199 interrupt-names = "eri", "rxi", "txi", 200 "bri", "dri", "tei"; 201 clocks = <&cpg CPG_MOD R9A08G045_SCIF5_CLK_PCK>; 202 clock-names = "fck"; 203 power-domains = <&cpg>; 204 resets = <&cpg R9A08G045_SCIF5_RST_SYSTEM_N>; 205 status = "disabled"; 206 }; 207 208 rtc: rtc@1004ec00 { 209 compatible = "renesas,r9a08g045-rtca3", "renesas,rz-rtca3"; 210 reg = <0 0x1004ec00 0 0x400>; 211 interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; 214 interrupt-names = "alarm", "period", "carry"; 215 clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb VBATTB_VBATTCLK>; 216 clock-names = "bus", "counter"; 217 power-domains = <&cpg>; 218 resets = <&cpg R9A08G045_VBAT_BRESETN>; 219 status = "disabled"; 220 }; 221 222 adc: adc@10058000 { 223 compatible = "renesas,r9a08g045-adc"; 224 reg = <0 0x10058000 0 0x1000>; 225 interrupts = <GIC_SPI 312 IRQ_TYPE_EDGE_RISING>; 226 clocks = <&cpg CPG_MOD R9A08G045_ADC_ADCLK>, 227 <&cpg CPG_MOD R9A08G045_ADC_PCLK>; 228 clock-names = "adclk", "pclk"; 229 resets = <&cpg R9A08G045_ADC_PRESETN>, 230 <&cpg R9A08G045_ADC_ADRST_N>; 231 reset-names = "presetn", "adrst-n"; 232 power-domains = <&cpg>; 233 #address-cells = <1>; 234 #size-cells = <0>; 235 #io-channel-cells = <1>; 236 status = "disabled"; 237 238 channel@0 { 239 reg = <0>; 240 }; 241 242 channel@1 { 243 reg = <1>; 244 }; 245 246 channel@2 { 247 reg = <2>; 248 }; 249 250 channel@3 { 251 reg = <3>; 252 }; 253 254 channel@4 { 255 reg = <4>; 256 }; 257 258 channel@5 { 259 reg = <5>; 260 }; 261 262 channel@6 { 263 reg = <6>; 264 }; 265 266 channel@7 { 267 reg = <7>; 268 }; 269 270 channel@8 { 271 reg = <8>; 272 }; 273 }; 274 275 vbattb: clock-controller@1005c000 { 276 compatible = "renesas,r9a08g045-vbattb"; 277 reg = <0 0x1005c000 0 0x1000>; 278 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 279 clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>; 280 clock-names = "bclk", "rtx"; 281 #clock-cells = <1>; 282 power-domains = <&cpg>; 283 resets = <&cpg R9A08G045_VBAT_BRESETN>; 284 status = "disabled"; 285 }; 286 287 i2c0: i2c@10090000 { 288 compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057"; 289 reg = <0 0x10090000 0 0x400>; 290 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>, 292 <GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 293 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 294 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 295 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 296 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 297 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; 298 interrupt-names = "tei", "ri", "ti", "spi", "sti", 299 "naki", "ali", "tmoi"; 300 clocks = <&cpg CPG_MOD R9A08G045_I2C0_PCLK>; 301 clock-frequency = <100000>; 302 resets = <&cpg R9A08G045_I2C0_MRST>; 303 power-domains = <&cpg>; 304 #address-cells = <1>; 305 #size-cells = <0>; 306 status = "disabled"; 307 }; 308 309 i2c1: i2c@10090400 { 310 compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057"; 311 reg = <0 0x10090400 0 0x400>; 312 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 313 <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>, 314 <GIC_SPI 272 IRQ_TYPE_EDGE_RISING>, 315 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 316 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 317 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 318 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 319 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>; 320 interrupt-names = "tei", "ri", "ti", "spi", "sti", 321 "naki", "ali", "tmoi"; 322 clocks = <&cpg CPG_MOD R9A08G045_I2C1_PCLK>; 323 clock-frequency = <100000>; 324 resets = <&cpg R9A08G045_I2C1_MRST>; 325 power-domains = <&cpg>; 326 #address-cells = <1>; 327 #size-cells = <0>; 328 status = "disabled"; 329 }; 330 331 i2c2: i2c@10090800 { 332 compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057"; 333 reg = <0 0x10090800 0 0x400>; 334 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 335 <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>, 336 <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>, 337 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 338 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 339 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 340 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 341 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>; 342 interrupt-names = "tei", "ri", "ti", "spi", "sti", 343 "naki", "ali", "tmoi"; 344 clocks = <&cpg CPG_MOD R9A08G045_I2C2_PCLK>; 345 clock-frequency = <100000>; 346 resets = <&cpg R9A08G045_I2C2_MRST>; 347 power-domains = <&cpg>; 348 #address-cells = <1>; 349 #size-cells = <0>; 350 status = "disabled"; 351 }; 352 353 i2c3: i2c@10090c00 { 354 compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057"; 355 reg = <0 0x10090c00 0 0x400>; 356 interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 357 <GIC_SPI 287 IRQ_TYPE_EDGE_RISING>, 358 <GIC_SPI 288 IRQ_TYPE_EDGE_RISING>, 359 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 360 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 361 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 362 <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>, 363 <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 364 interrupt-names = "tei", "ri", "ti", "spi", "sti", 365 "naki", "ali", "tmoi"; 366 clocks = <&cpg CPG_MOD R9A08G045_I2C3_PCLK>; 367 clock-frequency = <100000>; 368 resets = <&cpg R9A08G045_I2C3_MRST>; 369 power-domains = <&cpg>; 370 #address-cells = <1>; 371 #size-cells = <0>; 372 status = "disabled"; 373 }; 374 375 ssi0: ssi@100a8000 { 376 compatible = "renesas,r9a08g045-ssi", 377 "renesas,rz-ssi"; 378 reg = <0 0x100a8000 0 0x400>; 379 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 380 <GIC_SPI 241 IRQ_TYPE_EDGE_RISING>, 381 <GIC_SPI 242 IRQ_TYPE_EDGE_RISING>; 382 interrupt-names = "int_req", "dma_rx", "dma_tx"; 383 clocks = <&cpg CPG_MOD R9A08G045_SSI0_PCLK2>, 384 <&cpg CPG_MOD R9A08G045_SSI0_PCLK_SFR>, 385 <&audio_clk1>, <&audio_clk2>; 386 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 387 resets = <&cpg R9A08G045_SSI0_RST_M2_REG>; 388 dmas = <&dmac 0x2665>, <&dmac 0x2666>; 389 dma-names = "tx", "rx"; 390 power-domains = <&cpg>; 391 #sound-dai-cells = <0>; 392 status = "disabled"; 393 }; 394 395 ssi1: ssi@100a8400 { 396 compatible = "renesas,r9a08g045-ssi", 397 "renesas,rz-ssi"; 398 reg = <0 0x100a8400 0 0x400>; 399 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, 400 <GIC_SPI 244 IRQ_TYPE_EDGE_RISING>, 401 <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>; 402 interrupt-names = "int_req", "dma_rx", "dma_tx"; 403 clocks = <&cpg CPG_MOD R9A08G045_SSI1_PCLK2>, 404 <&cpg CPG_MOD R9A08G045_SSI1_PCLK_SFR>, 405 <&audio_clk1>, <&audio_clk2>; 406 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 407 resets = <&cpg R9A08G045_SSI1_RST_M2_REG>; 408 dmas = <&dmac 0x2669>, <&dmac 0x266a>; 409 dma-names = "tx", "rx"; 410 power-domains = <&cpg>; 411 #sound-dai-cells = <0>; 412 status = "disabled"; 413 }; 414 415 ssi2: ssi@100a8800 { 416 compatible = "renesas,r9a08g045-ssi", 417 "renesas,rz-ssi"; 418 reg = <0 0x100a8800 0 0x400>; 419 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 420 <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>, 421 <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>; 422 interrupt-names = "int_req", "dma_rx", "dma_tx"; 423 clocks = <&cpg CPG_MOD R9A08G045_SSI2_PCLK2>, 424 <&cpg CPG_MOD R9A08G045_SSI2_PCLK_SFR>, 425 <&audio_clk1>, <&audio_clk2>; 426 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 427 resets = <&cpg R9A08G045_SSI2_RST_M2_REG>; 428 dmas = <&dmac 0x266d>, <&dmac 0x266e>; 429 dma-names = "tx", "rx"; 430 power-domains = <&cpg>; 431 #sound-dai-cells = <0>; 432 status = "disabled"; 433 }; 434 435 ssi3: ssi@100a8c00 { 436 compatible = "renesas,r9a08g045-ssi", 437 "renesas,rz-ssi"; 438 reg = <0 0x100a8c00 0 0x400>; 439 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>, 441 <GIC_SPI 251 IRQ_TYPE_EDGE_RISING>; 442 interrupt-names = "int_req", "dma_rx", "dma_tx"; 443 clocks = <&cpg CPG_MOD R9A08G045_SSI3_PCLK2>, 444 <&cpg CPG_MOD R9A08G045_SSI3_PCLK_SFR>, 445 <&audio_clk1>, <&audio_clk2>; 446 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 447 resets = <&cpg R9A08G045_SSI3_RST_M2_REG>; 448 dmas = <&dmac 0x2671>, <&dmac 0x2672>; 449 dma-names = "tx", "rx"; 450 power-domains = <&cpg>; 451 #sound-dai-cells = <0>; 452 status = "disabled"; 453 }; 454 455 cpg: clock-controller@11010000 { 456 compatible = "renesas,r9a08g045-cpg"; 457 reg = <0 0x11010000 0 0x10000>; 458 clocks = <&extal_clk>; 459 clock-names = "extal"; 460 #clock-cells = <2>; 461 #reset-cells = <1>; 462 #power-domain-cells = <0>; 463 }; 464 465 sysc: system-controller@11020000 { 466 compatible = "renesas,r9a08g045-sysc"; 467 reg = <0 0x11020000 0 0x10000>; 468 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 469 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 470 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 471 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 472 interrupt-names = "lpm_int", "ca55stbydone_int", 473 "cm33stbyr_int", "ca55_deny"; 474 }; 475 476 pinctrl: pinctrl@11030000 { 477 compatible = "renesas,r9a08g045-pinctrl"; 478 reg = <0 0x11030000 0 0x10000>; 479 gpio-controller; 480 #gpio-cells = <2>; 481 interrupt-controller; 482 #interrupt-cells = <2>; 483 interrupt-parent = <&irqc>; 484 gpio-ranges = <&pinctrl 0 0 152>; 485 clocks = <&cpg CPG_MOD R9A08G045_GPIO_HCLK>; 486 power-domains = <&cpg>; 487 resets = <&cpg R9A08G045_GPIO_RSTN>, 488 <&cpg R9A08G045_GPIO_PORT_RESETN>, 489 <&cpg R9A08G045_GPIO_SPARE_RESETN>; 490 }; 491 492 irqc: interrupt-controller@11050000 { 493 compatible = "renesas,r9a08g045-irqc", "renesas,rzg2l-irqc"; 494 #interrupt-cells = <2>; 495 #address-cells = <0>; 496 interrupt-controller; 497 reg = <0 0x11050000 0 0x10000>; 498 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 499 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 500 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 501 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 502 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 506 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 507 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 526 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 534 <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, 536 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 537 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, 539 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 540 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 541 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 542 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 543 interrupt-names = "nmi", 544 "irq0", "irq1", "irq2", "irq3", 545 "irq4", "irq5", "irq6", "irq7", 546 "tint0", "tint1", "tint2", "tint3", 547 "tint4", "tint5", "tint6", "tint7", 548 "tint8", "tint9", "tint10", "tint11", 549 "tint12", "tint13", "tint14", "tint15", 550 "tint16", "tint17", "tint18", "tint19", 551 "tint20", "tint21", "tint22", "tint23", 552 "tint24", "tint25", "tint26", "tint27", 553 "tint28", "tint29", "tint30", "tint31", 554 "bus-err", "ec7tie1-0", "ec7tie2-0", 555 "ec7tiovf-0"; 556 clocks = <&cpg CPG_MOD R9A08G045_IA55_CLK>, 557 <&cpg CPG_MOD R9A08G045_IA55_PCLK>; 558 clock-names = "clk", "pclk"; 559 power-domains = <&cpg>; 560 resets = <&cpg R9A08G045_IA55_RESETN>; 561 }; 562 563 dmac: dma-controller@11820000 { 564 compatible = "renesas,r9a08g045-dmac", 565 "renesas,rz-dmac"; 566 reg = <0 0x11820000 0 0x10000>, 567 <0 0x11830000 0 0x10000>; 568 interrupts = <GIC_SPI 111 IRQ_TYPE_EDGE_RISING>, 569 <GIC_SPI 112 IRQ_TYPE_EDGE_RISING>, 570 <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>, 571 <GIC_SPI 114 IRQ_TYPE_EDGE_RISING>, 572 <GIC_SPI 115 IRQ_TYPE_EDGE_RISING>, 573 <GIC_SPI 116 IRQ_TYPE_EDGE_RISING>, 574 <GIC_SPI 117 IRQ_TYPE_EDGE_RISING>, 575 <GIC_SPI 118 IRQ_TYPE_EDGE_RISING>, 576 <GIC_SPI 119 IRQ_TYPE_EDGE_RISING>, 577 <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>, 578 <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>, 579 <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>, 580 <GIC_SPI 123 IRQ_TYPE_EDGE_RISING>, 581 <GIC_SPI 124 IRQ_TYPE_EDGE_RISING>, 582 <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>, 583 <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>, 584 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>; 585 interrupt-names = "error", 586 "ch0", "ch1", "ch2", "ch3", 587 "ch4", "ch5", "ch6", "ch7", 588 "ch8", "ch9", "ch10", "ch11", 589 "ch12", "ch13", "ch14", "ch15"; 590 clocks = <&cpg CPG_MOD R9A08G045_DMAC_ACLK>, 591 <&cpg CPG_MOD R9A08G045_DMAC_PCLK>; 592 clock-names = "main", "register"; 593 power-domains = <&cpg>; 594 resets = <&cpg R9A08G045_DMAC_ARESETN>, 595 <&cpg R9A08G045_DMAC_RST_ASYNC>; 596 reset-names = "arst", "rst_async"; 597 #dma-cells = <1>; 598 dma-channels = <16>; 599 }; 600 601 sdhi0: mmc@11c00000 { 602 compatible = "renesas,sdhi-r9a08g045", "renesas,rzg2l-sdhi"; 603 reg = <0x0 0x11c00000 0 0x10000>; 604 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 605 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 606 clocks = <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK>, 607 <&cpg CPG_MOD R9A08G045_SDHI0_CLK_HS>, 608 <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK2>, 609 <&cpg CPG_MOD R9A08G045_SDHI0_ACLK>; 610 clock-names = "core", "clkh", "cd", "aclk"; 611 resets = <&cpg R9A08G045_SDHI0_IXRST>; 612 power-domains = <&cpg>; 613 status = "disabled"; 614 }; 615 616 sdhi1: mmc@11c10000 { 617 compatible = "renesas,sdhi-r9a08g045", "renesas,rzg2l-sdhi"; 618 reg = <0x0 0x11c10000 0 0x10000>; 619 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 620 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 621 clocks = <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK>, 622 <&cpg CPG_MOD R9A08G045_SDHI1_CLK_HS>, 623 <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK2>, 624 <&cpg CPG_MOD R9A08G045_SDHI1_ACLK>; 625 clock-names = "core", "clkh", "cd", "aclk"; 626 resets = <&cpg R9A08G045_SDHI1_IXRST>; 627 power-domains = <&cpg>; 628 status = "disabled"; 629 }; 630 631 sdhi2: mmc@11c20000 { 632 compatible = "renesas,sdhi-r9a08g045", "renesas,rzg2l-sdhi"; 633 reg = <0x0 0x11c20000 0 0x10000>; 634 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 635 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 636 clocks = <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK>, 637 <&cpg CPG_MOD R9A08G045_SDHI2_CLK_HS>, 638 <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK2>, 639 <&cpg CPG_MOD R9A08G045_SDHI2_ACLK>; 640 clock-names = "core", "clkh", "cd", "aclk"; 641 resets = <&cpg R9A08G045_SDHI2_IXRST>; 642 power-domains = <&cpg>; 643 status = "disabled"; 644 }; 645 646 eth0: ethernet@11c30000 { 647 compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth"; 648 reg = <0 0x11c30000 0 0x10000>; 649 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 650 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 651 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 652 interrupt-names = "mux", "fil", "arp_ns"; 653 phy-mode = "rgmii"; 654 clocks = <&cpg CPG_MOD R9A08G045_ETH0_CLK_AXI>, 655 <&cpg CPG_MOD R9A08G045_ETH0_CLK_CHI>, 656 <&cpg CPG_MOD R9A08G045_ETH0_REFCLK>; 657 clock-names = "axi", "chi", "refclk"; 658 resets = <&cpg R9A08G045_ETH0_RST_HW_N>; 659 power-domains = <&cpg>; 660 #address-cells = <1>; 661 #size-cells = <0>; 662 status = "disabled"; 663 }; 664 665 eth1: ethernet@11c40000 { 666 compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth"; 667 reg = <0 0x11c40000 0 0x10000>; 668 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 669 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 670 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 671 interrupt-names = "mux", "fil", "arp_ns"; 672 phy-mode = "rgmii"; 673 clocks = <&cpg CPG_MOD R9A08G045_ETH1_CLK_AXI>, 674 <&cpg CPG_MOD R9A08G045_ETH1_CLK_CHI>, 675 <&cpg CPG_MOD R9A08G045_ETH1_REFCLK>; 676 clock-names = "axi", "chi", "refclk"; 677 resets = <&cpg R9A08G045_ETH1_RST_HW_N>; 678 power-domains = <&cpg>; 679 #address-cells = <1>; 680 #size-cells = <0>; 681 status = "disabled"; 682 }; 683 684 gic: interrupt-controller@12400000 { 685 compatible = "arm,gic-v3"; 686 #interrupt-cells = <3>; 687 #address-cells = <0>; 688 interrupt-controller; 689 reg = <0x0 0x12400000 0 0x20000>, 690 <0x0 0x12440000 0 0x40000>; 691 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 692 }; 693 694 wdt0: watchdog@12800800 { 695 compatible = "renesas,r9a08g045-wdt", "renesas,rzg2l-wdt"; 696 reg = <0 0x12800800 0 0x400>; 697 clocks = <&cpg CPG_MOD R9A08G045_WDT0_PCLK>, 698 <&cpg CPG_MOD R9A08G045_WDT0_CLK>; 699 clock-names = "pclk", "oscclk"; 700 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 701 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 702 interrupt-names = "wdt", "perrout"; 703 resets = <&cpg R9A08G045_WDT0_PRESETN>; 704 power-domains = <&cpg>; 705 status = "disabled"; 706 }; 707 }; 708 709 timer { 710 compatible = "arm,armv8-timer"; 711 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 712 <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 713 <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 714 <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 715 <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 716 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", 717 "hyp-virt"; 718 }; 719 720 vbattb_xtal: vbattb-xtal { 721 compatible = "fixed-clock"; 722 #clock-cells = <0>; 723 /* This value must be overridden by the board. */ 724 clock-frequency = <0>; 725 }; 726}; 727