1 /* $NetBSD: fpu_explode.c,v 1.6 2005/12/11 12:18:42 christos Exp $ */
2
3 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 * Copyright (c) 1992, 1993
7 * The Regents of the University of California. All rights reserved.
8 *
9 * This software was developed by the Computer Systems Engineering group
10 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
11 * contributed to Berkeley.
12 *
13 * All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by the University of
16 * California, Lawrence Berkeley Laboratory.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions
20 * are met:
21 * 1. Redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer.
23 * 2. Redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution.
26 * 3. Neither the name of the University nor the names of its contributors
27 * may be used to endorse or promote products derived from this software
28 * without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
33 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
38 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
39 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40 * SUCH DAMAGE.
41 */
42
43 /*
44 * FPU subroutines: `explode' the machine's `packed binary' format numbers
45 * into our internal format.
46 */
47
48 #include <sys/types.h>
49 #include <sys/systm.h>
50
51 #include <machine/fpu.h>
52 #include <machine/ieee.h>
53 #include <machine/pcb.h>
54
55 #include <powerpc/fpu/fpu_arith.h>
56 #include <powerpc/fpu/fpu_emu.h>
57 #include <powerpc/fpu/fpu_extern.h>
58 #include <powerpc/fpu/fpu_instr.h>
59
60 /*
61 * N.B.: in all of the following, we assume the FP format is
62 *
63 * ---------------------------
64 * | s | exponent | fraction |
65 * ---------------------------
66 *
67 * (which represents -1**s * 1.fraction * 2**exponent), so that the
68 * sign bit is way at the top (bit 31), the exponent is next, and
69 * then the remaining bits mark the fraction. A zero exponent means
70 * zero or denormalized (0.fraction rather than 1.fraction), and the
71 * maximum possible exponent, 2bias+1, signals inf (fraction==0) or NaN.
72 *
73 * Since the sign bit is always the topmost bit---this holds even for
74 * integers---we set that outside all the *tof functions. Each function
75 * returns the class code for the new number (but note that we use
76 * FPC_QNAN for all NaNs; fpu_explode will fix this if appropriate).
77 */
78
79 /*
80 * int -> fpn.
81 */
82 int
fpu_itof(struct fpn * fp,u_int i)83 fpu_itof(struct fpn *fp, u_int i)
84 {
85
86 if (i == 0)
87 return (FPC_ZERO);
88 /*
89 * The value FP_1 represents 2^FP_LG, so set the exponent
90 * there and let normalization fix it up. Convert negative
91 * numbers to sign-and-magnitude. Note that this relies on
92 * fpu_norm()'s handling of `supernormals'; see fpu_subr.c.
93 */
94 fp->fp_exp = FP_LG;
95 fp->fp_mant[0] = (int)i < 0 ? -i : i;
96 fp->fp_mant[1] = 0;
97 fp->fp_mant[2] = 0;
98 fp->fp_mant[3] = 0;
99 fpu_norm(fp);
100 return (FPC_NUM);
101 }
102
103 /*
104 * 64-bit int -> fpn.
105 */
106 int
fpu_xtof(struct fpn * fp,u_int64_t i)107 fpu_xtof(struct fpn *fp, u_int64_t i)
108 {
109
110 if (i == 0)
111 return (FPC_ZERO);
112 /*
113 * The value FP_1 represents 2^FP_LG, so set the exponent
114 * there and let normalization fix it up. Convert negative
115 * numbers to sign-and-magnitude. Note that this relies on
116 * fpu_norm()'s handling of `supernormals'; see fpu_subr.c.
117 */
118 fp->fp_exp = FP_LG2;
119 *((int64_t*)fp->fp_mant) = (int64_t)i < 0 ? -i : i;
120 fp->fp_mant[2] = 0;
121 fp->fp_mant[3] = 0;
122 fpu_norm(fp);
123 return (FPC_NUM);
124 }
125
126 #define mask(nbits) ((1L << (nbits)) - 1)
127
128 /*
129 * All external floating formats convert to internal in the same manner,
130 * as defined here. Note that only normals get an implied 1.0 inserted.
131 */
132 #define FP_TOF(exp, expbias, allfrac, f0, f1, f2, f3) \
133 if (exp == 0) { \
134 if (allfrac == 0) \
135 return (FPC_ZERO); \
136 fp->fp_exp = 1 - expbias; \
137 fp->fp_mant[0] = f0; \
138 fp->fp_mant[1] = f1; \
139 fp->fp_mant[2] = f2; \
140 fp->fp_mant[3] = f3; \
141 fpu_norm(fp); \
142 return (FPC_NUM); \
143 } \
144 if (exp == (2 * expbias + 1)) { \
145 if (allfrac == 0) \
146 return (FPC_INF); \
147 fp->fp_mant[0] = f0; \
148 fp->fp_mant[1] = f1; \
149 fp->fp_mant[2] = f2; \
150 fp->fp_mant[3] = f3; \
151 return (FPC_QNAN); \
152 } \
153 fp->fp_exp = exp - expbias; \
154 fp->fp_mant[0] = FP_1 | f0; \
155 fp->fp_mant[1] = f1; \
156 fp->fp_mant[2] = f2; \
157 fp->fp_mant[3] = f3; \
158 return (FPC_NUM)
159
160 /*
161 * 32-bit single precision -> fpn.
162 * We assume a single occupies at most (64-FP_LG) bits in the internal
163 * format: i.e., needs at most fp_mant[0] and fp_mant[1].
164 */
165 int
fpu_stof(struct fpn * fp,u_int i)166 fpu_stof(struct fpn *fp, u_int i)
167 {
168 int exp;
169 u_int frac, f0, f1;
170 #define SNG_SHIFT (SNG_FRACBITS - FP_LG)
171
172 exp = (i >> (32 - 1 - SNG_EXPBITS)) & mask(SNG_EXPBITS);
173 frac = i & mask(SNG_FRACBITS);
174 f0 = frac >> SNG_SHIFT;
175 f1 = frac << (32 - SNG_SHIFT);
176 FP_TOF(exp, SNG_EXP_BIAS, frac, f0, f1, 0, 0);
177 }
178
179 /*
180 * 64-bit double -> fpn.
181 * We assume this uses at most (96-FP_LG) bits.
182 */
183 int
fpu_dtof(struct fpn * fp,u_int i,u_int j)184 fpu_dtof(struct fpn *fp, u_int i, u_int j)
185 {
186 int exp;
187 u_int frac, f0, f1, f2;
188 #define DBL_SHIFT (DBL_FRACBITS - 32 - FP_LG)
189
190 exp = (i >> (32 - 1 - DBL_EXPBITS)) & mask(DBL_EXPBITS);
191 frac = i & mask(DBL_FRACBITS - 32);
192 f0 = frac >> DBL_SHIFT;
193 f1 = (frac << (32 - DBL_SHIFT)) | (j >> DBL_SHIFT);
194 f2 = j << (32 - DBL_SHIFT);
195 frac |= j;
196 FP_TOF(exp, DBL_EXP_BIAS, frac, f0, f1, f2, 0);
197 }
198
199 /*
200 * Explode the contents of a register / regpair / regquad.
201 * If the input is a signalling NaN, an NV (invalid) exception
202 * will be set. (Note that nothing but NV can occur until ALU
203 * operations are performed.)
204 */
205 void
fpu_explode(struct fpemu * fe,struct fpn * fp,int type,int reg)206 fpu_explode(struct fpemu *fe, struct fpn *fp, int type, int reg)
207 {
208 u_int s, *space;
209 u_int64_t l, *xspace;
210
211 xspace = (u_int64_t *)&fe->fe_fpstate->fpr[reg].fpr;
212 l = xspace[0];
213 space = (u_int *)&fe->fe_fpstate->fpr[reg].fpr;
214 s = space[0];
215 fp->fp_sign = s >> 31;
216 fp->fp_sticky = 0;
217 switch (type) {
218 case FTYPE_LNG:
219 s = fpu_xtof(fp, l);
220 break;
221
222 case FTYPE_INT:
223 s = fpu_itof(fp, space[1]);
224 break;
225
226 case FTYPE_SNG:
227 s = fpu_stof(fp, s);
228 break;
229
230 case FTYPE_DBL:
231 s = fpu_dtof(fp, s, space[1]);
232 break;
233
234 default:
235 panic("fpu_explode");
236 panic("fpu_explode: invalid type %d", type);
237 }
238
239 if (s == FPC_QNAN && (fp->fp_mant[0] & FP_QUIETBIT) == 0) {
240 /*
241 * Input is a signalling NaN. All operations that return
242 * an input NaN operand put it through a ``NaN conversion'',
243 * which basically just means ``turn on the quiet bit''.
244 * We do this here so that all NaNs internally look quiet
245 * (we can tell signalling ones by their class).
246 */
247 fp->fp_mant[0] |= FP_QUIETBIT;
248 fe->fe_cx = FPSCR_VXSNAN; /* assert invalid operand */
249 s = FPC_SNAN;
250 }
251 fp->fp_class = s;
252 DPRINTF(FPE_REG, ("fpu_explode: %%%c%d => ", (type == FTYPE_LNG) ? 'x' :
253 ((type == FTYPE_INT) ? 'i' :
254 ((type == FTYPE_SNG) ? 's' :
255 ((type == FTYPE_DBL) ? 'd' : '?'))),
256 reg));
257 DUMPFPN(FPE_REG, fp);
258 DPRINTF(FPE_REG, ("\n"));
259 }
260