1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2025 Oxide Computer Company 14 */ 15 16 #ifndef _SYS_NVME_PHISON_H 17 #define _SYS_NVME_PHISON_H 18 19 /* 20 * This header defines vendor-specific NVMe interfaces and is not a committed 21 * interface. Its contents and existence are subject to change. 22 * 23 * This header contains all of the current vendor-specific entries for known 24 * Phison devices as well as common structures and definitions that are shared 25 * across multiple device families. 26 */ 27 28 #ifdef __cplusplus 29 extern "C" { 30 #endif 31 32 #include <sys/nvme/ocp.h> 33 34 #define PHISON_PCI_VID 0x1987 35 #define PHISON_X200_DID 0x5302 36 37 typedef enum { 38 PHISON_X200_LOG_OCP_SMART = OCP_LOG_DSSD_SMART, 39 PHISON_X200_LOG_OCP_ERRREC = OCP_LOG_DSSD_ERROR_REC, 40 PHISON_X200_LOG_OCP_FWACT = OCP_LOG_DSSD_FWACT, 41 PHISON_X200_LOG_OCP_LATENCY = OCP_LOG_DSSD_LATENCY, 42 PHISON_X200_LOG_OCP_DEV_CAP = OCP_LOG_DSSD_DEV_CAP, 43 PHISON_X200_LOG_OCP_UNSUP = OCP_LOG_DSSD_UNSUP_REQ 44 } phison_x200_vul_t; 45 46 #ifdef __cplusplus 47 } 48 #endif 49 50 #endif /* _SYS_NVME_PHISON_H */ 51