1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved. 24 */ 25 26 #ifndef _PCI_I86PC_H 27 #define _PCI_I86PC_H 28 29 #include <pcibus_labels.h> 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 /* 36 * Data for label lookup based on existing slot label. 37 * 38 * Platforms may need entries here if the slot labels 39 * provided by firmware are incorrect. 40 * 41 * Note that re-writing to NULL provides a way of getting rid of totally 42 * spurious labels. 43 */ 44 45 slot_rwd_t x4600_rewrites[] = { 46 /* from hw, should be, test func */ 47 { "PCIX SLOT0", NULL, NULL }, 48 { "PCIX SLOT1", NULL, NULL }, 49 { "PCIX SLOT2", NULL, NULL }, 50 { "PCIExp SLOT2", NULL, NULL }, 51 { "PCIExp SLOT3", NULL, NULL }, 52 { "PCIExp SLOT4", NULL, NULL }, 53 { "PCIExp SLOT5", NULL, NULL }, 54 { "PCIExp SLOT6", NULL, NULL }, 55 { "PCIExp SLOT7", NULL, NULL }, 56 { "PCIExp SLOT8", NULL, NULL } 57 }; 58 59 slot_rwd_t netra_x4200_rewrites[] = { 60 /* from hw, should be, test func */ 61 { "PCIExp SLOT1", NULL, NULL }, 62 { "PCIX SLOT2", NULL, NULL }, 63 }; 64 65 slot_rwd_t x4250_rewrites[] = { 66 /* from hw, should be, test func */ 67 { "SLOT0", NULL, NULL }, 68 { "SLOT1", NULL, NULL }, 69 { "SLOT2", NULL, NULL } 70 }; 71 72 plat_rwd_t plat_rewrites[] = { 73 { "Sun-Fire-X4600", 74 sizeof (x4600_rewrites) / sizeof (slot_rwd_t), 75 x4600_rewrites }, 76 { "Sun-Fire-X4600-M2", 77 sizeof (x4600_rewrites) / sizeof (slot_rwd_t), 78 x4600_rewrites }, 79 { "Sun-Fire-X4250", 80 sizeof (x4250_rewrites) / sizeof (slot_rwd_t), 81 x4250_rewrites }, 82 { "Netra-X4200-M2", 83 sizeof (netra_x4200_rewrites) / sizeof (slot_rwd_t), 84 netra_x4200_rewrites } 85 }; 86 87 slotnm_rewrite_t SlotRWs = { 88 sizeof (plat_rewrites) / sizeof (plat_rwd_t), 89 plat_rewrites 90 }; 91 92 /* 93 * Data for label lookup based on device info. 94 * 95 * Platforms need entries here if there is no physical slot number 96 * or slot-names. 97 */ 98 99 extern int parent_is_rc(topo_mod_t *, did_t *); 100 extern int ba_is_2(topo_mod_t *, did_t *); 101 extern int ba_is_4(topo_mod_t *, did_t *); 102 103 devlab_t x4600_missing[] = { 104 /* board, bridge, root-complex, bus, dev, label, test func */ 105 { 0, 2, 2, -1, -1, "PCIExp SLOT4", parent_is_rc }, 106 { 0, 3, 3, -1, -1, "PCIExp SLOT2", parent_is_rc }, 107 { 0, 4, 4, -1, -1, "PCIExp SLOT3", parent_is_rc }, 108 { 0, 8, 8, -1, -1, "PCIExp SLOT7", parent_is_rc }, 109 { 0, 9, 9, -1, -1, "PCIExp SLOT5", parent_is_rc }, 110 { 0, 10, 10, -1, -1, "PCIExp SLOT6", parent_is_rc } 111 }; 112 113 devlab_t x4600m2_missing[] = { 114 /* board, bridge, root-complex, bus, dev, label, test func */ 115 { 0, 1, 1, -1, -1, "PCIExp SLOT4", parent_is_rc }, 116 { 0, 2, 2, -1, -1, "PCIExp SLOT2", parent_is_rc }, 117 { 0, 3, 3, -1, -1, "PCIExp SLOT3", parent_is_rc }, 118 { 0, 6, 6, -1, -1, "PCIExp SLOT7", parent_is_rc }, 119 { 0, 7, 7, -1, -1, "PCIExp SLOT5", parent_is_rc }, 120 { 0, 8, 8, -1, -1, "PCIExp SLOT6", parent_is_rc } 121 }; 122 123 devlab_t x4250_missing[] = { 124 /* board, bridge, root-complex, bus, dev, label, test func */ 125 { 0, 0, 0, -1, -1, "PCIExp SLOT3", ba_is_2 }, 126 { 0, 0, 0, -1, -1, "PCIExp SLOT0", ba_is_4 }, 127 { 0, 2, 2, -1, -1, "PCIExp SLOT4", ba_is_2 }, 128 { 0, 2, 2, -1, -1, "PCIExp SLOT1", ba_is_4 }, 129 { 0, 4, 4, -1, -1, "PCIExp SLOT5", ba_is_2 }, 130 { 0, 4, 4, -1, -1, "PCIExp SLOT2", ba_is_4 } 131 }; 132 133 devlab_t netra_x4200_missing[] = { 134 /* board, bridge, root-complex, bus, dev, label, test func */ 135 { 0, 4, 4, -1, -1, "PCIExp SLOT0", NULL }, 136 { 0, 0, 3 - TO_PCI, -1, -1, "PCIX SLOT", NULL }, 137 { 0, 0, 7 - TO_PCI, -1, -1, "PCIX SLOT", NULL } 138 }; 139 140 pdevlabs_t plats_missing[] = { 141 { "Sun-Fire-X4600", 142 sizeof (x4600_missing) / sizeof (devlab_t), 143 x4600_missing }, 144 { "Sun-Fire-X4600-M2", 145 sizeof (x4600m2_missing) / sizeof (devlab_t), 146 x4600m2_missing }, 147 { "Sun-Fire-X4250", 148 sizeof (x4250_missing) / sizeof (devlab_t), 149 x4250_missing }, 150 { "Netra-X4200-M2", 151 sizeof (netra_x4200_missing) / sizeof (devlab_t), 152 netra_x4200_missing } 153 }; 154 155 physnm_t x2100m2_pnms[] = { 156 /* Slot #, Label */ 157 { 37, "PCIe 0" }, 158 { 32, "PCIe 1" } 159 }; 160 161 physnm_t x2200m2_pnms[] = { 162 /* Slot #, Label */ 163 { 37, "PCIe 0" }, 164 { 32, "PCIe 1" } 165 }; 166 167 physnm_t x2250_pnms[] = { 168 /* Slot #, Label */ 169 { 6, "PCIe 0" } 170 }; 171 172 physnm_t x2270_pnms[] = { 173 /* Slot #, Label */ 174 { 55, "PCIe 0" } 175 }; 176 177 physnm_t x4170_pnms[] = { 178 /* Slot #, Label */ 179 { 1, "PCIe 0" }, 180 { 2, "PCIe 1" }, 181 { 3, "PCIe 2" } 182 }; 183 184 physnm_t x4270_pnms[] = { 185 /* Slot #, Label */ 186 { 1, "PCIe 0" }, 187 { 2, "PCIe 1" }, 188 { 3, "PCIe 2" }, 189 { 4, "PCIe 3" }, 190 { 5, "PCIe 4" }, 191 { 6, "PCIe 5" } 192 }; 193 194 physnm_t x4275_pnms[] = { 195 /* Slot #, Label */ 196 { 1, "PCIe 0" }, 197 { 2, "PCIe 1" }, 198 { 3, "PCIe 2" }, 199 { 4, "PCIe 3" }, 200 { 5, "PCIe 4" }, 201 { 6, "PCIe 5" } 202 }; 203 204 physnm_t netra4270_pnms[] = { 205 /* Slot #, Label */ 206 { 1, "PCIe 0" }, 207 { 2, "PCIe 1" }, 208 { 3, "PCIe 2" }, 209 { 5, "PCIe 4" }, 210 { 6, "PCIe 5" } 211 }; 212 213 physnm_t x4150_pnms[] = { 214 /* Slot #, Label */ 215 { 40, "PCIe 0" }, 216 { 48, "PCIe 1" }, 217 { 50, "PCIe 2" } 218 }; 219 220 physnm_t x4450_pnms[] = { 221 /* Slot #, Label */ 222 { 52, "PCIe 0" }, 223 { 54, "PCIe 1" }, 224 { 40, "PCIe 2" }, 225 { 49, "PCIe 3" }, 226 { 51, "PCIe 4" }, 227 { 41, "PCIe 5" } 228 }; 229 230 pphysnm_t plat_pnames[] = { 231 { "X2100-M2", 232 sizeof (x2100m2_pnms) / sizeof (physnm_t), 233 x2100m2_pnms }, 234 { "Sun-Fire-X2100-M2", 235 sizeof (x2100m2_pnms) / sizeof (physnm_t), 236 x2100m2_pnms }, 237 { "X2200-M2", 238 sizeof (x2200m2_pnms) / sizeof (physnm_t), 239 x2200m2_pnms }, 240 { "Sun-Fire-X2200-M2", 241 sizeof (x2200m2_pnms) / sizeof (physnm_t), 242 x2200m2_pnms }, 243 { "Sun-Fire-X2250", 244 sizeof (x2250_pnms) / sizeof (physnm_t), 245 x2250_pnms }, 246 { "Sun-Fire-X2270", 247 sizeof (x2270_pnms) / sizeof (physnm_t), 248 x2270_pnms }, 249 { "Sun-Fire-X4170", 250 sizeof (x4170_pnms) / sizeof (physnm_t), 251 x4170_pnms }, 252 { "Sun-Fire-X4270", 253 sizeof (x4270_pnms) / sizeof (physnm_t), 254 x4270_pnms }, 255 { "Sun-Fire-X4275", 256 sizeof (x4275_pnms) / sizeof (physnm_t), 257 x4275_pnms }, 258 { "Sun-Fire-X4170-Server", 259 sizeof (x4170_pnms) / sizeof (physnm_t), 260 x4170_pnms }, 261 { "Sun-Fire-X4270-Server", 262 sizeof (x4270_pnms) / sizeof (physnm_t), 263 x4270_pnms }, 264 { "Sun-Fire-X4275-Server", 265 sizeof (x4275_pnms) / sizeof (physnm_t), 266 x4275_pnms }, 267 { "Sun-Netra-X4270", 268 sizeof (netra4270_pnms) / sizeof (physnm_t), 269 netra4270_pnms }, 270 { "Sun-Fire-X4150", 271 sizeof (x4150_pnms) / sizeof (physnm_t), 272 x4150_pnms }, 273 { "Sun-Fire-X4450", 274 sizeof (x4450_pnms) / sizeof (physnm_t), 275 x4450_pnms } 276 }; 277 278 missing_names_t Missing = { 279 sizeof (plats_missing) / sizeof (pdevlabs_t), 280 plats_missing 281 }; 282 283 physlot_names_t PhyslotNMs = { 284 sizeof (plat_pnames) / sizeof (pphysnm_t), 285 plat_pnames 286 }; 287 288 slotnm_rewrite_t *Slot_Rewrites = &SlotRWs; 289 physlot_names_t *Physlot_Names = &PhyslotNMs; 290 missing_names_t *Missing_Names = &Missing; 291 292 #ifdef __cplusplus 293 } 294 #endif 295 296 #endif /* _PCI_I86PC_H */ 297