1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
23 * Use is subject to license terms.
24 */
25
26 #ifndef _NPI_TX_RD64_H
27 #define _NPI_TX_RD64_H
28
29 #ifdef __cplusplus
30 extern "C" {
31 #endif
32
33 #include <npi.h>
34
35 static void TXDMA_REG_READ64(npi_handle_t, uint64_t, int, uint64_t *);
36
37 /*
38 * TXDMA_REG_READ64
39 *
40 * Read a 64-bit value from a DMC register.
41 *
42 * Arguments:
43 * handle The NPI handle to use.
44 * offset The offset into the DMA CSR (the register).
45 * channel The channel, which is used as a multiplicand.
46 * value Where to put the 64-bit value to be read.
47 *
48 * Notes:
49 * For reference, here is the old macro:
50 *
51 * #define TXDMA_REG_READ64(handle, reg, channel, val_p) \
52 * NXGE_REG_RD64(handle, \
53 * (NXGE_TXDMA_OFFSET(reg, handle.is_vraddr, channel)), val_p)
54 *
55 * If handle.regp is a virtual address (the address of a VR),
56 * we have to subtract the value DMC right off the bat. DMC
57 * is defined as 0x600000, which works in a non-virtual address
58 * space, but not in a VR. In a VR, a DMA CSR's space begins
59 * at zero (0). So, since every call to RXMDA_REG_READ64 uses
60 * a register macro which adds in DMC, we have to subtract it.
61 *
62 * The rest of it is pretty straighforward. In a VR, a channel is
63 * logical, not absolute; and every DMA CSR is 512 bytes big;
64 * furthermore, a subpage of a VR is always ordered with the
65 * transmit CSRs first, followed by the receive CSRs. That is,
66 * a 512 byte space of Tx CSRs, followed by a 512 byte space of
67 * Rx CSRs. Hence this calculation:
68 *
69 * offset += ((channel << 1) << DMA_CSR_SLL);
70 *
71 * Here's an example:
72 *
73 * TXDMA_REG_READ64(handle, TX_CS_REG, channel, &value);
74 * Let's say channel is 3
75 * #define TX_CS_REG (DMC + 0x40028)
76 * offset = 0x640028
77 * offset &= 0xff = 0x28
78 * offset += ((3 << 1) << 9)
79 * 3 << 1 = 6
80 * 6 << 9 = 0xc00
81 * offset += 0xc00 = 0xc28
82 *
83 * Therefore, our register's (virtual) PIO address is 0xc28.
84 *
85 * cf. Table 10-6 on page 181 of the Neptune PRM, v 1.4:
86 *
87 * C00 - dFF CSRs for bound logical transmit DMA channel 3.
88 *
89 * In a non-virtual environment, you simply multiply the absolute
90 * channel number by 512 bytes, and get the correct offset to
91 * the register you're looking for. That is, the RX_DMA_CTL_STAT CSR,
92 * is, as are all of these registers, in a table where each channel
93 * is offset 512 bytes from the previous channel (count 16 step 512).
94 *
95 * offset += (channel << DMA_CSR_SLL); // channel<<9 = channel*512
96 *
97 * Here's an example:
98 *
99 * TXDMA_REG_READ64(handle, TX_CS_REG, channel, &value);
100 * Let's say channel is 3
101 * #define TX_CS_REG (DMC + 0x40028)
102 * offset = 0x640028
103 * offset += (3 << 9)
104 * 3 << 9 = 0x600
105 * offset += 0x600 = 0x640628
106 *
107 * Therefore, our register's PIO address is 0x640628.
108 *
109 * cf. Table 13-15 on page 265 of the Neptune PRM, v 1.4:
110 * TX_CS (DMC + 4002816) (count 24 step 0x200)
111 *
112 * Context:
113 * Any domain
114 *
115 */
116 extern const char *nxge_tx2str(int);
117
118 void
TXDMA_REG_READ64(npi_handle_t handle,uint64_t offset,int channel,uint64_t * value)119 TXDMA_REG_READ64(
120 npi_handle_t handle,
121 uint64_t offset,
122 int channel,
123 uint64_t *value)
124 {
125 #if defined(NPI_REG_TRACE)
126 const char *name = nxge_tx2str((int)offset);
127 #endif
128 if (handle.is_vraddr) {
129 offset &= DMA_CSR_MASK;
130 offset += ((channel << 1) << DMA_CSR_SLL);
131 } else {
132 offset += (channel << DMA_CSR_SLL);
133 }
134
135 #if defined(__i386)
136 *value = ddi_get64(handle.regh,
137 (uint64_t *)(handle.regp + (uint32_t)offset));
138 #else
139 *value = ddi_get64(handle.regh, (uint64_t *)(handle.regp + offset));
140 #endif
141
142 #if defined(NPI_REG_TRACE)
143 npi_trace_update(handle, B_FALSE, &npi_rtracebuf,
144 name, (uint32_t)offset, *value);
145 #elif defined(REG_SHOW)
146 /*
147 * Since we don't have a valid RTBUF index to show, send 0xBADBAD.
148 */
149 rt_show_reg(0xbadbad, B_FALSE, (uint32_t)offset, *value);
150 #endif
151 }
152
153 #ifdef __cplusplus
154 }
155 #endif
156
157 #endif /* _NPI_TX_RD64_H */
158