1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
23 * Use is subject to license terms.
24 */
25
26 #ifndef _NPI_RX_WR64_H
27 #define _NPI_RX_WR64_H
28
29 #ifdef __cplusplus
30 extern "C" {
31 #endif
32
33 #include <npi.h>
34
35 /*
36 * RXDMA_REG_WRITE64
37 *
38 * Write a 64-bit value to a DMC register.
39 *
40 * This is the old, rather convoluted, macro.
41 *
42 * #define RXDMA_REG_WRITE64(handle, reg, channel, data) { \
43 * NXGE_REG_WR64(handle, (NXGE_RXDMA_OFFSET(reg, handle.is_vraddr,\
44 * channel)), (data)) \
45 *
46 * There are 3 versions of NXGE_REG_WR64:
47 * -------------------------------------------------------------
48 * #if defined(REG_TRACE)
49 * #define NXGE_REG_WR64(handle, offset, val) { \
50 * NXGE_NPI_PIO_WRITE64(handle, (offset), (val)); \
51 * npi_rtrace_update(handle, B_TRUE, &npi_rtracebuf, (uint32_t)offset, \
52 * (uint64_t)(val)); \
53 * }
54 * #elif defined(REG_SHOW)
55 * #define NXGE_REG_WR64(handle, offset, val) {\
56 * NXGE_NPI_PIO_WRITE64(handle, offset, (val));\
57 * rt_show_reg(0xbadbad, B_TRUE, (uint32_t)offset, (uint64_t)(val));\
58 * }
59 * #else
60 * #define NXGE_REG_WR64(handle, offset, val) {\
61 * NXGE_NPI_PIO_WRITE64(handle, (offset), (val));\
62 * }
63 * #endif
64 *
65 * There are 2 versions of NXGE_NPI_PIO_WRITE64:
66 * -------------------------------------------------------------
67 * #if defined(__i386)
68 * #define NXGE_NPI_PIO_WRITE64(npi_handle, offset, data) \
69 * (ddi_put64(NPI_REGH(npi_handle), \
70 * (uint64_t *)(NPI_REGP(npi_handle) + (uint32_t)offset), data))
71 * #else
72 * #define NXGE_NPI_PIO_WRITE64(npi_handle, offset, data) \
73 * (ddi_put64(NPI_REGH(npi_handle), \
74 * (uint64_t *)(NPI_REGP(npi_handle) + offset), data))
75 * #endif
76 *
77 * -------------------------------------------------------------
78 * #define NPI_REGH(npi_handle) (npi_handle.regh)
79 * #define NPI_REGP(npi_handle) (npi_handle.regp)
80 *
81 * Now let's tackle NXGE_RXDMA_OFFSET
82 * -------------------------------------------------------------
83 * #define NXGE_RXDMA_OFFSET(x, v, channel) (x + \
84 * (!v ? DMC_OFFSET(channel) : \
85 * RDMC_PIOVADDR_OFFSET(channel)))
86 *
87 * -------------------------------------------------------------
88 * #define DMC_OFFSET(channel) (DMA_CSR_SIZE * channel)
89 *
90 * #define TDMC_PIOVADDR_OFFSET(channel) (2 * DMA_CSR_SIZE * channel)
91 * -------------------------------------------------------------
92 * #define RDMC_PIOVADDR_OFFSET(channel) \
93 * (TDMC_OFFSET(channel) + DMA_CSR_SIZE)
94 * -------------------------------------------------------------
95 * #define DMA_CSR_SIZE 512
96 *
97 * #define TDMC_OFFSET(channel) (TX_RNG_CFIG + DMA_CSR_SIZE * channel)
98 * #define TX_RNG_CFIG (DMC + 0x40000)
99 * -------------------------------------------------------------
100 * This definition is clearly wrong! I think this was intended:
101 *
102 * #define RDMC_PIOVADDR_OFFSET(channel) \
103 * (TDMC_PIOVADDR__OFFSET(channel) + DMA_CSR_SIZE)
104 * -------------------------------------------------------------
105 *
106 * Finally, we have the full macro:
107 * -------------------------------------------------------------
108 * #define RXDMA_REG_WRITE64(handle, reg, channel, data) { \
109 * NXGE_REG_WR64(handle, (NXGE_RXDMA_OFFSET(reg, handle.is_vraddr,\
110 * channel)), (data)) \
111 *
112 * ddi_put64(handle.regh, (uint64_t*)(handle.regp + ((0x600000 + 0x00000) +
113 * (!handle.is_vraddr ?
114 * (512 * channel) :
115 * (0x600000 + 0x40000 + 512 * channel + 512))), data);
116 */
117
118 static void RXDMA_REG_WRITE64(npi_handle_t, uint64_t, int, uint64_t);
119
120 /*
121 * RXDMA_REG_WRITE64
122 *
123 * Write a 64-bit value to a DMC register.
124 *
125 * Arguments:
126 * handle The NPI handle to use.
127 * offset The offset into the DMA CSR (the register).
128 * channel The channel, which is used as a multiplicand.
129 * value The 64-bit value to write.
130 *
131 * Notes:
132 * If handle.regp is a virtual address (the address of a VR),
133 * we have to subtract the value DMC right off the bat. DMC
134 * is defined as 0x600000, which works in a non-virtual address
135 * space, but not in a VR. In a VR, a DMA CSR's space begins
136 * at zero (0). So, since every call to RXMDA_REG_READ64 uses
137 * a register macro which adds in DMC, we have to subtract it.
138 *
139 * The rest of it is pretty straighforward. In a VR, a channel is
140 * logical, not absolute; and every DMA CSR is 512 bytes big;
141 * furthermore, a subpage of a VR is always ordered with the
142 * transmit CSRs first, followed by the receive CSRs. That is,
143 * a 512 byte space of Tx CSRs, followed by a 512 byte space of
144 * Rx CSRs. Hence this calculation:
145 *
146 * offset += ((channel << 1) + 1) << DMA_CSR_SLL;
147 *
148 * Here's an example:
149 *
150 * RXDMA_REG_WRITE64(handle, RX_DMA_CTL_STAT_REG, channel, value);
151 * Let's say channel is 3
152 * #define RX_DMA_CTL_STAT_REG (DMC + 0x00070)
153 * offset = 0x600070
154 * offset &= 0xff = 0x70
155 * offset += ((3 << 1) + 1) << 9
156 * 3 << 1 = 6
157 * 6 + 1 = 7
158 * 7 << 9 = 0xe00
159 * offset += 0xe00 = 0xe70
160 *
161 * Therefore, our register's (virtual) PIO address is 0xe70.
162 *
163 * cf. Table 10-6 on page 181 of the Neptune PRM, v 1.4:
164 *
165 * E00 - FFF CSRs for bound logical receive DMA channel 3.
166 *
167 * In a non-virtual environment, you simply multiply the absolute
168 * channel number by 512 bytes, and get the correct offset to
169 * the register you're looking for. That is, the RX_DMA_CTL_STAT CSR,
170 * is, as are all of these registers, in a table where each channel
171 * is offset 512 bytes from the previous channel (count 16 step 512).
172 *
173 * offset += (channel << DMA_CSR_SLL); // channel<<9 = channel*512
174 *
175 * Here's an example:
176 *
177 * RXDMA_REG_WRITE64(handle, RX_DMA_CTL_STAT_REG, channel, value);
178 * Let's say channel is 3
179 * #define RX_DMA_CTL_STAT_REG (DMC + 0x00070)
180 * offset = 0x600070
181 * offset += (3 << 9)
182 * 3 << 9 = 0x600
183 * offset += 0x600 = 0x600670
184 *
185 * Therefore, our register's PIO address is 0x600670.
186 *
187 * cf. Table 12-42 on page 234 of the Neptune PRM, v 1.4:
188 * RX_DMA_CTL_STAT (DMC + [0x]00070) (count 16 step [0x]200)
189 *
190 * Context:
191 * Any domain
192 *
193 */
194 extern const char *nxge_rx2str(int);
195
196 void
RXDMA_REG_WRITE64(npi_handle_t handle,uint64_t offset,int channel,uint64_t value)197 RXDMA_REG_WRITE64(
198 npi_handle_t handle,
199 uint64_t offset,
200 int channel,
201 uint64_t value)
202 {
203 #if defined(NPI_REG_TRACE)
204 const char *name = nxge_rx2str((int)offset);
205 #endif
206 if (handle.is_vraddr) {
207 offset &= DMA_CSR_MASK;
208 offset += (((channel << 1) + 1) << DMA_CSR_SLL);
209 } else {
210 offset += (channel << DMA_CSR_SLL);
211 }
212
213 #if defined(__i386)
214 ddi_put64(handle.regh,
215 (uint64_t *)(handle.regp + (uint32_t)offset), value);
216 #else
217 ddi_put64(handle.regh,
218 (uint64_t *)(handle.regp + offset), value);
219 #endif
220
221 #if defined(NPI_REG_TRACE)
222 npi_trace_update(handle, B_TRUE, &npi_rtracebuf,
223 name, (uint32_t)offset, value);
224 #elif defined(REG_SHOW)
225 /*
226 * Since we don't have a valid RTBUF index to show, send 0xBADBAD.
227 */
228 rt_show_reg(0xbadbad, B_TRUE, (uint32_t)offset, value);
229 #endif
230 }
231
232 #ifdef __cplusplus
233 }
234 #endif
235
236 #endif /* _NPI_RX_WR64_H */
237