1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
23 * Use is subject to license terms.
24 */
25
26 #ifndef _NPI_RX_RD64_H
27 #define _NPI_RX_RD64_H
28
29 #ifdef __cplusplus
30 extern "C" {
31 #endif
32
33 #include <npi.h>
34
35 /*
36 * RXDMA_REG_READ64
37 *
38 * Read a 64-bit value from a DMC register.
39 *
40 * This is the old, rather convoluted, macro:
41 *
42 * #define RXDMA_REG_READ64(handle, reg, channel, data_p) { \
43 * NXGE_REG_RD64(handle, (NXGE_RXDMA_OFFSET(reg, \
44 * handle.is_vraddr, channel)), (data_p))
45 *
46 * There are 4 versions of NXGE_REG_RD64:
47 * -------------------------------------------------------------
48 * #if defined(REG_TRACE)
49 * #define NXGE_REG_RD64(handle, offset, val_p) { \
50 * *(val_p) = NXGE_NPI_PIO_READ64(handle, offset); \
51 * npi_rtrace_update(handle, B_FALSE, &npi_rtracebuf, (uint32_t)offset, \
52 * (uint64_t)(*(val_p))); \
53 * }
54 * #elif defined(REG_SHOW)
55 * #define NXGE_REG_RD64(handle, offset, val_p) {\
56 * *(val_p) = NXGE_NPI_PIO_READ64(handle, offset);\
57 * rt_show_reg(0xbadbad, B_FALSE, (uint32_t)offset, (uint64_t)(*(val_p)));\
58 * }
59 * #elif defined(AXIS_DEBUG) && !defined(LEGION)
60 * #define NXGE_REG_RD64(handle, offset, val_p) {\
61 * int n; \
62 * for (n = 0; n < AXIS_WAIT_LOOP; n++) { \
63 * *(val_p) = 0; \
64 * *(val_p) = NXGE_NPI_PIO_READ64(handle, offset);\
65 * if (*(val_p) != (~0)) { \
66 * break; \
67 * } \
68 * drv_usecwait(AXIS_WAIT_PER_LOOP); \
69 * if (n < 20) { \
70 * cmn_err(CE_WARN, "NXGE_REG_RD64: loop %d " \
71 * "REG 0x%x(0x%llx)", \
72 * n, offset, *val_p);\
73 * } \
74 * } \
75 * if (n >= AXIS_WAIT_LOOP) { \
76 * cmn_err(CE_WARN, "(FATAL)NXGE_REG_RD64 on offset 0x%x " \
77 * "with -1!!!", offset); \
78 * } \
79 * }
80 * #else
81 * #define NXGE_REG_RD64(handle, offset, val_p) {\
82 * *(val_p) = NXGE_NPI_PIO_READ64(handle, offset);\
83 * }
84 * #endif
85 *
86 * There are 2 versions of NXGE_NPI_PIO_READ64:
87 * -------------------------------------------------------------
88 * #if defined(__i386)
89 * #define NXGE_NPI_PIO_READ64(npi_handle, offset) \
90 * (ddi_get64(NPI_REGH(npi_handle), \
91 * (uint64_t *)(NPI_REGP(npi_handle) + (uint32_t)offset)))
92 * #else
93 * #define NXGE_NPI_PIO_READ64(npi_handle, offset) \
94 * (ddi_get64(NPI_REGH(npi_handle), \
95 * (uint64_t *)(NPI_REGP(npi_handle) + offset)))
96 * #endif
97 *
98 * -------------------------------------------------------------
99 * #define NPI_REGH(npi_handle) (npi_handle.regh)
100 * #define NPI_REGP(npi_handle) (npi_handle.regp)
101 *
102 * Now let's tackle NXGE_RXDMA_OFFSET
103 * -------------------------------------------------------------
104 * #define NXGE_RXDMA_OFFSET(x, v, channel) (x + \
105 * (!v ? DMC_OFFSET(channel) : \
106 * RDMC_PIOVADDR_OFFSET(channel)))
107 *
108 * -------------------------------------------------------------
109 * #define DMC_OFFSET(channel) (DMA_CSR_SIZE * channel)
110 *
111 * #define TDMC_PIOVADDR_OFFSET(channel) (2 * DMA_CSR_SIZE * channel)
112 * -------------------------------------------------------------
113 * #define RDMC_PIOVADDR_OFFSET(channel) \
114 * (TDMC_OFFSET(channel) + DMA_CSR_SIZE)
115 * -------------------------------------------------------------
116 * #define DMA_CSR_SIZE 512
117 *
118 * #define TDMC_OFFSET(channel) (TX_RNG_CFIG + DMA_CSR_SIZE * channel)
119 * #define TX_RNG_CFIG (DMC + 0x40000)
120 * -------------------------------------------------------------
121 * This definition is clearly wrong! I think this was intended:
122 *
123 * #define RDMC_PIOVADDR_OFFSET(channel) \
124 * (TDMC_PIOVADDR__OFFSET(channel) + DMA_CSR_SIZE)
125 * -------------------------------------------------------------
126 *
127 * Finally, we have the full macro:
128 * -------------------------------------------------------------
129 * #define RXDMA_REG_READ64(handle, reg, channel, data_p) { \
130 * NXGE_REG_RD64(handle, (NXGE_RXDMA_OFFSET(reg, \
131 * handle.is_vraddr, channel)), (data_p))
132 *
133 * *data_p = ddi_get64(handle.regh, (uint64_t*)(handle.regp +
134 * ((0x600000+0x00000) +
135 * (!handle.is_vraddr ?
136 * (512 * channel) :
137 * 0x600000 + 0x40000 + (512 * channel) + 512)));
138 */
139
140 static void RXDMA_REG_READ64(npi_handle_t, uint64_t, int, uint64_t *);
141
142 /*
143 * RXDMA_REG_READ64
144 *
145 * Read a 64-bit value from a DMC register.
146 *
147 * Arguments:
148 * handle The NPI handle to use.
149 * offset The offset into the DMA CSR (the register).
150 * channel The channel, which is used as a multiplicand.
151 * value Where to put the 64-bit value to be read.
152 *
153 * Notes:
154 * If handle.regp is a virtual address (the address of a VR),
155 * we have to subtract the value DMC right off the bat. DMC
156 * is defined as 0x600000, which works in a non-virtual address
157 * space, but not in a VR. In a VR, a DMA CSR's space begins
158 * at zero (0). So, since every call to RXMDA_REG_READ64 uses
159 * a register macro which adds in DMC, we have to subtract it.
160 *
161 * The rest of it is pretty straighforward. In a VR, a channel is
162 * logical, not absolute; and every DMA CSR is 512 bytes big;
163 * furthermore, a subpage of a VR is always ordered with the
164 * transmit CSRs first, followed by the receive CSRs. That is,
165 * a 512 byte space of Tx CSRs, followed by a 512 byte space of
166 * Rx CSRs. Hence this calculation:
167 *
168 * offset += ((channel << 1) + 1) << DMA_CSR_SLL;
169 *
170 * Here's an example:
171 *
172 * RXDMA_REG_READ64(handle, RX_DMA_CTL_STAT_REG, channel, value);
173 * Let's say channel is 3
174 * #define RX_DMA_CTL_STAT_REG (DMC + 0x00070)
175 * offset = 0x600070
176 * offset &= 0xff = 0x70
177 * offset += ((3 << 1) + 1) << 9
178 * 3 << 1 = 6
179 * 6 + 1 = 7
180 * 7 << 9 = 0xe00
181 * offset += 0xe00 = 0xe70
182 *
183 * Therefore, our register's (virtual) PIO address is 0xe70.
184 *
185 * cf. Table 10-6 on page 181 of the Neptune PRM, v 1.4:
186 *
187 * E00 - FFF CSRs for bound logical receive DMA channel 3.
188 *
189 * In a non-virtual environment, you simply multiply the absolute
190 * channel number by 512 bytes, and get the correct offset to
191 * the register you're looking for. That is, the RX_DMA_CTL_STAT CSR,
192 * is, as are all of these registers, in a table where each channel
193 * is offset 512 bytes from the previous channel (count 16 step 512).
194 *
195 * offset += (channel << DMA_CSR_SLL); // channel<<9 = channel*512
196 *
197 * Here's an example:
198 *
199 * RXDMA_REG_READ64(handle, RX_DMA_CTL_STAT_REG, channel, value);
200 * Let's say channel is 3
201 * #define RX_DMA_CTL_STAT_REG (DMC + 0x00070)
202 * offset = 0x600070
203 * offset += (3 << 9)
204 * 3 << 9 = 0x600
205 * offset += 0x600 = 0x600670
206 *
207 * Therefore, our register's PIO address is 0x600670.
208 *
209 * cf. Table 12-42 on page 234 of the Neptune PRM, v 1.4:
210 * RX_DMA_CTL_STAT (DMC + [0x]00070) (count 16 step [0x]200)
211 *
212 * Context:
213 * Guest domain
214 *
215 */
216 extern const char *nxge_rx2str(int);
217
218 void
RXDMA_REG_READ64(npi_handle_t handle,uint64_t offset,int channel,uint64_t * value)219 RXDMA_REG_READ64(
220 npi_handle_t handle,
221 uint64_t offset,
222 int channel,
223 uint64_t *value)
224 {
225 #if defined(NPI_REG_TRACE)
226 const char *name = nxge_rx2str((int)offset);
227 #endif
228 if (handle.is_vraddr) {
229 offset &= DMA_CSR_MASK;
230 offset += (((channel << 1) + 1) << DMA_CSR_SLL);
231 } else {
232 offset += (channel << DMA_CSR_SLL);
233 }
234
235 #if defined(__i386)
236 *value = ddi_get64(handle.regh,
237 (uint64_t *)(handle.regp + (uint32_t)offset));
238 #else
239 *value = ddi_get64(handle.regh, (uint64_t *)(handle.regp + offset));
240 #endif
241
242 #if defined(NPI_REG_TRACE)
243 npi_trace_update(handle, B_FALSE, &npi_rtracebuf,
244 name, (uint32_t)offset, *value);
245 #elif defined(REG_SHOW)
246 /*
247 * Since we don't have a valid RTBUF index to show, send 0xBADBAD.
248 */
249 rt_show_reg(0xbadbad, B_FALSE, (uint32_t)offset, *value);
250 #endif
251 }
252
253 #ifdef __cplusplus
254 }
255 #endif
256
257 #endif /* _NPI_RX_RD64_H */
258