1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
23 * Use is subject to license terms.
24 */
25
26 #ifndef _NPI_RX_RD32_H
27 #define _NPI_RX_RD32_H
28
29 #pragma ident "%Z%%M% %I% %E% SMI"
30
31 #ifdef __cplusplus
32 extern "C" {
33 #endif
34
35 #include <npi.h>
36
37 static uint32_t RXDMA_REG_READ32(npi_handle_t, uint32_t, int);
38 #pragma inline(RXDMA_REG_READ32)
39
40 /*
41 * RXDMA_REG_READ32
42 *
43 * Read a 32-bit value from a DMC register.
44 *
45 * Arguments:
46 * handle The NPI handle to use.
47 * offset The offset into the DMA CSR (the register).
48 * channel The channel, which is used as a multiplicand.
49 *
50 * Notes:
51 * If handle.regp is a virtual address (the address of a VR),
52 * we have to subtract the value DMC right off the bat. DMC
53 * is defined as 0x600000, which works in a non-virtual address
54 * space, but not in a VR. In a VR, a DMA CSR's space begins
55 * at zero (0). So, since every call to RXMDA_REG_READ32 uses
56 * a register macro which adds in DMC, we have to subtract it.
57 *
58 * The rest of it is pretty straighforward. In a VR, a channel is
59 * logical, not absolute; and every DMA CSR is 512 bytes big;
60 * furthermore, a subpage of a VR is always ordered with the
61 * transmit CSRs first, followed by the receive CSRs. That is,
62 * a 512 byte space of Tx CSRs, followed by a 512 byte space of
63 * Rx CSRs. Hence this calculation:
64 *
65 * offset += ((channel << 1) + 1) << DMA_CSR_SLL;
66 *
67 * Here's an example:
68 *
69 * RXDMA_REG_READ32(handle, RX_DMA_CTL_STAT_REG, channel);
70 * Let's say channel is 3
71 * #define RX_DMA_CTL_STAT_REG (DMC + 0x00070)
72 * offset = 0x600070
73 * offset &= 0xff = 0x70
74 * offset += ((3 << 1) + 1) << 9
75 * 3 << 1 = 6
76 * 6 + 1 = 7
77 * 7 << 9 = 0xe00
78 * offset += 0xe00 = 0xe70
79 *
80 * Therefore, our register's (virtual) PIO address is 0xe70.
81 *
82 * cf. Table 10-6 on page 181 of the Neptune PRM, v 1.4:
83 *
84 * E00 - FFF CSRs for bound logical receive DMA channel 3.
85 *
86 * In a non-virtual environment, you simply multiply the absolute
87 * channel number by 512 bytes, and get the correct offset to
88 * the register you're looking for. That is, the RX_DMA_CTL_STAT CSR,
89 * is, as are all of these registers, in a table where each channel
90 * is offset 512 bytes from the previous channel (count 16 step 512).
91 *
92 * offset += (channel << DMA_CSR_SLL); // channel<<9 = channel*512
93 *
94 * Here's an example:
95 *
96 * RXDMA_REG_READ32(handle, RX_DMA_CTL_STAT_REG, channel);
97 * Let's say channel is 3
98 * #define RX_DMA_CTL_STAT_REG (DMC + 0x00070)
99 * offset = 0x600070
100 * offset += (3 << 9)
101 * 3 << 9 = 0x600
102 * offset += 0x600 = 0x600670
103 *
104 * Therefore, our register's PIO address is 0x600670.
105 *
106 * cf. Table 12-42 on page 234 of the Neptune PRM, v 1.4:
107 * RX_DMA_CTL_STAT (DMC + [0x]00070) (count 16 step [0x]200)
108 *
109 * Context:
110 * Guest domain
111 *
112 */
113 uint32_t
RXDMA_REG_READ32(npi_handle_t handle,uint32_t offset,int channel)114 RXDMA_REG_READ32(
115 npi_handle_t handle,
116 uint32_t offset,
117 int channel)
118 {
119 if (handle.is_vraddr) {
120 offset &= DMA_CSR_MASK;
121 offset += (((channel << 1) + 1) << DMA_CSR_SLL);
122 } else {
123 offset += (channel << DMA_CSR_SLL);
124 }
125
126 return (ddi_get32(handle.regh, (uint32_t *)(handle.regp + offset)));
127 }
128
129 #ifdef __cplusplus
130 }
131 #endif
132
133 #endif /* _NPI_RX_RD32_H */
134