1 /*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006 Cisco Systems. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #define LINUXKPI_PARAM_PREFIX mthca_
36
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/errno.h>
40 #include <linux/sched.h>
41 #include <linux/module.h>
42 #include <linux/slab.h>
43 #include <linux/page.h>
44 #include <asm/io.h>
45 #include <rdma/ib_mad.h>
46
47 #include "mthca_dev.h"
48 #include "mthca_config_reg.h"
49 #include "mthca_cmd.h"
50 #include "mthca_memfree.h"
51
52 #define CMD_POLL_TOKEN 0xffff
53
54 enum {
55 HCR_IN_PARAM_OFFSET = 0x00,
56 HCR_IN_MODIFIER_OFFSET = 0x08,
57 HCR_OUT_PARAM_OFFSET = 0x0c,
58 HCR_TOKEN_OFFSET = 0x14,
59 HCR_STATUS_OFFSET = 0x18,
60
61 HCR_OPMOD_SHIFT = 12,
62 HCA_E_BIT = 22,
63 HCR_GO_BIT = 23
64 };
65
66 enum {
67 /* initialization and general commands */
68 CMD_SYS_EN = 0x1,
69 CMD_SYS_DIS = 0x2,
70 CMD_MAP_FA = 0xfff,
71 CMD_UNMAP_FA = 0xffe,
72 CMD_RUN_FW = 0xff6,
73 CMD_MOD_STAT_CFG = 0x34,
74 CMD_QUERY_DEV_LIM = 0x3,
75 CMD_QUERY_FW = 0x4,
76 CMD_ENABLE_LAM = 0xff8,
77 CMD_DISABLE_LAM = 0xff7,
78 CMD_QUERY_DDR = 0x5,
79 CMD_QUERY_ADAPTER = 0x6,
80 CMD_INIT_HCA = 0x7,
81 CMD_CLOSE_HCA = 0x8,
82 CMD_INIT_IB = 0x9,
83 CMD_CLOSE_IB = 0xa,
84 CMD_QUERY_HCA = 0xb,
85 CMD_SET_IB = 0xc,
86 CMD_ACCESS_DDR = 0x2e,
87 CMD_MAP_ICM = 0xffa,
88 CMD_UNMAP_ICM = 0xff9,
89 CMD_MAP_ICM_AUX = 0xffc,
90 CMD_UNMAP_ICM_AUX = 0xffb,
91 CMD_SET_ICM_SIZE = 0xffd,
92
93 /* TPT commands */
94 CMD_SW2HW_MPT = 0xd,
95 CMD_QUERY_MPT = 0xe,
96 CMD_HW2SW_MPT = 0xf,
97 CMD_READ_MTT = 0x10,
98 CMD_WRITE_MTT = 0x11,
99 CMD_SYNC_TPT = 0x2f,
100
101 /* EQ commands */
102 CMD_MAP_EQ = 0x12,
103 CMD_SW2HW_EQ = 0x13,
104 CMD_HW2SW_EQ = 0x14,
105 CMD_QUERY_EQ = 0x15,
106
107 /* CQ commands */
108 CMD_SW2HW_CQ = 0x16,
109 CMD_HW2SW_CQ = 0x17,
110 CMD_QUERY_CQ = 0x18,
111 CMD_RESIZE_CQ = 0x2c,
112
113 /* SRQ commands */
114 CMD_SW2HW_SRQ = 0x35,
115 CMD_HW2SW_SRQ = 0x36,
116 CMD_QUERY_SRQ = 0x37,
117 CMD_ARM_SRQ = 0x40,
118
119 /* QP/EE commands */
120 CMD_RST2INIT_QPEE = 0x19,
121 CMD_INIT2RTR_QPEE = 0x1a,
122 CMD_RTR2RTS_QPEE = 0x1b,
123 CMD_RTS2RTS_QPEE = 0x1c,
124 CMD_SQERR2RTS_QPEE = 0x1d,
125 CMD_2ERR_QPEE = 0x1e,
126 CMD_RTS2SQD_QPEE = 0x1f,
127 CMD_SQD2SQD_QPEE = 0x38,
128 CMD_SQD2RTS_QPEE = 0x20,
129 CMD_ERR2RST_QPEE = 0x21,
130 CMD_QUERY_QPEE = 0x22,
131 CMD_INIT2INIT_QPEE = 0x2d,
132 CMD_SUSPEND_QPEE = 0x32,
133 CMD_UNSUSPEND_QPEE = 0x33,
134 /* special QPs and management commands */
135 CMD_CONF_SPECIAL_QP = 0x23,
136 CMD_MAD_IFC = 0x24,
137
138 /* multicast commands */
139 CMD_READ_MGM = 0x25,
140 CMD_WRITE_MGM = 0x26,
141 CMD_MGID_HASH = 0x27,
142
143 /* miscellaneous commands */
144 CMD_DIAG_RPRT = 0x30,
145 CMD_NOP = 0x31,
146
147 /* debug commands */
148 CMD_QUERY_DEBUG_MSG = 0x2a,
149 CMD_SET_DEBUG_MSG = 0x2b,
150 };
151
152 /*
153 * According to Mellanox code, FW may be starved and never complete
154 * commands. So we can't use strict timeouts described in PRM -- we
155 * just arbitrarily select 60 seconds for now.
156 */
157 #if 0
158 /*
159 * Round up and add 1 to make sure we get the full wait time (since we
160 * will be starting in the middle of a jiffy)
161 */
162 enum {
163 CMD_TIME_CLASS_A = (HZ + 999) / 1000 + 1,
164 CMD_TIME_CLASS_B = (HZ + 99) / 100 + 1,
165 CMD_TIME_CLASS_C = (HZ + 9) / 10 + 1,
166 CMD_TIME_CLASS_D = 60 * HZ
167 };
168 #else
169 #define CMD_TIME_CLASS_A (60 * HZ)
170 #define CMD_TIME_CLASS_B (60 * HZ)
171 #define CMD_TIME_CLASS_C (60 * HZ)
172 #define CMD_TIME_CLASS_D (60 * HZ)
173 #endif
174
175 #define GO_BIT_TIMEOUT (HZ * 10)
176
177 struct mthca_cmd_context {
178 struct completion done;
179 int result;
180 int next;
181 u64 out_param;
182 u16 token;
183 u8 status;
184 };
185
186 static int fw_cmd_doorbell = 0;
187 module_param(fw_cmd_doorbell, int, 0644);
188 MODULE_PARM_DESC(fw_cmd_doorbell, "post FW commands through doorbell page if nonzero "
189 "(and supported by FW)");
190
go_bit(struct mthca_dev * dev)191 static inline int go_bit(struct mthca_dev *dev)
192 {
193 return readl(dev->hcr + HCR_STATUS_OFFSET) &
194 swab32(1 << HCR_GO_BIT);
195 }
196
mthca_cmd_post_dbell(struct mthca_dev * dev,u64 in_param,u64 out_param,u32 in_modifier,u8 op_modifier,u16 op,u16 token)197 static void mthca_cmd_post_dbell(struct mthca_dev *dev,
198 u64 in_param,
199 u64 out_param,
200 u32 in_modifier,
201 u8 op_modifier,
202 u16 op,
203 u16 token)
204 {
205 void __iomem *ptr = dev->cmd.dbell_map;
206 u16 *offs = dev->cmd.dbell_offsets;
207
208 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), ptr + offs[0]);
209 wmb();
210 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), ptr + offs[1]);
211 wmb();
212 __raw_writel((__force u32) cpu_to_be32(in_modifier), ptr + offs[2]);
213 wmb();
214 __raw_writel((__force u32) cpu_to_be32(out_param >> 32), ptr + offs[3]);
215 wmb();
216 __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), ptr + offs[4]);
217 wmb();
218 __raw_writel((__force u32) cpu_to_be32(token << 16), ptr + offs[5]);
219 wmb();
220 __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) |
221 (1 << HCA_E_BIT) |
222 (op_modifier << HCR_OPMOD_SHIFT) |
223 op), ptr + offs[6]);
224 wmb();
225 __raw_writel((__force u32) 0, ptr + offs[7]);
226 wmb();
227 }
228
mthca_cmd_post_hcr(struct mthca_dev * dev,u64 in_param,u64 out_param,u32 in_modifier,u8 op_modifier,u16 op,u16 token,int event)229 static int mthca_cmd_post_hcr(struct mthca_dev *dev,
230 u64 in_param,
231 u64 out_param,
232 u32 in_modifier,
233 u8 op_modifier,
234 u16 op,
235 u16 token,
236 int event)
237 {
238 if (event) {
239 unsigned long end = jiffies + GO_BIT_TIMEOUT;
240
241 while (go_bit(dev) && time_before(jiffies, end)) {
242 set_current_state(TASK_RUNNING);
243 schedule();
244 }
245 }
246
247 if (go_bit(dev))
248 return -EAGAIN;
249
250 /*
251 * We use writel (instead of something like memcpy_toio)
252 * because writes of less than 32 bits to the HCR don't work
253 * (and some architectures such as ia64 implement memcpy_toio
254 * in terms of writeb).
255 */
256 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), dev->hcr + 0 * 4);
257 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), dev->hcr + 1 * 4);
258 __raw_writel((__force u32) cpu_to_be32(in_modifier), dev->hcr + 2 * 4);
259 __raw_writel((__force u32) cpu_to_be32(out_param >> 32), dev->hcr + 3 * 4);
260 __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), dev->hcr + 4 * 4);
261 __raw_writel((__force u32) cpu_to_be32(token << 16), dev->hcr + 5 * 4);
262
263 /* __raw_writel may not order writes. */
264 wmb();
265
266 __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) |
267 (event ? (1 << HCA_E_BIT) : 0) |
268 (op_modifier << HCR_OPMOD_SHIFT) |
269 op), dev->hcr + 6 * 4);
270
271 return 0;
272 }
273
mthca_cmd_post(struct mthca_dev * dev,u64 in_param,u64 out_param,u32 in_modifier,u8 op_modifier,u16 op,u16 token,int event)274 static int mthca_cmd_post(struct mthca_dev *dev,
275 u64 in_param,
276 u64 out_param,
277 u32 in_modifier,
278 u8 op_modifier,
279 u16 op,
280 u16 token,
281 int event)
282 {
283 int err = 0;
284
285 mutex_lock(&dev->cmd.hcr_mutex);
286
287 if (event && dev->cmd.flags & MTHCA_CMD_POST_DOORBELLS && fw_cmd_doorbell)
288 mthca_cmd_post_dbell(dev, in_param, out_param, in_modifier,
289 op_modifier, op, token);
290 else
291 err = mthca_cmd_post_hcr(dev, in_param, out_param, in_modifier,
292 op_modifier, op, token, event);
293
294 /*
295 * Make sure that our HCR writes don't get mixed in with
296 * writes from another CPU starting a FW command.
297 */
298 mmiowb();
299
300 mutex_unlock(&dev->cmd.hcr_mutex);
301 return err;
302 }
303
mthca_status_to_errno(u8 status)304 static int mthca_status_to_errno(u8 status)
305 {
306 static const int trans_table[] = {
307 [MTHCA_CMD_STAT_INTERNAL_ERR] = -EIO,
308 [MTHCA_CMD_STAT_BAD_OP] = -EPERM,
309 [MTHCA_CMD_STAT_BAD_PARAM] = -EINVAL,
310 [MTHCA_CMD_STAT_BAD_SYS_STATE] = -ENXIO,
311 [MTHCA_CMD_STAT_BAD_RESOURCE] = -EBADF,
312 [MTHCA_CMD_STAT_RESOURCE_BUSY] = -EBUSY,
313 [MTHCA_CMD_STAT_DDR_MEM_ERR] = -ENOMEM,
314 [MTHCA_CMD_STAT_EXCEED_LIM] = -ENOMEM,
315 [MTHCA_CMD_STAT_BAD_RES_STATE] = -EBADF,
316 [MTHCA_CMD_STAT_BAD_INDEX] = -EBADF,
317 [MTHCA_CMD_STAT_BAD_NVMEM] = -EFAULT,
318 [MTHCA_CMD_STAT_BAD_QPEE_STATE] = -EINVAL,
319 [MTHCA_CMD_STAT_BAD_SEG_PARAM] = -EFAULT,
320 [MTHCA_CMD_STAT_REG_BOUND] = -EBUSY,
321 [MTHCA_CMD_STAT_LAM_NOT_PRE] = -EAGAIN,
322 [MTHCA_CMD_STAT_BAD_PKT] = -EBADMSG,
323 [MTHCA_CMD_STAT_BAD_SIZE] = -ENOMEM,
324 };
325
326 if (status >= ARRAY_SIZE(trans_table) ||
327 (status != MTHCA_CMD_STAT_OK
328 && trans_table[status] == 0))
329 return -EINVAL;
330
331 return trans_table[status];
332 }
333
mthca_cmd_poll(struct mthca_dev * dev,u64 in_param,u64 * out_param,int out_is_imm,u32 in_modifier,u8 op_modifier,u16 op,unsigned long timeout)334 static int mthca_cmd_poll(struct mthca_dev *dev,
335 u64 in_param,
336 u64 *out_param,
337 int out_is_imm,
338 u32 in_modifier,
339 u8 op_modifier,
340 u16 op,
341 unsigned long timeout)
342 {
343 int err = 0;
344 unsigned long end;
345 u8 status;
346
347 down(&dev->cmd.poll_sem);
348
349 err = mthca_cmd_post(dev, in_param,
350 out_param ? *out_param : 0,
351 in_modifier, op_modifier,
352 op, CMD_POLL_TOKEN, 0);
353 if (err)
354 goto out;
355
356 end = timeout + jiffies;
357 while (go_bit(dev) && time_before(jiffies, end)) {
358 set_current_state(TASK_RUNNING);
359 schedule();
360 }
361
362 if (go_bit(dev)) {
363 err = -EBUSY;
364 goto out;
365 }
366
367 if (out_is_imm)
368 *out_param =
369 (u64) be32_to_cpu((__force __be32)
370 __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
371 (u64) be32_to_cpu((__force __be32)
372 __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET + 4));
373
374 status = be32_to_cpu((__force __be32) __raw_readl(dev->hcr + HCR_STATUS_OFFSET)) >> 24;
375 if (status) {
376 mthca_dbg(dev, "Command %02x completed with status %02x\n",
377 op, status);
378 err = mthca_status_to_errno(status);
379 }
380
381 out:
382 up(&dev->cmd.poll_sem);
383 return err;
384 }
385
mthca_cmd_event(struct mthca_dev * dev,u16 token,u8 status,u64 out_param)386 void mthca_cmd_event(struct mthca_dev *dev,
387 u16 token,
388 u8 status,
389 u64 out_param)
390 {
391 struct mthca_cmd_context *context =
392 &dev->cmd.context[token & dev->cmd.token_mask];
393
394 /* previously timed out command completing at long last */
395 if (token != context->token)
396 return;
397
398 context->result = 0;
399 context->status = status;
400 context->out_param = out_param;
401
402 complete(&context->done);
403 }
404
mthca_cmd_wait(struct mthca_dev * dev,u64 in_param,u64 * out_param,int out_is_imm,u32 in_modifier,u8 op_modifier,u16 op,unsigned long timeout)405 static int mthca_cmd_wait(struct mthca_dev *dev,
406 u64 in_param,
407 u64 *out_param,
408 int out_is_imm,
409 u32 in_modifier,
410 u8 op_modifier,
411 u16 op,
412 unsigned long timeout)
413 {
414 int err = 0;
415 struct mthca_cmd_context *context;
416
417 down(&dev->cmd.event_sem);
418
419 spin_lock(&dev->cmd.context_lock);
420 BUG_ON(dev->cmd.free_head < 0);
421 context = &dev->cmd.context[dev->cmd.free_head];
422 context->token += dev->cmd.token_mask + 1;
423 dev->cmd.free_head = context->next;
424 spin_unlock(&dev->cmd.context_lock);
425
426 init_completion(&context->done);
427
428 err = mthca_cmd_post(dev, in_param,
429 out_param ? *out_param : 0,
430 in_modifier, op_modifier,
431 op, context->token, 1);
432 if (err)
433 goto out;
434
435 if (!wait_for_completion_timeout(&context->done, timeout)) {
436 err = -EBUSY;
437 goto out;
438 }
439
440 err = context->result;
441 if (err)
442 goto out;
443
444 if (context->status) {
445 mthca_dbg(dev, "Command %02x completed with status %02x\n",
446 op, context->status);
447 err = mthca_status_to_errno(context->status);
448 }
449
450 if (out_is_imm)
451 *out_param = context->out_param;
452
453 out:
454 spin_lock(&dev->cmd.context_lock);
455 context->next = dev->cmd.free_head;
456 dev->cmd.free_head = context - dev->cmd.context;
457 spin_unlock(&dev->cmd.context_lock);
458
459 up(&dev->cmd.event_sem);
460 return err;
461 }
462
463 /* Invoke a command with an output mailbox */
mthca_cmd_box(struct mthca_dev * dev,u64 in_param,u64 out_param,u32 in_modifier,u8 op_modifier,u16 op,unsigned long timeout)464 static int mthca_cmd_box(struct mthca_dev *dev,
465 u64 in_param,
466 u64 out_param,
467 u32 in_modifier,
468 u8 op_modifier,
469 u16 op,
470 unsigned long timeout)
471 {
472 if (dev->cmd.flags & MTHCA_CMD_USE_EVENTS)
473 return mthca_cmd_wait(dev, in_param, &out_param, 0,
474 in_modifier, op_modifier, op,
475 timeout);
476 else
477 return mthca_cmd_poll(dev, in_param, &out_param, 0,
478 in_modifier, op_modifier, op,
479 timeout);
480 }
481
482 /* Invoke a command with no output parameter */
mthca_cmd(struct mthca_dev * dev,u64 in_param,u32 in_modifier,u8 op_modifier,u16 op,unsigned long timeout)483 static int mthca_cmd(struct mthca_dev *dev,
484 u64 in_param,
485 u32 in_modifier,
486 u8 op_modifier,
487 u16 op,
488 unsigned long timeout)
489 {
490 return mthca_cmd_box(dev, in_param, 0, in_modifier,
491 op_modifier, op, timeout);
492 }
493
494 /*
495 * Invoke a command with an immediate output parameter (and copy the
496 * output into the caller's out_param pointer after the command
497 * executes).
498 */
mthca_cmd_imm(struct mthca_dev * dev,u64 in_param,u64 * out_param,u32 in_modifier,u8 op_modifier,u16 op,unsigned long timeout)499 static int mthca_cmd_imm(struct mthca_dev *dev,
500 u64 in_param,
501 u64 *out_param,
502 u32 in_modifier,
503 u8 op_modifier,
504 u16 op,
505 unsigned long timeout)
506 {
507 if (dev->cmd.flags & MTHCA_CMD_USE_EVENTS)
508 return mthca_cmd_wait(dev, in_param, out_param, 1,
509 in_modifier, op_modifier, op,
510 timeout);
511 else
512 return mthca_cmd_poll(dev, in_param, out_param, 1,
513 in_modifier, op_modifier, op,
514 timeout);
515 }
516
mthca_cmd_init(struct mthca_dev * dev)517 int mthca_cmd_init(struct mthca_dev *dev)
518 {
519 mutex_init(&dev->cmd.hcr_mutex);
520 sema_init(&dev->cmd.poll_sem, 1);
521 dev->cmd.flags = 0;
522
523 dev->hcr = ioremap(pci_resource_start(dev->pdev, 0) + MTHCA_HCR_BASE,
524 MTHCA_HCR_SIZE);
525 if (!dev->hcr) {
526 mthca_err(dev, "Couldn't map command register.");
527 return -ENOMEM;
528 }
529
530 dev->cmd.pool = pci_pool_create("mthca_cmd", dev->pdev,
531 MTHCA_MAILBOX_SIZE,
532 MTHCA_MAILBOX_SIZE, 0);
533 if (!dev->cmd.pool) {
534 iounmap(dev->hcr);
535 return -ENOMEM;
536 }
537
538 return 0;
539 }
540
mthca_cmd_cleanup(struct mthca_dev * dev)541 void mthca_cmd_cleanup(struct mthca_dev *dev)
542 {
543 pci_pool_destroy(dev->cmd.pool);
544 iounmap(dev->hcr);
545 if (dev->cmd.flags & MTHCA_CMD_POST_DOORBELLS)
546 iounmap(dev->cmd.dbell_map);
547 }
548
549 /*
550 * Switch to using events to issue FW commands (should be called after
551 * event queue to command events has been initialized).
552 */
mthca_cmd_use_events(struct mthca_dev * dev)553 int mthca_cmd_use_events(struct mthca_dev *dev)
554 {
555 int i;
556
557 dev->cmd.context = kmalloc(dev->cmd.max_cmds *
558 sizeof (struct mthca_cmd_context),
559 GFP_KERNEL);
560 if (!dev->cmd.context)
561 return -ENOMEM;
562
563 for (i = 0; i < dev->cmd.max_cmds; ++i) {
564 dev->cmd.context[i].token = i;
565 dev->cmd.context[i].next = i + 1;
566 }
567
568 dev->cmd.context[dev->cmd.max_cmds - 1].next = -1;
569 dev->cmd.free_head = 0;
570
571 sema_init(&dev->cmd.event_sem, dev->cmd.max_cmds);
572 spin_lock_init(&dev->cmd.context_lock);
573
574 for (dev->cmd.token_mask = 1;
575 dev->cmd.token_mask < dev->cmd.max_cmds;
576 dev->cmd.token_mask <<= 1)
577 ; /* nothing */
578 --dev->cmd.token_mask;
579
580 dev->cmd.flags |= MTHCA_CMD_USE_EVENTS;
581
582 down(&dev->cmd.poll_sem);
583
584 return 0;
585 }
586
587 /*
588 * Switch back to polling (used when shutting down the device)
589 */
mthca_cmd_use_polling(struct mthca_dev * dev)590 void mthca_cmd_use_polling(struct mthca_dev *dev)
591 {
592 int i;
593
594 dev->cmd.flags &= ~MTHCA_CMD_USE_EVENTS;
595
596 for (i = 0; i < dev->cmd.max_cmds; ++i)
597 down(&dev->cmd.event_sem);
598
599 kfree(dev->cmd.context);
600
601 up(&dev->cmd.poll_sem);
602 }
603
mthca_alloc_mailbox(struct mthca_dev * dev,gfp_t gfp_mask)604 struct mthca_mailbox *mthca_alloc_mailbox(struct mthca_dev *dev,
605 gfp_t gfp_mask)
606 {
607 struct mthca_mailbox *mailbox;
608
609 mailbox = kmalloc(sizeof *mailbox, gfp_mask);
610 if (!mailbox)
611 return ERR_PTR(-ENOMEM);
612
613 mailbox->buf = pci_pool_alloc(dev->cmd.pool, gfp_mask, &mailbox->dma);
614 if (!mailbox->buf) {
615 kfree(mailbox);
616 return ERR_PTR(-ENOMEM);
617 }
618
619 return mailbox;
620 }
621
mthca_free_mailbox(struct mthca_dev * dev,struct mthca_mailbox * mailbox)622 void mthca_free_mailbox(struct mthca_dev *dev, struct mthca_mailbox *mailbox)
623 {
624 if (!mailbox)
625 return;
626
627 pci_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
628 kfree(mailbox);
629 }
630
mthca_SYS_EN(struct mthca_dev * dev)631 int mthca_SYS_EN(struct mthca_dev *dev)
632 {
633 u64 out;
634 int ret;
635
636 ret = mthca_cmd_imm(dev, 0, &out, 0, 0, CMD_SYS_EN, CMD_TIME_CLASS_D);
637
638 if (ret == -ENOMEM)
639 mthca_warn(dev, "SYS_EN DDR error: syn=%x, sock=%d, "
640 "sladdr=%d, SPD source=%s\n",
641 (int) (out >> 6) & 0xf, (int) (out >> 4) & 3,
642 (int) (out >> 1) & 7, (int) out & 1 ? "NVMEM" : "DIMM");
643
644 return ret;
645 }
646
mthca_SYS_DIS(struct mthca_dev * dev)647 int mthca_SYS_DIS(struct mthca_dev *dev)
648 {
649 return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, CMD_TIME_CLASS_C);
650 }
651
mthca_map_cmd(struct mthca_dev * dev,u16 op,struct mthca_icm * icm,u64 virt)652 static int mthca_map_cmd(struct mthca_dev *dev, u16 op, struct mthca_icm *icm,
653 u64 virt)
654 {
655 struct mthca_mailbox *mailbox;
656 struct mthca_icm_iter iter;
657 __be64 *pages;
658 int lg;
659 int nent = 0;
660 int i;
661 int err = 0;
662 #ifdef CONFIG_INFINIBAND_MTHCA_DEBUG
663 int ts = 0, tc = 0;
664 #endif /* CONFIG_INFINIBAND_MTHCA_DEBUG */
665
666 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
667 if (IS_ERR(mailbox))
668 return PTR_ERR(mailbox);
669 memset(mailbox->buf, 0, MTHCA_MAILBOX_SIZE);
670 pages = mailbox->buf;
671
672 for (mthca_icm_first(icm, &iter);
673 !mthca_icm_last(&iter);
674 mthca_icm_next(&iter)) {
675 /*
676 * We have to pass pages that are aligned to their
677 * size, so find the least significant 1 in the
678 * address or size and use that as our log2 size.
679 */
680 lg = ffs(mthca_icm_addr(&iter) | mthca_icm_size(&iter)) - 1;
681 if (lg < MTHCA_ICM_PAGE_SHIFT) {
682 mthca_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n",
683 MTHCA_ICM_PAGE_SIZE,
684 (unsigned long long) mthca_icm_addr(&iter),
685 mthca_icm_size(&iter));
686 err = -EINVAL;
687 goto out;
688 }
689 for (i = 0; i < mthca_icm_size(&iter) >> lg; ++i) {
690 if (virt != -1) {
691 pages[nent * 2] = cpu_to_be64(virt);
692 virt += 1 << lg;
693 }
694
695 pages[nent * 2 + 1] =
696 cpu_to_be64((mthca_icm_addr(&iter) + (i << lg)) |
697 (lg - MTHCA_ICM_PAGE_SHIFT));
698 #ifdef CONFIG_INFINIBAND_MTHCA_DEBUG
699 ts += 1 << (lg - 10);
700 ++tc;
701 #endif /* CONFIG_INFINIBAND_MTHCA_DEBUG */
702
703 if (++nent == MTHCA_MAILBOX_SIZE / 16) {
704 err = mthca_cmd(dev, mailbox->dma, nent, 0, op,
705 CMD_TIME_CLASS_B);
706 if (err)
707 goto out;
708 nent = 0;
709 }
710 }
711 }
712
713 if (nent)
714 err = mthca_cmd(dev, mailbox->dma, nent, 0, op,
715 CMD_TIME_CLASS_B);
716
717 switch (op) {
718 case CMD_MAP_FA:
719 mthca_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
720 break;
721 case CMD_MAP_ICM_AUX:
722 mthca_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
723 break;
724 case CMD_MAP_ICM:
725 mthca_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
726 tc, ts, (unsigned long long) virt - (ts << 10));
727 break;
728 }
729
730 out:
731 mthca_free_mailbox(dev, mailbox);
732 return err;
733 }
734
mthca_MAP_FA(struct mthca_dev * dev,struct mthca_icm * icm)735 int mthca_MAP_FA(struct mthca_dev *dev, struct mthca_icm *icm)
736 {
737 return mthca_map_cmd(dev, CMD_MAP_FA, icm, -1);
738 }
739
mthca_UNMAP_FA(struct mthca_dev * dev)740 int mthca_UNMAP_FA(struct mthca_dev *dev)
741 {
742 return mthca_cmd(dev, 0, 0, 0, CMD_UNMAP_FA, CMD_TIME_CLASS_B);
743 }
744
mthca_RUN_FW(struct mthca_dev * dev)745 int mthca_RUN_FW(struct mthca_dev *dev)
746 {
747 return mthca_cmd(dev, 0, 0, 0, CMD_RUN_FW, CMD_TIME_CLASS_A);
748 }
749
mthca_setup_cmd_doorbells(struct mthca_dev * dev,u64 base)750 static void mthca_setup_cmd_doorbells(struct mthca_dev *dev, u64 base)
751 {
752 phys_addr_t addr;
753 u16 max_off = 0;
754 int i;
755
756 for (i = 0; i < 8; ++i)
757 max_off = max(max_off, dev->cmd.dbell_offsets[i]);
758
759 if ((base & PAGE_MASK) != ((base + max_off) & PAGE_MASK)) {
760 mthca_warn(dev, "Firmware doorbell region at 0x%016llx, "
761 "length 0x%x crosses a page boundary\n",
762 (unsigned long long) base, max_off);
763 return;
764 }
765
766 addr = pci_resource_start(dev->pdev, 2) +
767 ((pci_resource_len(dev->pdev, 2) - 1) & base);
768 dev->cmd.dbell_map = ioremap(addr, max_off + sizeof(u32));
769 if (!dev->cmd.dbell_map)
770 return;
771
772 dev->cmd.flags |= MTHCA_CMD_POST_DOORBELLS;
773 mthca_dbg(dev, "Mapped doorbell page for posting FW commands\n");
774 }
775
mthca_QUERY_FW(struct mthca_dev * dev)776 int mthca_QUERY_FW(struct mthca_dev *dev)
777 {
778 struct mthca_mailbox *mailbox;
779 u32 *outbox;
780 u64 base;
781 u32 tmp;
782 int err = 0;
783 u8 lg;
784 int i;
785
786 #define QUERY_FW_OUT_SIZE 0x100
787 #define QUERY_FW_VER_OFFSET 0x00
788 #define QUERY_FW_MAX_CMD_OFFSET 0x0f
789 #define QUERY_FW_ERR_START_OFFSET 0x30
790 #define QUERY_FW_ERR_SIZE_OFFSET 0x38
791
792 #define QUERY_FW_CMD_DB_EN_OFFSET 0x10
793 #define QUERY_FW_CMD_DB_OFFSET 0x50
794 #define QUERY_FW_CMD_DB_BASE 0x60
795
796 #define QUERY_FW_START_OFFSET 0x20
797 #define QUERY_FW_END_OFFSET 0x28
798
799 #define QUERY_FW_SIZE_OFFSET 0x00
800 #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
801 #define QUERY_FW_EQ_ARM_BASE_OFFSET 0x40
802 #define QUERY_FW_EQ_SET_CI_BASE_OFFSET 0x48
803
804 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
805 if (IS_ERR(mailbox))
806 return PTR_ERR(mailbox);
807 outbox = mailbox->buf;
808
809 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_FW,
810 CMD_TIME_CLASS_A);
811
812 if (err)
813 goto out;
814
815 MTHCA_GET(dev->fw_ver, outbox, QUERY_FW_VER_OFFSET);
816 /*
817 * FW subminor version is at more significant bits than minor
818 * version, so swap here.
819 */
820 dev->fw_ver = (dev->fw_ver & 0xffff00000000ull) |
821 ((dev->fw_ver & 0xffff0000ull) >> 16) |
822 ((dev->fw_ver & 0x0000ffffull) << 16);
823
824 MTHCA_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
825 dev->cmd.max_cmds = 1 << lg;
826
827 mthca_dbg(dev, "FW version %012llx, max commands %d\n",
828 (unsigned long long) dev->fw_ver, dev->cmd.max_cmds);
829
830 MTHCA_GET(dev->catas_err.addr, outbox, QUERY_FW_ERR_START_OFFSET);
831 MTHCA_GET(dev->catas_err.size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
832
833 mthca_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x\n",
834 (unsigned long long) dev->catas_err.addr, dev->catas_err.size);
835
836 MTHCA_GET(tmp, outbox, QUERY_FW_CMD_DB_EN_OFFSET);
837 if (tmp & 0x1) {
838 mthca_dbg(dev, "FW supports commands through doorbells\n");
839
840 MTHCA_GET(base, outbox, QUERY_FW_CMD_DB_BASE);
841 for (i = 0; i < MTHCA_CMD_NUM_DBELL_DWORDS; ++i)
842 MTHCA_GET(dev->cmd.dbell_offsets[i], outbox,
843 QUERY_FW_CMD_DB_OFFSET + (i << 1));
844
845 mthca_setup_cmd_doorbells(dev, base);
846 }
847
848 if (mthca_is_memfree(dev)) {
849 MTHCA_GET(dev->fw.arbel.fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
850 MTHCA_GET(dev->fw.arbel.clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
851 MTHCA_GET(dev->fw.arbel.eq_arm_base, outbox, QUERY_FW_EQ_ARM_BASE_OFFSET);
852 MTHCA_GET(dev->fw.arbel.eq_set_ci_base, outbox, QUERY_FW_EQ_SET_CI_BASE_OFFSET);
853 mthca_dbg(dev, "FW size %d KB\n", dev->fw.arbel.fw_pages << 2);
854
855 /*
856 * Round up number of system pages needed in case
857 * MTHCA_ICM_PAGE_SIZE < PAGE_SIZE.
858 */
859 #if MTHCA_ICM_PAGE_SIZE < PAGE_SIZE
860 dev->fw.arbel.fw_pages =
861 ALIGN(dev->fw.arbel.fw_pages, PAGE_SIZE / MTHCA_ICM_PAGE_SIZE) >>
862 (PAGE_SHIFT - MTHCA_ICM_PAGE_SHIFT);
863 #endif
864
865 mthca_dbg(dev, "Clear int @ %llx, EQ arm @ %llx, EQ set CI @ %llx\n",
866 (unsigned long long) dev->fw.arbel.clr_int_base,
867 (unsigned long long) dev->fw.arbel.eq_arm_base,
868 (unsigned long long) dev->fw.arbel.eq_set_ci_base);
869 } else {
870 MTHCA_GET(dev->fw.tavor.fw_start, outbox, QUERY_FW_START_OFFSET);
871 MTHCA_GET(dev->fw.tavor.fw_end, outbox, QUERY_FW_END_OFFSET);
872
873 mthca_dbg(dev, "FW size %d KB (start %llx, end %llx)\n",
874 (int) ((dev->fw.tavor.fw_end - dev->fw.tavor.fw_start) >> 10),
875 (unsigned long long) dev->fw.tavor.fw_start,
876 (unsigned long long) dev->fw.tavor.fw_end);
877 }
878
879 out:
880 mthca_free_mailbox(dev, mailbox);
881 return err;
882 }
883
mthca_ENABLE_LAM(struct mthca_dev * dev)884 int mthca_ENABLE_LAM(struct mthca_dev *dev)
885 {
886 struct mthca_mailbox *mailbox;
887 u8 info;
888 u32 *outbox;
889 int err = 0;
890
891 #define ENABLE_LAM_OUT_SIZE 0x100
892 #define ENABLE_LAM_START_OFFSET 0x00
893 #define ENABLE_LAM_END_OFFSET 0x08
894 #define ENABLE_LAM_INFO_OFFSET 0x13
895
896 #define ENABLE_LAM_INFO_HIDDEN_FLAG (1 << 4)
897 #define ENABLE_LAM_INFO_ECC_MASK 0x3
898
899 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
900 if (IS_ERR(mailbox))
901 return PTR_ERR(mailbox);
902 outbox = mailbox->buf;
903
904 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_ENABLE_LAM,
905 CMD_TIME_CLASS_C);
906
907 if (err)
908 goto out;
909
910 MTHCA_GET(dev->ddr_start, outbox, ENABLE_LAM_START_OFFSET);
911 MTHCA_GET(dev->ddr_end, outbox, ENABLE_LAM_END_OFFSET);
912 MTHCA_GET(info, outbox, ENABLE_LAM_INFO_OFFSET);
913
914 if (!!(info & ENABLE_LAM_INFO_HIDDEN_FLAG) !=
915 !!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) {
916 mthca_info(dev, "FW reports that HCA-attached memory "
917 "is %s hidden; does not match PCI config\n",
918 (info & ENABLE_LAM_INFO_HIDDEN_FLAG) ?
919 "" : "not");
920 }
921 if (info & ENABLE_LAM_INFO_HIDDEN_FLAG)
922 mthca_dbg(dev, "HCA-attached memory is hidden.\n");
923
924 mthca_dbg(dev, "HCA memory size %d KB (start %llx, end %llx)\n",
925 (int) ((dev->ddr_end - dev->ddr_start) >> 10),
926 (unsigned long long) dev->ddr_start,
927 (unsigned long long) dev->ddr_end);
928
929 out:
930 mthca_free_mailbox(dev, mailbox);
931 return err;
932 }
933
mthca_DISABLE_LAM(struct mthca_dev * dev)934 int mthca_DISABLE_LAM(struct mthca_dev *dev)
935 {
936 return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, CMD_TIME_CLASS_C);
937 }
938
mthca_QUERY_DDR(struct mthca_dev * dev)939 int mthca_QUERY_DDR(struct mthca_dev *dev)
940 {
941 struct mthca_mailbox *mailbox;
942 u8 info;
943 u32 *outbox;
944 int err = 0;
945
946 #define QUERY_DDR_OUT_SIZE 0x100
947 #define QUERY_DDR_START_OFFSET 0x00
948 #define QUERY_DDR_END_OFFSET 0x08
949 #define QUERY_DDR_INFO_OFFSET 0x13
950
951 #define QUERY_DDR_INFO_HIDDEN_FLAG (1 << 4)
952 #define QUERY_DDR_INFO_ECC_MASK 0x3
953
954 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
955 if (IS_ERR(mailbox))
956 return PTR_ERR(mailbox);
957 outbox = mailbox->buf;
958
959 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_DDR,
960 CMD_TIME_CLASS_A);
961
962 if (err)
963 goto out;
964
965 MTHCA_GET(dev->ddr_start, outbox, QUERY_DDR_START_OFFSET);
966 MTHCA_GET(dev->ddr_end, outbox, QUERY_DDR_END_OFFSET);
967 MTHCA_GET(info, outbox, QUERY_DDR_INFO_OFFSET);
968
969 if (!!(info & QUERY_DDR_INFO_HIDDEN_FLAG) !=
970 !!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) {
971 mthca_info(dev, "FW reports that HCA-attached memory "
972 "is %s hidden; does not match PCI config\n",
973 (info & QUERY_DDR_INFO_HIDDEN_FLAG) ?
974 "" : "not");
975 }
976 if (info & QUERY_DDR_INFO_HIDDEN_FLAG)
977 mthca_dbg(dev, "HCA-attached memory is hidden.\n");
978
979 mthca_dbg(dev, "HCA memory size %d KB (start %llx, end %llx)\n",
980 (int) ((dev->ddr_end - dev->ddr_start) >> 10),
981 (unsigned long long) dev->ddr_start,
982 (unsigned long long) dev->ddr_end);
983
984 out:
985 mthca_free_mailbox(dev, mailbox);
986 return err;
987 }
988
mthca_QUERY_DEV_LIM(struct mthca_dev * dev,struct mthca_dev_lim * dev_lim)989 int mthca_QUERY_DEV_LIM(struct mthca_dev *dev,
990 struct mthca_dev_lim *dev_lim)
991 {
992 struct mthca_mailbox *mailbox;
993 u32 *outbox;
994 u8 field;
995 u16 size;
996 u16 stat_rate;
997 int err;
998
999 #define QUERY_DEV_LIM_OUT_SIZE 0x100
1000 #define QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET 0x10
1001 #define QUERY_DEV_LIM_MAX_QP_SZ_OFFSET 0x11
1002 #define QUERY_DEV_LIM_RSVD_QP_OFFSET 0x12
1003 #define QUERY_DEV_LIM_MAX_QP_OFFSET 0x13
1004 #define QUERY_DEV_LIM_RSVD_SRQ_OFFSET 0x14
1005 #define QUERY_DEV_LIM_MAX_SRQ_OFFSET 0x15
1006 #define QUERY_DEV_LIM_RSVD_EEC_OFFSET 0x16
1007 #define QUERY_DEV_LIM_MAX_EEC_OFFSET 0x17
1008 #define QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET 0x19
1009 #define QUERY_DEV_LIM_RSVD_CQ_OFFSET 0x1a
1010 #define QUERY_DEV_LIM_MAX_CQ_OFFSET 0x1b
1011 #define QUERY_DEV_LIM_MAX_MPT_OFFSET 0x1d
1012 #define QUERY_DEV_LIM_RSVD_EQ_OFFSET 0x1e
1013 #define QUERY_DEV_LIM_MAX_EQ_OFFSET 0x1f
1014 #define QUERY_DEV_LIM_RSVD_MTT_OFFSET 0x20
1015 #define QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET 0x21
1016 #define QUERY_DEV_LIM_RSVD_MRW_OFFSET 0x22
1017 #define QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET 0x23
1018 #define QUERY_DEV_LIM_MAX_AV_OFFSET 0x27
1019 #define QUERY_DEV_LIM_MAX_REQ_QP_OFFSET 0x29
1020 #define QUERY_DEV_LIM_MAX_RES_QP_OFFSET 0x2b
1021 #define QUERY_DEV_LIM_MAX_RDMA_OFFSET 0x2f
1022 #define QUERY_DEV_LIM_RSZ_SRQ_OFFSET 0x33
1023 #define QUERY_DEV_LIM_ACK_DELAY_OFFSET 0x35
1024 #define QUERY_DEV_LIM_MTU_WIDTH_OFFSET 0x36
1025 #define QUERY_DEV_LIM_VL_PORT_OFFSET 0x37
1026 #define QUERY_DEV_LIM_MAX_GID_OFFSET 0x3b
1027 #define QUERY_DEV_LIM_RATE_SUPPORT_OFFSET 0x3c
1028 #define QUERY_DEV_LIM_MAX_PKEY_OFFSET 0x3f
1029 #define QUERY_DEV_LIM_FLAGS_OFFSET 0x44
1030 #define QUERY_DEV_LIM_RSVD_UAR_OFFSET 0x48
1031 #define QUERY_DEV_LIM_UAR_SZ_OFFSET 0x49
1032 #define QUERY_DEV_LIM_PAGE_SZ_OFFSET 0x4b
1033 #define QUERY_DEV_LIM_MAX_SG_OFFSET 0x51
1034 #define QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET 0x52
1035 #define QUERY_DEV_LIM_MAX_SG_RQ_OFFSET 0x55
1036 #define QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET 0x56
1037 #define QUERY_DEV_LIM_MAX_QP_MCG_OFFSET 0x61
1038 #define QUERY_DEV_LIM_RSVD_MCG_OFFSET 0x62
1039 #define QUERY_DEV_LIM_MAX_MCG_OFFSET 0x63
1040 #define QUERY_DEV_LIM_RSVD_PD_OFFSET 0x64
1041 #define QUERY_DEV_LIM_MAX_PD_OFFSET 0x65
1042 #define QUERY_DEV_LIM_RSVD_RDD_OFFSET 0x66
1043 #define QUERY_DEV_LIM_MAX_RDD_OFFSET 0x67
1044 #define QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET 0x80
1045 #define QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET 0x82
1046 #define QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET 0x84
1047 #define QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET 0x86
1048 #define QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET 0x88
1049 #define QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET 0x8a
1050 #define QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET 0x8c
1051 #define QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET 0x8e
1052 #define QUERY_DEV_LIM_MTT_ENTRY_SZ_OFFSET 0x90
1053 #define QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET 0x92
1054 #define QUERY_DEV_LIM_PBL_SZ_OFFSET 0x96
1055 #define QUERY_DEV_LIM_BMME_FLAGS_OFFSET 0x97
1056 #define QUERY_DEV_LIM_RSVD_LKEY_OFFSET 0x98
1057 #define QUERY_DEV_LIM_LAMR_OFFSET 0x9f
1058 #define QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET 0xa0
1059
1060 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1061 if (IS_ERR(mailbox))
1062 return PTR_ERR(mailbox);
1063 outbox = mailbox->buf;
1064
1065 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_DEV_LIM,
1066 CMD_TIME_CLASS_A);
1067
1068 if (err)
1069 goto out;
1070
1071 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_QP_OFFSET);
1072 dev_lim->reserved_qps = 1 << (field & 0xf);
1073 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_OFFSET);
1074 dev_lim->max_qps = 1 << (field & 0x1f);
1075 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_SRQ_OFFSET);
1076 dev_lim->reserved_srqs = 1 << (field >> 4);
1077 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_OFFSET);
1078 dev_lim->max_srqs = 1 << (field & 0x1f);
1079 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EEC_OFFSET);
1080 dev_lim->reserved_eecs = 1 << (field & 0xf);
1081 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EEC_OFFSET);
1082 dev_lim->max_eecs = 1 << (field & 0x1f);
1083 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET);
1084 dev_lim->max_cq_sz = 1 << field;
1085 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_CQ_OFFSET);
1086 dev_lim->reserved_cqs = 1 << (field & 0xf);
1087 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_OFFSET);
1088 dev_lim->max_cqs = 1 << (field & 0x1f);
1089 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MPT_OFFSET);
1090 dev_lim->max_mpts = 1 << (field & 0x3f);
1091 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EQ_OFFSET);
1092 dev_lim->reserved_eqs = 1 << (field & 0xf);
1093 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EQ_OFFSET);
1094 dev_lim->max_eqs = 1 << (field & 0x7);
1095 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MTT_OFFSET);
1096 if (mthca_is_memfree(dev))
1097 dev_lim->reserved_mtts = ALIGN((1 << (field >> 4)) * sizeof(u64),
1098 dev->limits.mtt_seg_size) / dev->limits.mtt_seg_size;
1099 else
1100 dev_lim->reserved_mtts = 1 << (field >> 4);
1101 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET);
1102 dev_lim->max_mrw_sz = 1 << field;
1103 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MRW_OFFSET);
1104 dev_lim->reserved_mrws = 1 << (field & 0xf);
1105 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET);
1106 dev_lim->max_mtt_seg = 1 << (field & 0x3f);
1107 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_REQ_QP_OFFSET);
1108 dev_lim->max_requester_per_qp = 1 << (field & 0x3f);
1109 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RES_QP_OFFSET);
1110 dev_lim->max_responder_per_qp = 1 << (field & 0x3f);
1111 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDMA_OFFSET);
1112 dev_lim->max_rdma_global = 1 << (field & 0x3f);
1113 MTHCA_GET(field, outbox, QUERY_DEV_LIM_ACK_DELAY_OFFSET);
1114 dev_lim->local_ca_ack_delay = field & 0x1f;
1115 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MTU_WIDTH_OFFSET);
1116 dev_lim->max_mtu = field >> 4;
1117 dev_lim->max_port_width = field & 0xf;
1118 MTHCA_GET(field, outbox, QUERY_DEV_LIM_VL_PORT_OFFSET);
1119 dev_lim->max_vl = field >> 4;
1120 dev_lim->num_ports = field & 0xf;
1121 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_GID_OFFSET);
1122 dev_lim->max_gids = 1 << (field & 0xf);
1123 MTHCA_GET(stat_rate, outbox, QUERY_DEV_LIM_RATE_SUPPORT_OFFSET);
1124 dev_lim->stat_rate_support = stat_rate;
1125 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PKEY_OFFSET);
1126 dev_lim->max_pkeys = 1 << (field & 0xf);
1127 MTHCA_GET(dev_lim->flags, outbox, QUERY_DEV_LIM_FLAGS_OFFSET);
1128 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_UAR_OFFSET);
1129 dev_lim->reserved_uars = field >> 4;
1130 MTHCA_GET(field, outbox, QUERY_DEV_LIM_UAR_SZ_OFFSET);
1131 dev_lim->uar_size = 1 << ((field & 0x3f) + 20);
1132 MTHCA_GET(field, outbox, QUERY_DEV_LIM_PAGE_SZ_OFFSET);
1133 dev_lim->min_page_sz = 1 << field;
1134 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_OFFSET);
1135 dev_lim->max_sg = field;
1136
1137 MTHCA_GET(size, outbox, QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET);
1138 dev_lim->max_desc_sz = size;
1139
1140 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_MCG_OFFSET);
1141 dev_lim->max_qp_per_mcg = 1 << field;
1142 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MCG_OFFSET);
1143 dev_lim->reserved_mgms = field & 0xf;
1144 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MCG_OFFSET);
1145 dev_lim->max_mcgs = 1 << field;
1146 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_PD_OFFSET);
1147 dev_lim->reserved_pds = field >> 4;
1148 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PD_OFFSET);
1149 dev_lim->max_pds = 1 << (field & 0x3f);
1150 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_RDD_OFFSET);
1151 dev_lim->reserved_rdds = field >> 4;
1152 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDD_OFFSET);
1153 dev_lim->max_rdds = 1 << (field & 0x3f);
1154
1155 MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET);
1156 dev_lim->eec_entry_sz = size;
1157 MTHCA_GET(size, outbox, QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET);
1158 dev_lim->qpc_entry_sz = size;
1159 MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET);
1160 dev_lim->eeec_entry_sz = size;
1161 MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET);
1162 dev_lim->eqpc_entry_sz = size;
1163 MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET);
1164 dev_lim->eqc_entry_sz = size;
1165 MTHCA_GET(size, outbox, QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET);
1166 dev_lim->cqc_entry_sz = size;
1167 MTHCA_GET(size, outbox, QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET);
1168 dev_lim->srq_entry_sz = size;
1169 MTHCA_GET(size, outbox, QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET);
1170 dev_lim->uar_scratch_entry_sz = size;
1171
1172 if (mthca_is_memfree(dev)) {
1173 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET);
1174 dev_lim->max_srq_sz = 1 << field;
1175 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_SZ_OFFSET);
1176 dev_lim->max_qp_sz = 1 << field;
1177 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSZ_SRQ_OFFSET);
1178 dev_lim->hca.arbel.resize_srq = field & 1;
1179 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_RQ_OFFSET);
1180 dev_lim->max_sg = min_t(int, field, dev_lim->max_sg);
1181 MTHCA_GET(size, outbox, QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET);
1182 dev_lim->max_desc_sz = min_t(int, size, dev_lim->max_desc_sz);
1183 MTHCA_GET(size, outbox, QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET);
1184 dev_lim->mpt_entry_sz = size;
1185 MTHCA_GET(field, outbox, QUERY_DEV_LIM_PBL_SZ_OFFSET);
1186 dev_lim->hca.arbel.max_pbl_sz = 1 << (field & 0x3f);
1187 MTHCA_GET(dev_lim->hca.arbel.bmme_flags, outbox,
1188 QUERY_DEV_LIM_BMME_FLAGS_OFFSET);
1189 MTHCA_GET(dev_lim->hca.arbel.reserved_lkey, outbox,
1190 QUERY_DEV_LIM_RSVD_LKEY_OFFSET);
1191 MTHCA_GET(field, outbox, QUERY_DEV_LIM_LAMR_OFFSET);
1192 dev_lim->hca.arbel.lam_required = field & 1;
1193 MTHCA_GET(dev_lim->hca.arbel.max_icm_sz, outbox,
1194 QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET);
1195
1196 if (dev_lim->hca.arbel.bmme_flags & 1)
1197 mthca_dbg(dev, "Base MM extensions: yes "
1198 "(flags %d, max PBL %d, rsvd L_Key %08x)\n",
1199 dev_lim->hca.arbel.bmme_flags,
1200 dev_lim->hca.arbel.max_pbl_sz,
1201 dev_lim->hca.arbel.reserved_lkey);
1202 else
1203 mthca_dbg(dev, "Base MM extensions: no\n");
1204
1205 mthca_dbg(dev, "Max ICM size %lld MB\n",
1206 (unsigned long long) dev_lim->hca.arbel.max_icm_sz >> 20);
1207 } else {
1208 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET);
1209 dev_lim->max_srq_sz = (1 << field) - 1;
1210 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_SZ_OFFSET);
1211 dev_lim->max_qp_sz = (1 << field) - 1;
1212 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_AV_OFFSET);
1213 dev_lim->hca.tavor.max_avs = 1 << (field & 0x3f);
1214 dev_lim->mpt_entry_sz = MTHCA_MPT_ENTRY_SIZE;
1215 }
1216
1217 mthca_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
1218 dev_lim->max_qps, dev_lim->reserved_qps, dev_lim->qpc_entry_sz);
1219 mthca_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
1220 dev_lim->max_srqs, dev_lim->reserved_srqs, dev_lim->srq_entry_sz);
1221 mthca_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
1222 dev_lim->max_cqs, dev_lim->reserved_cqs, dev_lim->cqc_entry_sz);
1223 mthca_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
1224 dev_lim->max_eqs, dev_lim->reserved_eqs, dev_lim->eqc_entry_sz);
1225 mthca_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
1226 dev_lim->reserved_mrws, dev_lim->reserved_mtts);
1227 mthca_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
1228 dev_lim->max_pds, dev_lim->reserved_pds, dev_lim->reserved_uars);
1229 mthca_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
1230 dev_lim->max_pds, dev_lim->reserved_mgms);
1231 mthca_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
1232 dev_lim->max_cq_sz, dev_lim->max_qp_sz, dev_lim->max_srq_sz);
1233
1234 mthca_dbg(dev, "Flags: %08x\n", dev_lim->flags);
1235
1236 out:
1237 mthca_free_mailbox(dev, mailbox);
1238 return err;
1239 }
1240
get_board_id(void * vsd,char * board_id)1241 static void get_board_id(void *vsd, char *board_id)
1242 {
1243 int i;
1244
1245 #define VSD_OFFSET_SIG1 0x00
1246 #define VSD_OFFSET_SIG2 0xde
1247 #define VSD_OFFSET_MLX_BOARD_ID 0xd0
1248 #define VSD_OFFSET_TS_BOARD_ID 0x20
1249
1250 #define VSD_SIGNATURE_TOPSPIN 0x5ad
1251
1252 memset(board_id, 0, MTHCA_BOARD_ID_LEN);
1253
1254 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
1255 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
1256 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MTHCA_BOARD_ID_LEN);
1257 } else {
1258 /*
1259 * The board ID is a string but the firmware byte
1260 * swaps each 4-byte word before passing it back to
1261 * us. Therefore we need to swab it before printing.
1262 */
1263 for (i = 0; i < 4; ++i)
1264 ((u32 *) board_id)[i] =
1265 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
1266 }
1267 }
1268
mthca_QUERY_ADAPTER(struct mthca_dev * dev,struct mthca_adapter * adapter)1269 int mthca_QUERY_ADAPTER(struct mthca_dev *dev,
1270 struct mthca_adapter *adapter)
1271 {
1272 struct mthca_mailbox *mailbox;
1273 u32 *outbox;
1274 int err;
1275
1276 #define QUERY_ADAPTER_OUT_SIZE 0x100
1277 #define QUERY_ADAPTER_VENDOR_ID_OFFSET 0x00
1278 #define QUERY_ADAPTER_DEVICE_ID_OFFSET 0x04
1279 #define QUERY_ADAPTER_REVISION_ID_OFFSET 0x08
1280 #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
1281 #define QUERY_ADAPTER_VSD_OFFSET 0x20
1282
1283 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1284 if (IS_ERR(mailbox))
1285 return PTR_ERR(mailbox);
1286 outbox = mailbox->buf;
1287
1288 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_ADAPTER,
1289 CMD_TIME_CLASS_A);
1290
1291 if (err)
1292 goto out;
1293
1294 if (!mthca_is_memfree(dev)) {
1295 MTHCA_GET(adapter->vendor_id, outbox,
1296 QUERY_ADAPTER_VENDOR_ID_OFFSET);
1297 MTHCA_GET(adapter->device_id, outbox,
1298 QUERY_ADAPTER_DEVICE_ID_OFFSET);
1299 MTHCA_GET(adapter->revision_id, outbox,
1300 QUERY_ADAPTER_REVISION_ID_OFFSET);
1301 }
1302 MTHCA_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
1303
1304 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
1305 adapter->board_id);
1306
1307 out:
1308 mthca_free_mailbox(dev, mailbox);
1309 return err;
1310 }
1311
mthca_INIT_HCA(struct mthca_dev * dev,struct mthca_init_hca_param * param)1312 int mthca_INIT_HCA(struct mthca_dev *dev,
1313 struct mthca_init_hca_param *param)
1314 {
1315 struct mthca_mailbox *mailbox;
1316 __be32 *inbox;
1317 int err;
1318
1319 #define INIT_HCA_IN_SIZE 0x200
1320 #define INIT_HCA_FLAGS1_OFFSET 0x00c
1321 #define INIT_HCA_FLAGS2_OFFSET 0x014
1322 #define INIT_HCA_QPC_OFFSET 0x020
1323 #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
1324 #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
1325 #define INIT_HCA_EEC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x20)
1326 #define INIT_HCA_LOG_EEC_OFFSET (INIT_HCA_QPC_OFFSET + 0x27)
1327 #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
1328 #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
1329 #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
1330 #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
1331 #define INIT_HCA_EQPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
1332 #define INIT_HCA_EEEC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
1333 #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
1334 #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
1335 #define INIT_HCA_RDB_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
1336 #define INIT_HCA_UDAV_OFFSET 0x0b0
1337 #define INIT_HCA_UDAV_LKEY_OFFSET (INIT_HCA_UDAV_OFFSET + 0x0)
1338 #define INIT_HCA_UDAV_PD_OFFSET (INIT_HCA_UDAV_OFFSET + 0x4)
1339 #define INIT_HCA_MCAST_OFFSET 0x0c0
1340 #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
1341 #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1342 #define INIT_HCA_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
1343 #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
1344 #define INIT_HCA_TPT_OFFSET 0x0f0
1345 #define INIT_HCA_MPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
1346 #define INIT_HCA_MTT_SEG_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x09)
1347 #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
1348 #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
1349 #define INIT_HCA_UAR_OFFSET 0x120
1350 #define INIT_HCA_UAR_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x00)
1351 #define INIT_HCA_UARC_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x09)
1352 #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
1353 #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
1354 #define INIT_HCA_UAR_SCATCH_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x10)
1355 #define INIT_HCA_UAR_CTX_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x18)
1356
1357 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1358 if (IS_ERR(mailbox))
1359 return PTR_ERR(mailbox);
1360 inbox = mailbox->buf;
1361
1362 memset(inbox, 0, INIT_HCA_IN_SIZE);
1363
1364 if (dev->mthca_flags & MTHCA_FLAG_SINAI_OPT)
1365 MTHCA_PUT(inbox, 0x1, INIT_HCA_FLAGS1_OFFSET);
1366
1367 #if defined(__LITTLE_ENDIAN)
1368 *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
1369 #elif defined(__BIG_ENDIAN)
1370 *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) |= cpu_to_be32(1 << 1);
1371 #else
1372 #error Host endianness not defined
1373 #endif
1374 /* Check port for UD address vector: */
1375 *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) |= cpu_to_be32(1);
1376
1377 /* Enable IPoIB checksumming if we can: */
1378 if (dev->device_cap_flags & IB_DEVICE_UD_IP_CSUM)
1379 *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) |= cpu_to_be32(7 << 3);
1380
1381 /* We leave wqe_quota, responder_exu, etc as 0 (default) */
1382
1383 /* QPC/EEC/CQC/EQC/RDB attributes */
1384
1385 MTHCA_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
1386 MTHCA_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
1387 MTHCA_PUT(inbox, param->eec_base, INIT_HCA_EEC_BASE_OFFSET);
1388 MTHCA_PUT(inbox, param->log_num_eecs, INIT_HCA_LOG_EEC_OFFSET);
1389 MTHCA_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
1390 MTHCA_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1391 MTHCA_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
1392 MTHCA_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
1393 MTHCA_PUT(inbox, param->eqpc_base, INIT_HCA_EQPC_BASE_OFFSET);
1394 MTHCA_PUT(inbox, param->eeec_base, INIT_HCA_EEEC_BASE_OFFSET);
1395 MTHCA_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
1396 MTHCA_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
1397 MTHCA_PUT(inbox, param->rdb_base, INIT_HCA_RDB_BASE_OFFSET);
1398
1399 /* UD AV attributes */
1400
1401 /* multicast attributes */
1402
1403 MTHCA_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
1404 MTHCA_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1405 MTHCA_PUT(inbox, param->mc_hash_sz, INIT_HCA_MC_HASH_SZ_OFFSET);
1406 MTHCA_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1407
1408 /* TPT attributes */
1409
1410 MTHCA_PUT(inbox, param->mpt_base, INIT_HCA_MPT_BASE_OFFSET);
1411 if (!mthca_is_memfree(dev))
1412 MTHCA_PUT(inbox, param->mtt_seg_sz, INIT_HCA_MTT_SEG_SZ_OFFSET);
1413 MTHCA_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
1414 MTHCA_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
1415
1416 /* UAR attributes */
1417 {
1418 u8 uar_page_sz = PAGE_SHIFT - 12;
1419 MTHCA_PUT(inbox, uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1420 }
1421
1422 MTHCA_PUT(inbox, param->uar_scratch_base, INIT_HCA_UAR_SCATCH_BASE_OFFSET);
1423
1424 if (mthca_is_memfree(dev)) {
1425 MTHCA_PUT(inbox, param->log_uarc_sz, INIT_HCA_UARC_SZ_OFFSET);
1426 MTHCA_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
1427 MTHCA_PUT(inbox, param->uarc_base, INIT_HCA_UAR_CTX_BASE_OFFSET);
1428 }
1429
1430 err = mthca_cmd(dev, mailbox->dma, 0, 0,
1431 CMD_INIT_HCA, CMD_TIME_CLASS_D);
1432
1433 mthca_free_mailbox(dev, mailbox);
1434 return err;
1435 }
1436
mthca_INIT_IB(struct mthca_dev * dev,struct mthca_init_ib_param * param,int port)1437 int mthca_INIT_IB(struct mthca_dev *dev,
1438 struct mthca_init_ib_param *param,
1439 int port)
1440 {
1441 struct mthca_mailbox *mailbox;
1442 u32 *inbox;
1443 int err;
1444 u32 flags;
1445
1446 #define INIT_IB_IN_SIZE 56
1447 #define INIT_IB_FLAGS_OFFSET 0x00
1448 #define INIT_IB_FLAG_SIG (1 << 18)
1449 #define INIT_IB_FLAG_NG (1 << 17)
1450 #define INIT_IB_FLAG_G0 (1 << 16)
1451 #define INIT_IB_VL_SHIFT 4
1452 #define INIT_IB_PORT_WIDTH_SHIFT 8
1453 #define INIT_IB_MTU_SHIFT 12
1454 #define INIT_IB_MAX_GID_OFFSET 0x06
1455 #define INIT_IB_MAX_PKEY_OFFSET 0x0a
1456 #define INIT_IB_GUID0_OFFSET 0x10
1457 #define INIT_IB_NODE_GUID_OFFSET 0x18
1458 #define INIT_IB_SI_GUID_OFFSET 0x20
1459
1460 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1461 if (IS_ERR(mailbox))
1462 return PTR_ERR(mailbox);
1463 inbox = mailbox->buf;
1464
1465 memset(inbox, 0, INIT_IB_IN_SIZE);
1466
1467 flags = 0;
1468 flags |= param->set_guid0 ? INIT_IB_FLAG_G0 : 0;
1469 flags |= param->set_node_guid ? INIT_IB_FLAG_NG : 0;
1470 flags |= param->set_si_guid ? INIT_IB_FLAG_SIG : 0;
1471 flags |= param->vl_cap << INIT_IB_VL_SHIFT;
1472 flags |= param->port_width << INIT_IB_PORT_WIDTH_SHIFT;
1473 flags |= param->mtu_cap << INIT_IB_MTU_SHIFT;
1474 MTHCA_PUT(inbox, flags, INIT_IB_FLAGS_OFFSET);
1475
1476 MTHCA_PUT(inbox, param->gid_cap, INIT_IB_MAX_GID_OFFSET);
1477 MTHCA_PUT(inbox, param->pkey_cap, INIT_IB_MAX_PKEY_OFFSET);
1478 MTHCA_PUT(inbox, param->guid0, INIT_IB_GUID0_OFFSET);
1479 MTHCA_PUT(inbox, param->node_guid, INIT_IB_NODE_GUID_OFFSET);
1480 MTHCA_PUT(inbox, param->si_guid, INIT_IB_SI_GUID_OFFSET);
1481
1482 err = mthca_cmd(dev, mailbox->dma, port, 0, CMD_INIT_IB,
1483 CMD_TIME_CLASS_A);
1484
1485 mthca_free_mailbox(dev, mailbox);
1486 return err;
1487 }
1488
mthca_CLOSE_IB(struct mthca_dev * dev,int port)1489 int mthca_CLOSE_IB(struct mthca_dev *dev, int port)
1490 {
1491 return mthca_cmd(dev, 0, port, 0, CMD_CLOSE_IB, CMD_TIME_CLASS_A);
1492 }
1493
mthca_CLOSE_HCA(struct mthca_dev * dev,int panic)1494 int mthca_CLOSE_HCA(struct mthca_dev *dev, int panic)
1495 {
1496 return mthca_cmd(dev, 0, 0, panic, CMD_CLOSE_HCA, CMD_TIME_CLASS_C);
1497 }
1498
mthca_SET_IB(struct mthca_dev * dev,struct mthca_set_ib_param * param,int port)1499 int mthca_SET_IB(struct mthca_dev *dev, struct mthca_set_ib_param *param,
1500 int port)
1501 {
1502 struct mthca_mailbox *mailbox;
1503 u32 *inbox;
1504 int err;
1505 u32 flags = 0;
1506
1507 #define SET_IB_IN_SIZE 0x40
1508 #define SET_IB_FLAGS_OFFSET 0x00
1509 #define SET_IB_FLAG_SIG (1 << 18)
1510 #define SET_IB_FLAG_RQK (1 << 0)
1511 #define SET_IB_CAP_MASK_OFFSET 0x04
1512 #define SET_IB_SI_GUID_OFFSET 0x08
1513
1514 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1515 if (IS_ERR(mailbox))
1516 return PTR_ERR(mailbox);
1517 inbox = mailbox->buf;
1518
1519 memset(inbox, 0, SET_IB_IN_SIZE);
1520
1521 flags |= param->set_si_guid ? SET_IB_FLAG_SIG : 0;
1522 flags |= param->reset_qkey_viol ? SET_IB_FLAG_RQK : 0;
1523 MTHCA_PUT(inbox, flags, SET_IB_FLAGS_OFFSET);
1524
1525 MTHCA_PUT(inbox, param->cap_mask, SET_IB_CAP_MASK_OFFSET);
1526 MTHCA_PUT(inbox, param->si_guid, SET_IB_SI_GUID_OFFSET);
1527
1528 err = mthca_cmd(dev, mailbox->dma, port, 0, CMD_SET_IB,
1529 CMD_TIME_CLASS_B);
1530
1531 mthca_free_mailbox(dev, mailbox);
1532 return err;
1533 }
1534
mthca_MAP_ICM(struct mthca_dev * dev,struct mthca_icm * icm,u64 virt)1535 int mthca_MAP_ICM(struct mthca_dev *dev, struct mthca_icm *icm, u64 virt)
1536 {
1537 return mthca_map_cmd(dev, CMD_MAP_ICM, icm, virt);
1538 }
1539
mthca_MAP_ICM_page(struct mthca_dev * dev,u64 dma_addr,u64 virt)1540 int mthca_MAP_ICM_page(struct mthca_dev *dev, u64 dma_addr, u64 virt)
1541 {
1542 struct mthca_mailbox *mailbox;
1543 __be64 *inbox;
1544 int err;
1545
1546 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1547 if (IS_ERR(mailbox))
1548 return PTR_ERR(mailbox);
1549 inbox = mailbox->buf;
1550
1551 inbox[0] = cpu_to_be64(virt);
1552 inbox[1] = cpu_to_be64(dma_addr);
1553
1554 err = mthca_cmd(dev, mailbox->dma, 1, 0, CMD_MAP_ICM,
1555 CMD_TIME_CLASS_B);
1556
1557 mthca_free_mailbox(dev, mailbox);
1558
1559 if (!err)
1560 mthca_dbg(dev, "Mapped page at %llx to %llx for ICM.\n",
1561 (unsigned long long) dma_addr, (unsigned long long) virt);
1562
1563 return err;
1564 }
1565
mthca_UNMAP_ICM(struct mthca_dev * dev,u64 virt,u32 page_count)1566 int mthca_UNMAP_ICM(struct mthca_dev *dev, u64 virt, u32 page_count)
1567 {
1568 mthca_dbg(dev, "Unmapping %d pages at %llx from ICM.\n",
1569 page_count, (unsigned long long) virt);
1570
1571 return mthca_cmd(dev, virt, page_count, 0,
1572 CMD_UNMAP_ICM, CMD_TIME_CLASS_B);
1573 }
1574
mthca_MAP_ICM_AUX(struct mthca_dev * dev,struct mthca_icm * icm)1575 int mthca_MAP_ICM_AUX(struct mthca_dev *dev, struct mthca_icm *icm)
1576 {
1577 return mthca_map_cmd(dev, CMD_MAP_ICM_AUX, icm, -1);
1578 }
1579
mthca_UNMAP_ICM_AUX(struct mthca_dev * dev)1580 int mthca_UNMAP_ICM_AUX(struct mthca_dev *dev)
1581 {
1582 return mthca_cmd(dev, 0, 0, 0, CMD_UNMAP_ICM_AUX, CMD_TIME_CLASS_B);
1583 }
1584
mthca_SET_ICM_SIZE(struct mthca_dev * dev,u64 icm_size,u64 * aux_pages)1585 int mthca_SET_ICM_SIZE(struct mthca_dev *dev, u64 icm_size, u64 *aux_pages)
1586 {
1587 int ret = mthca_cmd_imm(dev, icm_size, aux_pages, 0,
1588 0, CMD_SET_ICM_SIZE, CMD_TIME_CLASS_A);
1589
1590 if (ret)
1591 return ret;
1592
1593 /*
1594 * Round up number of system pages needed in case
1595 * MTHCA_ICM_PAGE_SIZE < PAGE_SIZE.
1596 */
1597 #if MTHCA_ICM_PAGE_SIZE < PAGE_SIZE
1598 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MTHCA_ICM_PAGE_SIZE) >>
1599 (PAGE_SHIFT - MTHCA_ICM_PAGE_SHIFT);
1600 #endif
1601
1602 return 0;
1603 }
1604
mthca_SW2HW_MPT(struct mthca_dev * dev,struct mthca_mailbox * mailbox,int mpt_index)1605 int mthca_SW2HW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1606 int mpt_index)
1607 {
1608 return mthca_cmd(dev, mailbox->dma, mpt_index, 0, CMD_SW2HW_MPT,
1609 CMD_TIME_CLASS_B);
1610 }
1611
mthca_HW2SW_MPT(struct mthca_dev * dev,struct mthca_mailbox * mailbox,int mpt_index)1612 int mthca_HW2SW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1613 int mpt_index)
1614 {
1615 return mthca_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, mpt_index,
1616 !mailbox, CMD_HW2SW_MPT,
1617 CMD_TIME_CLASS_B);
1618 }
1619
mthca_WRITE_MTT(struct mthca_dev * dev,struct mthca_mailbox * mailbox,int num_mtt)1620 int mthca_WRITE_MTT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1621 int num_mtt)
1622 {
1623 return mthca_cmd(dev, mailbox->dma, num_mtt, 0, CMD_WRITE_MTT,
1624 CMD_TIME_CLASS_B);
1625 }
1626
mthca_SYNC_TPT(struct mthca_dev * dev)1627 int mthca_SYNC_TPT(struct mthca_dev *dev)
1628 {
1629 return mthca_cmd(dev, 0, 0, 0, CMD_SYNC_TPT, CMD_TIME_CLASS_B);
1630 }
1631
mthca_MAP_EQ(struct mthca_dev * dev,u64 event_mask,int unmap,int eq_num)1632 int mthca_MAP_EQ(struct mthca_dev *dev, u64 event_mask, int unmap,
1633 int eq_num)
1634 {
1635 mthca_dbg(dev, "%s mask %016llx for eqn %d\n",
1636 unmap ? "Clearing" : "Setting",
1637 (unsigned long long) event_mask, eq_num);
1638 return mthca_cmd(dev, event_mask, (unmap << 31) | eq_num,
1639 0, CMD_MAP_EQ, CMD_TIME_CLASS_B);
1640 }
1641
mthca_SW2HW_EQ(struct mthca_dev * dev,struct mthca_mailbox * mailbox,int eq_num)1642 int mthca_SW2HW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1643 int eq_num)
1644 {
1645 return mthca_cmd(dev, mailbox->dma, eq_num, 0, CMD_SW2HW_EQ,
1646 CMD_TIME_CLASS_A);
1647 }
1648
mthca_HW2SW_EQ(struct mthca_dev * dev,struct mthca_mailbox * mailbox,int eq_num)1649 int mthca_HW2SW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1650 int eq_num)
1651 {
1652 return mthca_cmd_box(dev, 0, mailbox->dma, eq_num, 0,
1653 CMD_HW2SW_EQ,
1654 CMD_TIME_CLASS_A);
1655 }
1656
mthca_SW2HW_CQ(struct mthca_dev * dev,struct mthca_mailbox * mailbox,int cq_num)1657 int mthca_SW2HW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1658 int cq_num)
1659 {
1660 return mthca_cmd(dev, mailbox->dma, cq_num, 0, CMD_SW2HW_CQ,
1661 CMD_TIME_CLASS_A);
1662 }
1663
mthca_HW2SW_CQ(struct mthca_dev * dev,struct mthca_mailbox * mailbox,int cq_num)1664 int mthca_HW2SW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1665 int cq_num)
1666 {
1667 return mthca_cmd_box(dev, 0, mailbox->dma, cq_num, 0,
1668 CMD_HW2SW_CQ,
1669 CMD_TIME_CLASS_A);
1670 }
1671
mthca_RESIZE_CQ(struct mthca_dev * dev,int cq_num,u32 lkey,u8 log_size)1672 int mthca_RESIZE_CQ(struct mthca_dev *dev, int cq_num, u32 lkey, u8 log_size)
1673 {
1674 struct mthca_mailbox *mailbox;
1675 __be32 *inbox;
1676 int err;
1677
1678 #define RESIZE_CQ_IN_SIZE 0x40
1679 #define RESIZE_CQ_LOG_SIZE_OFFSET 0x0c
1680 #define RESIZE_CQ_LKEY_OFFSET 0x1c
1681
1682 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1683 if (IS_ERR(mailbox))
1684 return PTR_ERR(mailbox);
1685 inbox = mailbox->buf;
1686
1687 memset(inbox, 0, RESIZE_CQ_IN_SIZE);
1688 /*
1689 * Leave start address fields zeroed out -- mthca assumes that
1690 * MRs for CQs always start at virtual address 0.
1691 */
1692 MTHCA_PUT(inbox, log_size, RESIZE_CQ_LOG_SIZE_OFFSET);
1693 MTHCA_PUT(inbox, lkey, RESIZE_CQ_LKEY_OFFSET);
1694
1695 err = mthca_cmd(dev, mailbox->dma, cq_num, 1, CMD_RESIZE_CQ,
1696 CMD_TIME_CLASS_B);
1697
1698 mthca_free_mailbox(dev, mailbox);
1699 return err;
1700 }
1701
mthca_SW2HW_SRQ(struct mthca_dev * dev,struct mthca_mailbox * mailbox,int srq_num)1702 int mthca_SW2HW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1703 int srq_num)
1704 {
1705 return mthca_cmd(dev, mailbox->dma, srq_num, 0, CMD_SW2HW_SRQ,
1706 CMD_TIME_CLASS_A);
1707 }
1708
mthca_HW2SW_SRQ(struct mthca_dev * dev,struct mthca_mailbox * mailbox,int srq_num)1709 int mthca_HW2SW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1710 int srq_num)
1711 {
1712 return mthca_cmd_box(dev, 0, mailbox->dma, srq_num, 0,
1713 CMD_HW2SW_SRQ,
1714 CMD_TIME_CLASS_A);
1715 }
1716
mthca_QUERY_SRQ(struct mthca_dev * dev,u32 num,struct mthca_mailbox * mailbox)1717 int mthca_QUERY_SRQ(struct mthca_dev *dev, u32 num,
1718 struct mthca_mailbox *mailbox)
1719 {
1720 return mthca_cmd_box(dev, 0, mailbox->dma, num, 0,
1721 CMD_QUERY_SRQ, CMD_TIME_CLASS_A);
1722 }
1723
mthca_ARM_SRQ(struct mthca_dev * dev,int srq_num,int limit)1724 int mthca_ARM_SRQ(struct mthca_dev *dev, int srq_num, int limit)
1725 {
1726 return mthca_cmd(dev, limit, srq_num, 0, CMD_ARM_SRQ,
1727 CMD_TIME_CLASS_B);
1728 }
1729
mthca_MODIFY_QP(struct mthca_dev * dev,enum ib_qp_state cur,enum ib_qp_state next,u32 num,int is_ee,struct mthca_mailbox * mailbox,u32 optmask)1730 int mthca_MODIFY_QP(struct mthca_dev *dev, enum ib_qp_state cur,
1731 enum ib_qp_state next, u32 num, int is_ee,
1732 struct mthca_mailbox *mailbox, u32 optmask)
1733 {
1734 static const u16 op[IB_QPS_ERR + 1][IB_QPS_ERR + 1] = {
1735 [IB_QPS_RESET] = {
1736 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1737 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1738 [IB_QPS_INIT] = CMD_RST2INIT_QPEE,
1739 },
1740 [IB_QPS_INIT] = {
1741 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1742 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1743 [IB_QPS_INIT] = CMD_INIT2INIT_QPEE,
1744 [IB_QPS_RTR] = CMD_INIT2RTR_QPEE,
1745 },
1746 [IB_QPS_RTR] = {
1747 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1748 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1749 [IB_QPS_RTS] = CMD_RTR2RTS_QPEE,
1750 },
1751 [IB_QPS_RTS] = {
1752 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1753 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1754 [IB_QPS_RTS] = CMD_RTS2RTS_QPEE,
1755 [IB_QPS_SQD] = CMD_RTS2SQD_QPEE,
1756 },
1757 [IB_QPS_SQD] = {
1758 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1759 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1760 [IB_QPS_RTS] = CMD_SQD2RTS_QPEE,
1761 [IB_QPS_SQD] = CMD_SQD2SQD_QPEE,
1762 },
1763 [IB_QPS_SQE] = {
1764 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1765 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1766 [IB_QPS_RTS] = CMD_SQERR2RTS_QPEE,
1767 },
1768 [IB_QPS_ERR] = {
1769 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1770 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1771 }
1772 };
1773
1774 u8 op_mod = 0;
1775 int my_mailbox = 0;
1776 int err;
1777
1778 if (op[cur][next] == CMD_ERR2RST_QPEE) {
1779 op_mod = 3; /* don't write outbox, any->reset */
1780
1781 /* For debugging */
1782 if (!mailbox) {
1783 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1784 if (!IS_ERR(mailbox)) {
1785 my_mailbox = 1;
1786 op_mod = 2; /* write outbox, any->reset */
1787 } else
1788 mailbox = NULL;
1789 }
1790
1791 err = mthca_cmd_box(dev, 0, mailbox ? mailbox->dma : 0,
1792 (!!is_ee << 24) | num, op_mod,
1793 op[cur][next], CMD_TIME_CLASS_C);
1794
1795 if (0 && mailbox) {
1796 int i;
1797 mthca_dbg(dev, "Dumping QP context:\n");
1798 printk(" %08x\n", be32_to_cpup(mailbox->buf));
1799 for (i = 0; i < 0x100 / 4; ++i) {
1800 if (i % 8 == 0)
1801 printk("[%02x] ", i * 4);
1802 printk(" %08x",
1803 be32_to_cpu(((__be32 *) mailbox->buf)[i + 2]));
1804 if ((i + 1) % 8 == 0)
1805 printk("\n");
1806 }
1807 }
1808
1809 if (my_mailbox)
1810 mthca_free_mailbox(dev, mailbox);
1811 } else {
1812 if (0) {
1813 int i;
1814 mthca_dbg(dev, "Dumping QP context:\n");
1815 printk(" opt param mask: %08x\n", be32_to_cpup(mailbox->buf));
1816 for (i = 0; i < 0x100 / 4; ++i) {
1817 if (i % 8 == 0)
1818 printk(" [%02x] ", i * 4);
1819 printk(" %08x",
1820 be32_to_cpu(((__be32 *) mailbox->buf)[i + 2]));
1821 if ((i + 1) % 8 == 0)
1822 printk("\n");
1823 }
1824 }
1825
1826 err = mthca_cmd(dev, mailbox->dma, optmask | (!!is_ee << 24) | num,
1827 op_mod, op[cur][next], CMD_TIME_CLASS_C);
1828 }
1829
1830 return err;
1831 }
1832
mthca_QUERY_QP(struct mthca_dev * dev,u32 num,int is_ee,struct mthca_mailbox * mailbox)1833 int mthca_QUERY_QP(struct mthca_dev *dev, u32 num, int is_ee,
1834 struct mthca_mailbox *mailbox)
1835 {
1836 return mthca_cmd_box(dev, 0, mailbox->dma, (!!is_ee << 24) | num, 0,
1837 CMD_QUERY_QPEE, CMD_TIME_CLASS_A);
1838 }
1839
mthca_CONF_SPECIAL_QP(struct mthca_dev * dev,int type,u32 qpn)1840 int mthca_CONF_SPECIAL_QP(struct mthca_dev *dev, int type, u32 qpn)
1841 {
1842 u8 op_mod;
1843
1844 switch (type) {
1845 case IB_QPT_SMI:
1846 op_mod = 0;
1847 break;
1848 case IB_QPT_GSI:
1849 op_mod = 1;
1850 break;
1851 case IB_QPT_RAW_IPV6:
1852 op_mod = 2;
1853 break;
1854 case IB_QPT_RAW_ETHERTYPE:
1855 op_mod = 3;
1856 break;
1857 default:
1858 return -EINVAL;
1859 }
1860
1861 return mthca_cmd(dev, 0, qpn, op_mod, CMD_CONF_SPECIAL_QP,
1862 CMD_TIME_CLASS_B);
1863 }
1864
mthca_MAD_IFC(struct mthca_dev * dev,int ignore_mkey,int ignore_bkey,int port,const struct ib_wc * in_wc,const struct ib_grh * in_grh,const void * in_mad,void * response_mad)1865 int mthca_MAD_IFC(struct mthca_dev *dev, int ignore_mkey, int ignore_bkey,
1866 int port, const struct ib_wc *in_wc, const struct ib_grh *in_grh,
1867 const void *in_mad, void *response_mad)
1868 {
1869 struct mthca_mailbox *inmailbox, *outmailbox;
1870 void *inbox;
1871 int err;
1872 u32 in_modifier = port;
1873 u8 op_modifier = 0;
1874
1875 #define MAD_IFC_BOX_SIZE 0x400
1876 #define MAD_IFC_MY_QPN_OFFSET 0x100
1877 #define MAD_IFC_RQPN_OFFSET 0x108
1878 #define MAD_IFC_SL_OFFSET 0x10c
1879 #define MAD_IFC_G_PATH_OFFSET 0x10d
1880 #define MAD_IFC_RLID_OFFSET 0x10e
1881 #define MAD_IFC_PKEY_OFFSET 0x112
1882 #define MAD_IFC_GRH_OFFSET 0x140
1883
1884 inmailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1885 if (IS_ERR(inmailbox))
1886 return PTR_ERR(inmailbox);
1887 inbox = inmailbox->buf;
1888
1889 outmailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1890 if (IS_ERR(outmailbox)) {
1891 mthca_free_mailbox(dev, inmailbox);
1892 return PTR_ERR(outmailbox);
1893 }
1894
1895 memcpy(inbox, in_mad, 256);
1896
1897 /*
1898 * Key check traps can't be generated unless we have in_wc to
1899 * tell us where to send the trap.
1900 */
1901 if (ignore_mkey || !in_wc)
1902 op_modifier |= 0x1;
1903 if (ignore_bkey || !in_wc)
1904 op_modifier |= 0x2;
1905
1906 if (in_wc) {
1907 u8 val;
1908
1909 memset(inbox + 256, 0, 256);
1910
1911 MTHCA_PUT(inbox, in_wc->qp->qp_num, MAD_IFC_MY_QPN_OFFSET);
1912 MTHCA_PUT(inbox, in_wc->src_qp, MAD_IFC_RQPN_OFFSET);
1913
1914 val = in_wc->sl << 4;
1915 MTHCA_PUT(inbox, val, MAD_IFC_SL_OFFSET);
1916
1917 val = in_wc->dlid_path_bits |
1918 (in_wc->wc_flags & IB_WC_GRH ? 0x80 : 0);
1919 MTHCA_PUT(inbox, val, MAD_IFC_G_PATH_OFFSET);
1920
1921 MTHCA_PUT(inbox, in_wc->slid, MAD_IFC_RLID_OFFSET);
1922 MTHCA_PUT(inbox, in_wc->pkey_index, MAD_IFC_PKEY_OFFSET);
1923
1924 if (in_grh)
1925 memcpy(inbox + MAD_IFC_GRH_OFFSET, in_grh, 40);
1926
1927 op_modifier |= 0x4;
1928
1929 in_modifier |= in_wc->slid << 16;
1930 }
1931
1932 err = mthca_cmd_box(dev, inmailbox->dma, outmailbox->dma,
1933 in_modifier, op_modifier,
1934 CMD_MAD_IFC, CMD_TIME_CLASS_C);
1935
1936 if (!err)
1937 memcpy(response_mad, outmailbox->buf, 256);
1938
1939 mthca_free_mailbox(dev, inmailbox);
1940 mthca_free_mailbox(dev, outmailbox);
1941 return err;
1942 }
1943
mthca_READ_MGM(struct mthca_dev * dev,int index,struct mthca_mailbox * mailbox)1944 int mthca_READ_MGM(struct mthca_dev *dev, int index,
1945 struct mthca_mailbox *mailbox)
1946 {
1947 return mthca_cmd_box(dev, 0, mailbox->dma, index, 0,
1948 CMD_READ_MGM, CMD_TIME_CLASS_A);
1949 }
1950
mthca_WRITE_MGM(struct mthca_dev * dev,int index,struct mthca_mailbox * mailbox)1951 int mthca_WRITE_MGM(struct mthca_dev *dev, int index,
1952 struct mthca_mailbox *mailbox)
1953 {
1954 return mthca_cmd(dev, mailbox->dma, index, 0, CMD_WRITE_MGM,
1955 CMD_TIME_CLASS_A);
1956 }
1957
mthca_MGID_HASH(struct mthca_dev * dev,struct mthca_mailbox * mailbox,u16 * hash)1958 int mthca_MGID_HASH(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1959 u16 *hash)
1960 {
1961 u64 imm;
1962 int err;
1963
1964 err = mthca_cmd_imm(dev, mailbox->dma, &imm, 0, 0, CMD_MGID_HASH,
1965 CMD_TIME_CLASS_A);
1966
1967 *hash = imm;
1968 return err;
1969 }
1970
mthca_NOP(struct mthca_dev * dev)1971 int mthca_NOP(struct mthca_dev *dev)
1972 {
1973 return mthca_cmd(dev, 0, 0x1f, 0, CMD_NOP, msecs_to_jiffies(100));
1974 }
1975