1 2 /***************************************************************************** 3 * CDDL HEADER START 4 * 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 * 22 * Copyright 2014 QLogic Corporation 23 * The contents of this file are subject to the terms of the 24 * QLogic End User License (the "License"). 25 * You may not use this file except in compliance with the License. 26 * 27 * You can obtain a copy of the License at 28 * http://www.qlogic.com/Resources/Documents/DriverDownloadHelp/ 29 * QLogic_End_User_Software_License.txt 30 * See the License for the specific language governing permissions 31 * and limitations under the License. 32 * 33 *****************************************************************************/ 34 35 #include <sys/atomic.h> 36 37 // portable integer type of the pointer size for current platform (64/32) 38 typedef unsigned long mm_int_ptr_t; 39 40 typedef kmutex_t mm_spin_lock_t; 41 42 /* overrides __FILE_STRIPPED__ usage in mm.h (__BASENAME__ from Makefile) */ 43 #undef __FILE_STRIPPED__ 44 #define __FILE_STRIPPED__ __BASENAME__ 45 46 #define mm_read_barrier_imp() membar_consumer() 47 #define mm_write_barrier_imp() membar_producer() 48 #define mm_barrier_imp() \ 49 do { \ 50 membar_consumer(); \ 51 membar_producer(); \ 52 } while(0) 53 54 #define mm_atomic_set_imp(_p, _v) \ 55 atomic_swap_32((volatile uint32_t *)(_p), (uint32_t)(_v)) 56 57 #define mm_atomic_dec_imp(_p) atomic_dec_32_nv((volatile uint32_t *)(_p)) 58 #define mm_atomic_inc_imp(_p) atomic_inc_32_nv((volatile uint32_t *)(_p)) 59 60 #define mm_atomic_and_imp(_p, _v) \ 61 atomic_and_32((volatile uint32_t *)(_p), (uint32_t)(_v)) 62 #define mm_atomic_long_and_imp(_p, _v) \ 63 atomic_and_ulong((volatile ulong_t *)(_p), (ulong_t)(_v)) 64 65 #define mm_atomic_or_imp(_p, _v) \ 66 atomic_or_32((volatile uint32_t *)(_p), (uint32_t)(_v)) 67 #define mm_atomic_long_or_imp(_p, _v) \ 68 atomic_or_ulong((volatile ulong_t *)(_p), (ulong_t)(_v)) 69 70 #define mm_atomic_read_imp(_p) \ 71 atomic_add_32_nv((volatile uint32_t *)(_p), (int32_t)0) 72 #define mm_atomic_long_read_imp(_p) \ 73 atomic_add_long_nv((volatile ulong_t *)(_p), (long)0) 74 75 #define mm_atomic_cmpxchg_imp(_p, _old_val, _new_val) \ 76 atomic_cas_32((volatile uint32_t *)(_p), (uint32_t)_old_val, (uint32_t)_new_val) 77 78 79 #if defined(__SunOS_MDB) 80 81 /* Solaris debugger (MDB) doesn't have access to ddi_get/put routines */ 82 83 #define MM_WRITE_DOORBELL_IMP(PDEV, BAR, CID, VAL) \ 84 LM_BAR_WR32_ADDRESS((PDEV), ((u8_t *)PFDEV(PDEV)->context_info->array[VF_TO_PF_CID((PDEV),(CID))].cid_resc.mapped_cid_bar_addr + (DPM_TRIGER_TYPE)), (VAL)); 85 86 #else /* __SunOS && !__SunOS_MDB */ 87 88 #define MM_WRITE_DOORBELL_IMP(PDEV, BAR, CID, VAL) \ 89 ddi_put32(PFDEV(PDEV)->context_info->array[VF_TO_PF_CID((PDEV),(CID))].cid_resc.reg_handle, \ 90 (uint32_t *)((caddr_t)PFDEV(PDEV)->context_info->array[VF_TO_PF_CID((PDEV),(CID))].cid_resc.mapped_cid_bar_addr + (DPM_TRIGER_TYPE)), \ 91 (VAL)) 92 93 #endif /* __SunOS_MDB */ 94 95 #define MM_REGISTER_LPME_IMP(_pdev, _func, _b_fw_access, _b_queue_for_fw) \ 96 mm_register_lpme((_pdev), (_func), (_b_fw_access), (_b_queue_for_fw)) 97 98 99 #define MM_DCB_MP_L2_IS_ENABLE(_pdev) (FALSE) 100 101 void MM_ACQUIRE_SPQ_LOCK_IMP(struct _lm_device_t * pDev); 102 void MM_RELEASE_SPQ_LOCK_IMP(struct _lm_device_t * pDev); 103 void MM_ACQUIRE_SPQ_LOCK_DPC_IMP(struct _lm_device_t * pDev); 104 void MM_RELEASE_SPQ_LOCK_DPC_IMP(struct _lm_device_t * pDev); 105 106 void MM_ACQUIRE_CID_LOCK_IMP(struct _lm_device_t * pDev); 107 void MM_RELEASE_CID_LOCK_IMP(struct _lm_device_t * pDev); 108 109 void MM_ACQUIRE_REQUEST_LOCK_IMP(struct _lm_device_t * pDev); 110 void MM_RELEASE_REQUEST_LOCK_IMP(struct _lm_device_t * pDev); 111 112 void MM_ACQUIRE_PHY_LOCK_IMP(struct _lm_device_t * pDev); 113 void MM_RELEASE_PHY_LOCK_IMP(struct _lm_device_t * pDev); 114 void MM_ACQUIRE_PHY_LOCK_DPC_IMP(struct _lm_device_t * pDev); 115 void MM_RELEASE_PHY_LOCK_DPC_IMP(struct _lm_device_t * pDev); 116 117 void MM_ACQUIRE_MCP_LOCK_IMP(struct _lm_device_t * pDev); 118 void MM_RELEASE_MCP_LOCK_IMP(struct _lm_device_t * pDev); 119 120 void MM_ACQUIRE_ISLES_CONTROL_LOCK_IMP(struct _lm_device_t * pDev); 121 void MM_RELEASE_ISLES_CONTROL_LOCK_IMP(struct _lm_device_t * pDev); 122 void MM_ACQUIRE_ISLES_CONTROL_LOCK_DPC_IMP(struct _lm_device_t * pDev); 123 void MM_RELEASE_ISLES_CONTROL_LOCK_DPC_IMP(struct _lm_device_t * pDev); 124 125 void MM_ACQUIRE_IND_REG_LOCK_IMP(struct _lm_device_t * pDev); 126 void MM_RELEASE_IND_REG_LOCK_IMP(struct _lm_device_t * pDev); 127 128 #define MM_ACQUIRE_RAMROD_COMP_LOCK_IMP(pDev) 129 #define MM_RELEASE_RAMROD_COMP_LOCK_IMP(pDev) 130 131 void MM_ACQUIRE_LOADER_LOCK_IMP(); 132 void MM_RELEASE_LOADER_LOCK_IMP(); 133 134 void MM_ACQUIRE_SP_REQ_MGR_LOCK_IMP(struct _lm_device_t * pDev); 135 void MM_RELEASE_SP_REQ_MGR_LOCK_IMP(struct _lm_device_t * pDev); 136 137 void MM_ACQUIRE_SB_LOCK_IMP(struct _lm_device_t * pDev, u8_t sb_idx); 138 void MM_RELEASE_SB_LOCK_IMP(struct _lm_device_t * pDev, u8_t sb_idx); 139 140 void MM_ACQUIRE_ETH_CON_LOCK_IMP(struct _lm_device_t * pDev); 141 void MM_RELEASE_ETH_CON_LOCK_IMP(struct _lm_device_t * pDev); 142 143 #ifdef VF_INVOLVED 144 145 #error "VF_INVOLVED defined with no backend MM implementation" 146 147 #define MM_ACQUIRE_PF_LOCK_IMP(pdev) 148 #define MM_RELEASE_PF_LOCK_IMP(pdev) 149 150 #define MM_ACQUIRE_VFS_STATS_LOCK_IMP(pdev) 151 #define MM_RELEASE_VFS_STATS_LOCK_IMP(pdev) 152 #define MM_ACQUIRE_VFS_STATS_LOCK_DPC_IMP(pdev) 153 #define MM_RELEASE_VFS_STATS_LOCK_DPC_IMP(pdev) 154 155 #endif /* VF_INVOLVED */ 156 157 158 #define mm_er_initiate_recovery_imp(pdev) \ 159 (LM_STATUS_FAILURE) 160 161 #define mm_register_dpc_imp(_pdev, _func) \ 162 (LM_STATUS_FAILURE) 163 164 #define mm_empty_ramrod_received_imp(pdev, empty_data) 165 166 #define mm_dbus_start_if_enabled_imp(pdev) 167 #define mm_dbus_stop_if_started_imp(pdev) 168 169 170 #ifdef BIG_ENDIAN 171 // LE 172 #define mm_le16_to_cpu_imp(val) SWAP_BYTES16(val) 173 #define mm_cpu_to_le16_imp(val) SWAP_BYTES16(val) 174 #define mm_le32_to_cpu_imp(val) SWAP_BYTES32(val) 175 #define mm_cpu_to_le32_imp(val) SWAP_BYTES32(val) 176 // BE 177 #define mm_be32_to_cpu_imp(val) (val) 178 #define mm_cpu_to_be32_imp(val) (val) 179 #define mm_be16_to_cpu_imp(val) (val) 180 #define mm_cpu_to_be16_imp(val) (val) 181 #else /* LITTLE_ENDIAN */ 182 // LE 183 #define mm_le16_to_cpu_imp(val) (val) 184 #define mm_cpu_to_le16_imp(val) (val) 185 #define mm_le32_to_cpu_imp(val) (val) 186 #define mm_cpu_to_le32_imp(val) (val) 187 // BE 188 #define mm_be32_to_cpu_imp(val) SWAP_BYTES32(val) 189 #define mm_cpu_to_be32_imp(val) SWAP_BYTES32(val) 190 #define mm_be16_to_cpu_imp(val) SWAP_BYTES16(val) 191 #define mm_cpu_to_be16_imp(val) SWAP_BYTES16(val) 192 #endif /* ifdef BIG_ENDIAN */ 193 194 195 #define mm_get_bar_offset_imp(pdev, bar_num, bar_addr) \ 196 lm_get_bar_offset_direct(pdev, bar_num, bar_addr) 197 198 #define mm_get_bar_size_imp(pdev, bar_num, val_p) \ 199 lm_get_bar_size_direct(pdev, bar_num, val_p) 200 201 void mm_bar_read_byte(struct _lm_device_t *pdev, 202 u8_t bar, 203 u32_t offset, 204 u8_t *ret); 205 206 void mm_bar_read_word(struct _lm_device_t *pdev, 207 u8_t bar, 208 u32_t offset, 209 u16_t *ret); 210 211 void mm_bar_read_dword(struct _lm_device_t *pdev, 212 u8_t bar, 213 u32_t offset, 214 u32_t *ret); 215 216 void mm_bar_read_ddword(struct _lm_device_t *pdev, 217 u8_t bar, 218 u32_t offset, 219 u64_t *ret); 220 221 void mm_bar_write_byte(struct _lm_device_t *pdev, 222 u8_t bar, 223 u32_t offset, 224 u8_t val); 225 226 void mm_bar_write_word(struct _lm_device_t *pdev, 227 u8_t bar, 228 u32_t offset, 229 u16_t val); 230 231 void mm_bar_write_dword(struct _lm_device_t *pdev, 232 u8_t bar, 233 u32_t offset, 234 u32_t val); 235 236 void mm_bar_write_ddword(struct _lm_device_t *pdev, 237 u8_t bar, 238 u32_t offset, 239 u64_t val); 240 241 void mm_bar_copy_buffer(struct _lm_device_t * pdev, 242 u8_t bar, 243 u32_t offset, 244 u32_t size, 245 u32_t *buf_ptr); 246 247 u32_t mm_get_cap_offset(struct _lm_device_t * pdev, 248 u32_t cap_id); 249 250 u32_t mm_get_wol_flags(struct _lm_device_t * pdev); 251 252 u32_t mm_get_feature_flags(struct _lm_device_t * pdev); 253 254 u32_t mm_get_vmq_cnt(struct _lm_device_t * pdev); 255 256 lm_status_t mm_i2c_update(struct _lm_device_t * pdev); 257 258 u64_t mm_query_system_time(void); 259 260