1
2 /*****************************************************************************
3 * CDDL HEADER START
4 *
5 * The contents of this file are subject to the terms of the
6 * Common Development and Distribution License (the "License").
7 * You may not use this file except in compliance with the License.
8 *
9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10 * or http://www.opensolaris.org/os/licensing.
11 * See the License for the specific language governing permissions
12 * and limitations under the License.
13 *
14 * When distributing Covered Code, include this CDDL HEADER in each
15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16 * If applicable, add the following below this CDDL HEADER, with the
17 * fields enclosed by brackets "[]" replaced with your own identifying
18 * information: Portions Copyright [yyyy] [name of copyright owner]
19 *
20 * CDDL HEADER END
21 *
22 * Copyright 2014 QLogic Corporation
23 * The contents of this file are subject to the terms of the
24 * QLogic End User License (the "License").
25 * You may not use this file except in compliance with the License.
26 *
27 * You can obtain a copy of the License at
28 * http://www.qlogic.com/Resources/Documents/DriverDownloadHelp/
29 * QLogic_End_User_Software_License.txt
30 * See the License for the specific language governing permissions
31 * and limitations under the License.
32 *
33 *****************************************************************************/
34
35 #if defined(USER_LINUX)
36 typedef int mm_spin_lock_t;
37
38 #else
39
40 #include "ediag_compat.h"
41
42 // portable integer type of the pointer size for current platform (64/32)
43 typedef unsigned long mm_int_ptr_t;
44
45 typedef struct semaphore_t * mm_spin_lock_t;
46
47
48 #define mm_read_barrier_imp() \
49 do { \
50 barrier(); \
51 ediag_rmb(); \
52 } while(0)
53
54 #define mm_write_barrier_imp() \
55 do { \
56 barrier(); \
57 ediag_wmb(); \
58 } while(0)
59
60 #define mm_barrier_imp() \
61 do { \
62 barrier(); \
63 ediag_rmb(); \
64 ediag_wmb(); \
65 } while(0)
66
67 #define mm_atomic_set_imp(_p, _v) ediag_atomic_set((s32_t *)_p, (s32_t)_v)
68
69 #define mm_atomic_dec_imp(_p) ediag_atomic_dec_and_test((s32_t *)_p)
70
71 /* returns the decremented value */
72 #define mm_atomic_inc_imp(_p) ediag_atomic_inc_and_test((s32_t *)_p)
73
74 #define mm_atomic_read_imp(_p) ediag_atomic_read((s32_t *)_p)
75
76 #define mm_atomic_long_read_imp(_p) ediag_atomic_long_read((unsigned long *)_p)
77
78 #define mm_atomic_cmpxchg_imp(_p, _cmp, _new_v) ediag_atomic_cmpxchg((s32_t *)_p, (int)_cmp, (int)_new_v)
79
80
81 #define mm_atomic_and_imp(p, v) \
82 do { \
83 *(p) = *(p) & (v); \
84 } while (0)
85
86 #define mm_atomic_long_and_imp(p, v) mm_atomic_and((p), (v))
87
88 #define mm_atomic_or_imp(p, v) \
89 do { \
90 *(p) = *(p) | (v); \
91 } while (0)
92
93 #define mm_atomic_long_or_imp(p, v) mm_atomic_or((p), (v))
94
95
96 #define MM_WRITE_DOORBELL_IMP(PDEV, BAR, CID, VAL) \
97 LM_BAR_WR32_ADDRESS((PDEV), ((u8_t *)PFDEV(PDEV)->context_info->array[VF_TO_PF_CID((PDEV),(CID))].cid_resc.mapped_cid_bar_addr + (DPM_TRIGER_TYPE)), (VAL))
98
99 #define MM_REGISTER_LPME_IMP(_pdev, _func, _b_fw_access, _b_queue_for_fw) \
100 (LM_STATUS_SUCCESS)
101
102 #define MM_DCB_MP_L2_IS_ENABLE(_pdev) (FALSE)
103
104 void MM_ACQUIRE_SPQ_LOCK_IMP(struct _lm_device_t *_pdev);
105 void MM_RELEASE_SPQ_LOCK_IMP(struct _lm_device_t *_pdev);
106 void MM_ACQUIRE_SPQ_LOCK_DPC_IMP(struct _lm_device_t *_pdev);
107 void MM_RELEASE_SPQ_LOCK_DPC_IMP(struct _lm_device_t *_pdev);
108
109 void MM_ACQUIRE_CID_LOCK_IMP(struct _lm_device_t *_pdev);
110 void MM_RELEASE_CID_LOCK_IMP(struct _lm_device_t *_pdev);
111
112 void MM_ACQUIRE_REQUEST_LOCK_IMP(struct _lm_device_t *_pdev);
113 void MM_RELEASE_REQUEST_LOCK_IMP(struct _lm_device_t *_pdev);
114
115 void MM_ACQUIRE_REQUEST_LOCK_DPC_IMP(struct _lm_device_t *_pdev);
116 void MM_RELEASE_REQUEST_LOCK_DPC_IMP(struct _lm_device_t *_pdev);
117
118 void MM_ACQUIRE_PHY_LOCK_IMP(struct _lm_device_t *_pdev);
119 void MM_RELEASE_PHY_LOCK_IMP(struct _lm_device_t *_pdev);
120 void MM_ACQUIRE_PHY_LOCK_DPC_IMP(struct _lm_device_t *_pdev);
121 void MM_RELEASE_PHY_LOCK_DPC_IMP(struct _lm_device_t *_pdev);
122
123
124 void MM_ACQUIRE_ISLES_CONTROL_LOCK_IMP(struct _lm_device_t *_pdev);
125 void MM_RELEASE_ISLES_CONTROL_LOCK_IMP(struct _lm_device_t *_pdev);
126 void MM_ACQUIRE_ISLES_CONTROL_LOCK_DPC_IMP(struct _lm_device_t *_pdev);
127 void MM_RELEASE_ISLES_CONTROL_LOCK_DPC_IMP(struct _lm_device_t *_pdev);
128
129 void MM_ACQUIRE_RAMROD_COMP_LOCK_IMP(struct _lm_device_t *_pdev);
130 void MM_RELEASE_RAMROD_COMP_LOCK_IMP(struct _lm_device_t *_pdev);
131
132
133
134
135 #define MM_ACQUIRE_IND_REG_LOCK_IMP(pdev)
136 #define MM_RELEASE_IND_REG_LOCK_IMP(pdev)
137
138 void MM_ACQUIRE_LOADER_LOCK_IMP(void);
139 void MM_RELEASE_LOADER_LOCK_IMP(void);
140
141 void MM_ACQUIRE_SP_REQ_MGR_LOCK_IMP(struct _lm_device_t *pdev);
142 void MM_RELEASE_SP_REQ_MGR_LOCK_IMP(struct _lm_device_t *pdev);
143
144 void MM_ACQUIRE_MCP_LOCK_IMP(struct _lm_device_t *pdev);
145 void MM_RELEASE_MCP_LOCK_IMP(struct _lm_device_t *pdev);
146
147 void MM_ACQUIRE_SB_LOCK_IMP(struct _lm_device_t *_pdev, u8_t _sb_idx);
148 void MM_RELEASE_SB_LOCK_IMP(struct _lm_device_t *_pdev, u8_t _sb_idx);
149
150 void MM_ACQUIRE_ETH_CON_LOCK_IMP(struct _lm_device_t *pdev);
151 void MM_RELEASE_ETH_CON_LOCK_IMP(struct _lm_device_t *pdev);
152
153 #ifdef VF_INVOLVED
154
155 void MM_ACQUIRE_PF_LOCK_IMP(struct _lm_device_t *pdev);
156 void MM_RELEASE_PF_LOCK_IMP(struct _lm_device_t *pdev);
157
158 void MM_ACQUIRE_VFS_STATS_LOCK_IMP(struct _lm_device_t *_pdev);
159 void MM_RELEASE_VFS_STATS_LOCK_IMP(struct _lm_device_t *_pdev);
160 void MM_ACQUIRE_VFS_STATS_LOCK_DPC_IMP(struct _lm_device_t *_pdev);
161 void MM_RELEASE_VFS_STATS_LOCK_DPC_IMP(struct _lm_device_t *_pdev);
162
163 #endif /* VF_INVOLVED */
164
165
166 #define mm_er_initiate_recovery_imp(pdev) \
167 (LM_STATUS_FAILURE)
168
169 #define mm_register_dpc_imp(_pdev, _func) \
170 (LM_STATUS_FAILURE)
171
172 #define mm_empty_ramrod_received_imp(pdev, empty_data)
173
174 #define mm_dbus_start_if_enabled_imp(_pdev)
175 #define mm_dbus_stop_if_started_imp(_pdev)
176
177
178 lm_status_t mm_get_bar_offset_imp(struct _lm_device_t *pdev,
179 u8_t barn,
180 lm_address_t *bar_addr);
181
182 lm_status_t mm_get_bar_size_imp(struct _lm_device_t *pdev,
183 u8_t bar_num,
184 u32_t *bar_sz);
185
186
187
188 lm_status_t mm_get_bar_size(
189 struct _lm_device_t * pdev,
190 u8_t bar_num,
191 u32_t * bar_sz
192 );
193
194 void mm_bar_read_byte(
195 struct _lm_device_t * _pdev,
196 u8_t bar,
197 u32_t offset,
198 u8_t * ret
199 );
200
201
202 void mm_bar_read_word(
203 struct _lm_device_t * _pdev,
204 u8_t bar,
205 u32_t offset,
206 u16_t * ret
207 );
208
209 void mm_bar_read_dword(
210 struct _lm_device_t * _pdev,
211 u8_t bar,
212 u32_t offset,
213 u32_t * ret
214 );
215
216
217 void mm_bar_read_ddword(
218 struct _lm_device_t * _pdev,
219 u8_t bar,
220 u32_t offset,
221 u64_t * ret
222 );
223
224
225 void mm_bar_write_byte(
226 struct _lm_device_t * _pdev,
227 u8_t bar,
228 u32_t offset,
229 u8_t val
230 );
231
232
233 void mm_bar_write_word(
234 struct _lm_device_t * _pdev,
235 u8_t bar,
236 u32_t offset,
237 u16_t val
238 );
239
240
241 void mm_bar_write_dword(
242 struct _lm_device_t * _pdev,
243 u8_t bar,
244 u32_t offset,
245 u32_t val
246 );
247
248
249 void mm_io_write_dword(
250 struct _lm_device_t * _pdev,
251 void * addr,
252 u32_t val
253 );
254
255
256 void mm_bar_write_ddword(
257 struct _lm_device_t * _pdev,
258 u8_t bar,
259 u32_t offset,
260 u64_t val
261 );
262
263
264 void mm_bar_copy_buffer(
265 struct _lm_device_t * _pdev,
266 u8_t bar,
267 u32_t offset,
268 u32_t size,
269 u32_t *buf_ptr
270 );
271
272
273
mm_le16_to_cpu_imp(u16_t val)274 static inline u16_t mm_le16_to_cpu_imp(u16_t val)
275 {
276 return ediag_le16_to_cpu(val);
277 }
278
mm_le32_to_cpu_imp(u32_t val)279 static inline u32_t mm_le32_to_cpu_imp(u32_t val)
280 {
281 return ediag_le32_to_cpu(val);
282 }
283
mm_be32_to_cpu_imp(u32_t val)284 static inline u32_t mm_be32_to_cpu_imp(u32_t val)
285 {
286 return ediag_be32_to_cpu(val);
287 }
288
mm_be16_to_cpu_imp(u32_t val)289 static inline u32_t mm_be16_to_cpu_imp(u32_t val)
290 {
291 return ediag_be16_to_cpu(val);
292 }
293
mm_cpu_to_be32_imp(u32_t val)294 static inline u32_t mm_cpu_to_be32_imp(u32_t val)
295 {
296 return ediag_cpu_to_be32(val);
297 }
298
mm_cpu_to_be16_imp(u32_t val)299 static inline u32_t mm_cpu_to_be16_imp(u32_t val)
300 {
301 return ediag_cpu_to_be16(val);
302 }
303
mm_cpu_to_le16_imp(u16_t val)304 static inline u16_t mm_cpu_to_le16_imp(u16_t val)
305 {
306 return ediag_cpu_to_le16(val);
307 }
308
mm_cpu_to_le32_imp(u32_t val)309 static inline u32_t mm_cpu_to_le32_imp(u32_t val)
310 {
311 return ediag_cpu_to_le32(val);
312 }
313
314 u32_t mm_get_wol_flags( IN struct _lm_device_t* pdev );
315
316 u32_t mm_get_feature_flags(struct _lm_device_t* pdev);
317
318 u32_t mm_get_vmq_cnt(struct _lm_device_t* pdev);
319
320 lm_status_t mm_i2c_update(struct _lm_device_t *pdev);
321
322 u64_t mm_query_system_time(void);
323
324 /* the following are __LINUX only... */
325
326 u32_t mm_get_cap_offset(struct _lm_device_t *pdev,
327 u32_t cap_id);
328
329 void mm_eth_ramrod_comp_cb(struct _lm_device_t *pdev,
330 struct common_ramrod_eth_rx_cqe *cqe);
331
332 void mm_common_ramrod_comp_cb(struct _lm_device_t *pdev,
333 struct event_ring_msg *msg);
334
335
336 #endif
337