1 /***************************************************************************** 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 * 21 * Copyright 2014 QLogic Corporation 22 * The contents of this file are subject to the terms of the 23 * QLogic End User License (the "License"). 24 * You may not use this file except in compliance with the License. 25 * 26 * You can obtain a copy of the License at 27 * http://www.qlogic.com/Resources/Documents/DriverDownloadHelp/ 28 * QLogic_End_User_Software_License.txt 29 * See the License for the specific language governing permissions 30 * and limitations under the License. 31 * 32 *****************************************************************************/ 33 34 #include "sync.h" 35 36 // portable integer type of the pointer size for current platform (64/32) 37 typedef u32_t mm_int_ptr_t; 38 39 typedef int mm_spin_lock_t; 40 41 #define mm_read_barrier_imp() 42 #define mm_write_barrier_imp() 43 #define mm_barrier_imp() 44 45 static __inline void mm_atomic_set_imp(u32_t *p, u32_t v) 46 { 47 LOCK(); 48 *p = v; 49 UNLOCK(); 50 } 51 52 static __inline u32_t mm_atomic_dec_imp(u32_t *p) 53 { 54 u32_t ret; 55 LOCK(); 56 ret = --(*p); 57 UNLOCK(); 58 return ret; 59 } 60 61 static __inline s32_t mm_atomic_inc_imp(u32_t *p) 62 { 63 s32_t ret; 64 LOCK(); 65 ret = ++(*p); 66 UNLOCK(); 67 return ret; 68 } 69 70 static __inline s32_t mm_atomic_and_imp(u32_t *p, u32_t v) 71 { 72 s32_t ret; 73 LOCK(); 74 ret = *p; 75 *p &= v; 76 UNLOCK(); 77 return ret; 78 } 79 80 static __inline unsigned long mm_atomic_long_and_imp(unsigned long *p, 81 unsigned long v) 82 { 83 unsigned long ret; 84 LOCK(); 85 ret = *p; 86 *p &= v; 87 UNLOCK(); 88 return ret; 89 } 90 91 static __inline s32_t mm_atomic_or_imp(u32_t *p, u32_t v) 92 { 93 s32_t ret; 94 LOCK(); 95 ret = *p; 96 *p |= v; 97 UNLOCK(); 98 return ret; 99 } 100 101 static __inline unsigned long mm_atomic_long_or_imp(unsigned long *p, 102 unsigned long v) 103 { 104 unsigned long ret; 105 LOCK(); 106 ret = *p; 107 *p |= v; 108 UNLOCK(); 109 return ret; 110 } 111 112 #define mm_atomic_read_imp(_p) (*_p) 113 #define mm_atomic_long_read_imp(_p) (*_p) 114 115 static __inline s32_t mm_atomic_cmpxchg_imp(u32_t *p, 116 u32_t old_v, 117 u32_t new_v) 118 { 119 s32_t ret; 120 LOCK(); 121 ret = *p; 122 if (*p == old_v) 123 { 124 *p = new_v; 125 } 126 UNLOCK(); 127 return ret; 128 } 129 130 131 #define MM_WRITE_DOORBELL_IMP(PDEV, BAR, CID, VAL) \ 132 LM_BAR_WR32_ADDRESS((PDEV), ((u8_t *)(PFDEV(PDEV))->context_info->array[VF_TO_PF_CID((PDEV),(CID))].cid_resc.mapped_cid_bar_addr + (DPM_TRIGER_TYPE)), (VAL)) 133 134 #define MM_REGISTER_LPME_IMP(_pdev, _func, _b_fw_access, _b_queue_for_fw) \ 135 (LM_STATUS_SUCCESS) 136 137 138 #define MM_ACQUIRE_SPQ_LOCK_IMP(pdev) LOCK() 139 #define MM_RELEASE_SPQ_LOCK_IMP(pdev) UNLOCK() 140 #define MM_ACQUIRE_SPQ_LOCK_DPC_IMP(pdev) LOCK() 141 #define MM_RELEASE_SPQ_LOCK_DPC_IMP(pdev) UNLOCK() 142 143 #define MM_ACQUIRE_CID_LOCK_IMP(pdev) LOCK() 144 #define MM_RELEASE_CID_LOCK_IMP(pdev) UNLOCK() 145 146 #define MM_ACQUIRE_REQUEST_LOCK_IMP(pdev) LOCK() 147 #define MM_RELEASE_REQUEST_LOCK_IMP(pdev) UNLOCK() 148 149 #define MM_ACQUIRE_PHY_LOCK_IMP(pdev) LOCK() 150 #define MM_RELEASE_PHY_LOCK_IMP(pdev) UNLOCK() 151 #define MM_ACQUIRE_PHY_LOCK_DPC_IMP(pdev) LOCK() 152 #define MM_RELEASE_PHY_LOCK_DPC_IMP(pdev) UNLOCK() 153 154 #define MM_ACQUIRE_MCP_LOCK_IMP(pdev) LOCK() 155 #define MM_RELEASE_MCP_LOCK_IMP(pdev) UNLOCK() 156 157 #define MM_ACQUIRE_ISLES_CONTROL_LOCK_IMP(pdev) LOCK() 158 #define MM_RELEASE_ISLES_CONTROL_LOCK_IMP(pdev) UNLOCK() 159 #define MM_ACQUIRE_ISLES_CONTROL_LOCK_DPC_IMP(pdev) LOCK() 160 #define MM_RELEASE_ISLES_CONTROL_LOCK_DPC_IMP(pdev) UNLOCK() 161 162 #define MM_ACQUIRE_IND_REG_LOCK_IMP(pdev) LOCK() 163 #define MM_RELEASE_IND_REG_LOCK_IMP(pdev) UNLOCK() 164 165 #define MM_ACQUIRE_LOADER_LOCK_IMP() LOCK() 166 #define MM_RELEASE_LOADER_LOCK_IMP() UNLOCK() 167 168 #define MM_ACQUIRE_RAMROD_COMP_LOCK_IMP(_pdev) LOCK() 169 #define MM_RELEASE_RAMROD_COMP_LOCK_IMP(_pdev) UNLOCK() 170 171 #define MM_ACQUIRE_SP_REQ_MGR_LOCK_IMP(pdev) LOCK() 172 #define MM_RELEASE_SP_REQ_MGR_LOCK_IMP(pdev) UNLOCK() 173 174 #define MM_ACQUIRE_SB_LOCK_IMP(pdev, sb_idx) LOCK() 175 #define MM_RELEASE_SB_LOCK_IMP(pdev, sb_idx) UNLOCK() 176 177 #define MM_ACQUIRE_ETH_CON_LOCK_IMP(pdev) LOCK() 178 #define MM_RELEASE_ETH_CON_LOCK_IMP(pdev) UNLOCK() 179 180 #define MM_DCB_MP_L2_IS_ENABLE(_pdev) (FALSE) 181 182 #ifdef VF_INVOLVED 183 184 #define MM_ACQUIRE_PF_LOCK_IMP(pdev) LOCK() 185 #define MM_RELEASE_PF_LOCK_IMP(pdev) UNLOCK() 186 187 #define MM_ACQUIRE_VFS_STATS_LOCK_IMP(pdev) LOCK() 188 #define MM_RELEASE_VFS_STATS_LOCK_IMP(pdev) UNLOCK() 189 #define MM_ACQUIRE_VFS_STATS_LOCK_DPC_IMP(pdev) LOCK() 190 #define MM_RELEASE_VFS_STATS_LOCK_DPC_IMP(pdev) UNLOCK() 191 192 #endif /* VF_INVOLVED */ 193 194 static __inline void mm_init_lock(struct _lm_device_t *_pdev, 195 mm_spin_lock_t *lock) 196 { 197 /* Do nothing */ 198 } 199 200 static __inline lm_status_t mm_acquire_lock(mm_spin_lock_t *spinlock) 201 { 202 return LM_STATUS_SUCCESS; 203 } 204 205 static __inline lm_status_t mm_release_lock(mm_spin_lock_t *spinlock) 206 { 207 return LM_STATUS_SUCCESS; 208 } 209 210 211 212 213 214 #define mm_er_initiate_recovery_imp(pdev) \ 215 (LM_STATUS_FAILURE) 216 217 #define mm_register_dpc_imp(_pdev, _func) \ 218 (LM_STATUS_FAILURE) 219 220 #define mm_empty_ramrod_received_imp(pdev, empty_data) 221 222 #define mm_dbus_start_if_enabled_imp(pdev) 223 #define mm_dbus_stop_if_started_imp(pdev) 224 225 226 #ifdef BIG_ENDIAN 227 // LE 228 #define mm_le16_to_cpu_imp(val) SWAP_BYTES16(val) 229 #define mm_cpu_to_le16_imp(val) SWAP_BYTES16(val) 230 #define mm_le32_to_cpu_imp(val) SWAP_BYTES32(val) 231 #define mm_cpu_to_le32_imp(val) SWAP_BYTES32(val) 232 // BE 233 #define mm_be32_to_cpu_imp(val) (val) 234 #define mm_cpu_to_be32_imp(val) (val) 235 #define mm_be16_to_cpu_imp(val) (val) 236 #define mm_cpu_to_be16_imp(val) (val) 237 #else /* LITTLE_ENDIAN */ 238 // LE 239 #define mm_le16_to_cpu_imp(val) (val) 240 #define mm_cpu_to_le16_imp(val) (val) 241 #define mm_le32_to_cpu_imp(val) (val) 242 #define mm_cpu_to_le32_imp(val) (val) 243 // BE 244 #define mm_be32_to_cpu_imp(val) SWAP_BYTES32(val) 245 #define mm_cpu_to_be32_imp(val) SWAP_BYTES32(val) 246 #define mm_be16_to_cpu_imp(val) SWAP_BYTES16(val) 247 #define mm_cpu_to_be16_imp(val) SWAP_BYTES16(val) 248 #endif /* ifdef BIG_ENDIAN */ 249 250 251 #define mm_get_bar_offset_imp(pdev, bar_num, bar_addr) \ 252 lm_get_bar_offset_direct(pdev, bar_num, bar_addr) 253 254 #define mm_get_bar_size_imp(pdev, bar_num, val_p) \ 255 lm_get_bar_size_direct(pdev, bar_num, val_p) 256 257 u32_t mm_get_wol_flags( IN struct _lm_device_t* pdev ); 258 259 u32_t mm_get_feature_flags(struct _lm_device_t* pdev); 260 261 u32_t mm_get_vmq_cnt(struct _lm_device_t* pdev); 262 263 lm_status_t mm_i2c_update(struct _lm_device_t *pdev); 264 265 u64_t mm_query_system_time(void); 266 267