1 /*-
2 * Copyright (c) 2017, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <dev/mlx5/cmd.h>
34 #include <dev/mlx5/driver.h>
35 #include <dev/mlx5/device.h>
36 #include <dev/mlx5/mlx5_core/mlx5_core.h>
37 #include <dev/mlx5/mlx5_fpga/cmd.h>
38 #include <dev/mlx5/mlx5_fpga/core.h>
39
40 #define MLX5_FPGA_ACCESS_REG_SZ (MLX5_ST_SZ_DW(fpga_access_reg) + \
41 MLX5_FPGA_ACCESS_REG_SIZE_MAX)
42
mlx5_fpga_access_reg(struct mlx5_core_dev * dev,u8 size,u64 addr,void * buf,bool write)43 int mlx5_fpga_access_reg(struct mlx5_core_dev *dev, u8 size, u64 addr,
44 void *buf, bool write)
45 {
46 u32 in[MLX5_FPGA_ACCESS_REG_SZ] = {0};
47 u32 out[MLX5_FPGA_ACCESS_REG_SZ];
48 int err;
49
50 if (size & 3)
51 return -EINVAL;
52 if (addr & 3)
53 return -EINVAL;
54 if (size > MLX5_FPGA_ACCESS_REG_SIZE_MAX)
55 return -EINVAL;
56
57 MLX5_SET(fpga_access_reg, in, size, size);
58 MLX5_SET64(fpga_access_reg, in, address, addr);
59 if (write)
60 memcpy(MLX5_ADDR_OF(fpga_access_reg, in, data), buf, size);
61
62 err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
63 MLX5_REG_FPGA_ACCESS_REG, 0, write);
64 if (err)
65 return err;
66
67 if (!write)
68 memcpy(buf, MLX5_ADDR_OF(fpga_access_reg, out, data), size);
69
70 return 0;
71 }
72
mlx5_fpga_caps(struct mlx5_core_dev * dev)73 int mlx5_fpga_caps(struct mlx5_core_dev *dev)
74 {
75 u32 in[MLX5_ST_SZ_DW(fpga_cap)] = {0};
76
77 return mlx5_core_access_reg(dev, in, sizeof(in), dev->caps.fpga,
78 MLX5_ST_SZ_BYTES(fpga_cap),
79 MLX5_REG_FPGA_CAP, 0, 0);
80 }
81
mlx5_fpga_ctrl_op(struct mlx5_core_dev * dev,u8 op)82 int mlx5_fpga_ctrl_op(struct mlx5_core_dev *dev, u8 op)
83 {
84 u32 in[MLX5_ST_SZ_DW(fpga_ctrl)] = {0};
85 u32 out[MLX5_ST_SZ_DW(fpga_ctrl)];
86
87 MLX5_SET(fpga_ctrl, in, operation, op);
88
89 return mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
90 MLX5_REG_FPGA_CTRL, 0, true);
91 }
92
mlx5_fpga_sbu_caps(struct mlx5_core_dev * dev,void * caps,int size)93 int mlx5_fpga_sbu_caps(struct mlx5_core_dev *dev, void *caps, int size)
94 {
95 unsigned int cap_size = MLX5_CAP_FPGA(dev, sandbox_extended_caps_len);
96 u64 addr = MLX5_CAP64_FPGA(dev, sandbox_extended_caps_addr);
97 unsigned int read;
98 int ret = 0;
99
100 if (cap_size > size) {
101 mlx5_core_warn(dev, "Not enough buffer %u for FPGA SBU caps %u",
102 size, cap_size);
103 return -EINVAL;
104 }
105
106 while (cap_size > 0) {
107 read = min_t(unsigned int, cap_size,
108 MLX5_FPGA_ACCESS_REG_SIZE_MAX);
109
110 ret = mlx5_fpga_access_reg(dev, read, addr, caps, false);
111 if (ret) {
112 mlx5_core_warn(dev, "Error reading FPGA SBU caps %u bytes at address %#jx: %d",
113 read, (uintmax_t)addr, ret);
114 return ret;
115 }
116
117 cap_size -= read;
118 addr += read;
119 caps += read;
120 }
121
122 return ret;
123 }
124
mlx5_fpga_ctrl_write(struct mlx5_core_dev * dev,u8 op,enum mlx5_fpga_image image)125 static int mlx5_fpga_ctrl_write(struct mlx5_core_dev *dev, u8 op,
126 enum mlx5_fpga_image image)
127 {
128 u32 in[MLX5_ST_SZ_DW(fpga_ctrl)] = {0};
129 u32 out[MLX5_ST_SZ_DW(fpga_ctrl)];
130
131 MLX5_SET(fpga_ctrl, in, operation, op);
132 MLX5_SET(fpga_ctrl, in, flash_select_admin, image);
133
134 return mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
135 MLX5_REG_FPGA_CTRL, 0, true);
136 }
137
mlx5_fpga_load(struct mlx5_core_dev * dev,enum mlx5_fpga_image image)138 int mlx5_fpga_load(struct mlx5_core_dev *dev, enum mlx5_fpga_image image)
139 {
140 return mlx5_fpga_ctrl_write(dev, MLX5_FPGA_CTRL_OPERATION_LOAD, image);
141 }
142
mlx5_fpga_image_select(struct mlx5_core_dev * dev,enum mlx5_fpga_image image)143 int mlx5_fpga_image_select(struct mlx5_core_dev *dev,
144 enum mlx5_fpga_image image)
145 {
146 return mlx5_fpga_ctrl_write(dev, MLX5_FPGA_CTRL_OPERATION_FLASH_SELECT, image);
147 }
148
mlx5_fpga_query(struct mlx5_core_dev * dev,struct mlx5_fpga_query * query)149 int mlx5_fpga_query(struct mlx5_core_dev *dev, struct mlx5_fpga_query *query)
150 {
151 u32 in[MLX5_ST_SZ_DW(fpga_ctrl)] = {0};
152 u32 out[MLX5_ST_SZ_DW(fpga_ctrl)];
153 int err;
154
155 err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
156 MLX5_REG_FPGA_CTRL, 0, false);
157 if (err)
158 return err;
159
160 query->image_status = MLX5_GET(fpga_ctrl, out, status);
161 query->admin_image = MLX5_GET(fpga_ctrl, out, flash_select_admin);
162 query->oper_image = MLX5_GET(fpga_ctrl, out, flash_select_oper);
163 return 0;
164 }
165
mlx5_fpga_ctrl_connect(struct mlx5_core_dev * dev,enum mlx5_fpga_connect * connect)166 int mlx5_fpga_ctrl_connect(struct mlx5_core_dev *dev,
167 enum mlx5_fpga_connect *connect)
168 {
169 u32 in[MLX5_ST_SZ_DW(fpga_ctrl)] = {0};
170 u32 out[MLX5_ST_SZ_DW(fpga_ctrl)];
171 int status;
172 int err;
173
174 if (*connect == MLX5_FPGA_CONNECT_QUERY) {
175 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
176 sizeof(out), MLX5_REG_FPGA_CTRL,
177 0, false);
178 if (err)
179 return err;
180 status = MLX5_GET(fpga_ctrl, out, status);
181 *connect = (status == MLX5_FDEV_STATE_DISCONNECTED) ?
182 MLX5_FPGA_CONNECT_DISCONNECT :
183 MLX5_FPGA_CONNECT_CONNECT;
184 } else {
185 MLX5_SET(fpga_ctrl, in, operation, *connect);
186 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
187 sizeof(out), MLX5_REG_FPGA_CTRL,
188 0, true);
189 }
190 return err;
191 }
192
mlx5_fpga_query_mtmp(struct mlx5_core_dev * dev,struct mlx5_fpga_temperature * temp)193 int mlx5_fpga_query_mtmp(struct mlx5_core_dev *dev,
194 struct mlx5_fpga_temperature *temp)
195 {
196 u32 in[MLX5_ST_SZ_DW(mtmp_reg)] = {0};
197 u32 out[MLX5_ST_SZ_DW(mtmp_reg)] = {0};
198 int err;
199
200 MLX5_SET(mtmp_reg, in, sensor_index, temp->index);
201 MLX5_SET(mtmp_reg, in, i,
202 ((temp->index < MLX5_FPGA_INTERNAL_SENSORS_LOW) ||
203 (temp->index > MLX5_FPGA_INTERNAL_SENSORS_HIGH)) ? 1 : 0);
204
205 err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
206 MLX5_REG_MTMP, 0, false);
207 if (err)
208 return err;
209
210 temp->index = MLX5_GET(mtmp_reg, out, sensor_index);
211 temp->temperature = MLX5_GET(mtmp_reg, out, temperature);
212 temp->mte = MLX5_GET(mtmp_reg, out, mte);
213 temp->max_temperature = MLX5_GET(mtmp_reg, out, max_temperature);
214 temp->tee = MLX5_GET(mtmp_reg, out, tee);
215 temp->temperature_threshold_hi = MLX5_GET(mtmp_reg, out,
216 temperature_threshold_hi);
217 temp->temperature_threshold_lo = MLX5_GET(mtmp_reg, out,
218 temperature_threshold_lo);
219 memcpy(temp->sensor_name, MLX5_ADDR_OF(mtmp_reg, out, sensor_name),
220 MLX5_FLD_SZ_BYTES(mtmp_reg, sensor_name));
221
222 return 0;
223 }
224
mlx5_fpga_create_qp(struct mlx5_core_dev * dev,void * fpga_qpc,u32 * fpga_qpn)225 int mlx5_fpga_create_qp(struct mlx5_core_dev *dev, void *fpga_qpc,
226 u32 *fpga_qpn)
227 {
228 u32 in[MLX5_ST_SZ_DW(fpga_create_qp_in)] = {0};
229 u32 out[MLX5_ST_SZ_DW(fpga_create_qp_out)];
230 int ret;
231
232 MLX5_SET(fpga_create_qp_in, in, opcode, MLX5_CMD_OP_FPGA_CREATE_QP);
233 memcpy(MLX5_ADDR_OF(fpga_create_qp_in, in, fpga_qpc), fpga_qpc,
234 MLX5_FLD_SZ_BYTES(fpga_create_qp_in, fpga_qpc));
235
236 ret = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
237 if (ret)
238 return ret;
239
240 memcpy(fpga_qpc, MLX5_ADDR_OF(fpga_create_qp_out, out, fpga_qpc),
241 MLX5_FLD_SZ_BYTES(fpga_create_qp_out, fpga_qpc));
242 *fpga_qpn = MLX5_GET(fpga_create_qp_out, out, fpga_qpn);
243 return ret;
244 }
245
mlx5_fpga_modify_qp(struct mlx5_core_dev * dev,u32 fpga_qpn,enum mlx5_fpga_qpc_field_select fields,void * fpga_qpc)246 int mlx5_fpga_modify_qp(struct mlx5_core_dev *dev, u32 fpga_qpn,
247 enum mlx5_fpga_qpc_field_select fields,
248 void *fpga_qpc)
249 {
250 u32 in[MLX5_ST_SZ_DW(fpga_modify_qp_in)] = {0};
251 u32 out[MLX5_ST_SZ_DW(fpga_modify_qp_out)];
252
253 MLX5_SET(fpga_modify_qp_in, in, opcode, MLX5_CMD_OP_FPGA_MODIFY_QP);
254 MLX5_SET(fpga_modify_qp_in, in, field_select, fields);
255 MLX5_SET(fpga_modify_qp_in, in, fpga_qpn, fpga_qpn);
256 memcpy(MLX5_ADDR_OF(fpga_modify_qp_in, in, fpga_qpc), fpga_qpc,
257 MLX5_FLD_SZ_BYTES(fpga_modify_qp_in, fpga_qpc));
258
259 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
260 }
261
mlx5_fpga_query_qp(struct mlx5_core_dev * dev,u32 fpga_qpn,void * fpga_qpc)262 int mlx5_fpga_query_qp(struct mlx5_core_dev *dev,
263 u32 fpga_qpn, void *fpga_qpc)
264 {
265 u32 in[MLX5_ST_SZ_DW(fpga_query_qp_in)] = {0};
266 u32 out[MLX5_ST_SZ_DW(fpga_query_qp_out)];
267 int ret;
268
269 MLX5_SET(fpga_query_qp_in, in, opcode, MLX5_CMD_OP_FPGA_QUERY_QP);
270 MLX5_SET(fpga_query_qp_in, in, fpga_qpn, fpga_qpn);
271
272 ret = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
273 if (ret)
274 return ret;
275
276 memcpy(fpga_qpc, MLX5_ADDR_OF(fpga_query_qp_out, out, fpga_qpc),
277 MLX5_FLD_SZ_BYTES(fpga_query_qp_out, fpga_qpc));
278 return ret;
279 }
280
mlx5_fpga_destroy_qp(struct mlx5_core_dev * dev,u32 fpga_qpn)281 int mlx5_fpga_destroy_qp(struct mlx5_core_dev *dev, u32 fpga_qpn)
282 {
283 u32 in[MLX5_ST_SZ_DW(fpga_destroy_qp_in)] = {0};
284 u32 out[MLX5_ST_SZ_DW(fpga_destroy_qp_out)];
285
286 MLX5_SET(fpga_destroy_qp_in, in, opcode, MLX5_CMD_OP_FPGA_DESTROY_QP);
287 MLX5_SET(fpga_destroy_qp_in, in, fpga_qpn, fpga_qpn);
288
289 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
290 }
291
mlx5_fpga_query_qp_counters(struct mlx5_core_dev * dev,u32 fpga_qpn,bool clear,struct mlx5_fpga_qp_counters * data)292 int mlx5_fpga_query_qp_counters(struct mlx5_core_dev *dev, u32 fpga_qpn,
293 bool clear, struct mlx5_fpga_qp_counters *data)
294 {
295 u32 in[MLX5_ST_SZ_DW(fpga_query_qp_counters_in)] = {0};
296 u32 out[MLX5_ST_SZ_DW(fpga_query_qp_counters_out)];
297 int ret;
298
299 MLX5_SET(fpga_query_qp_counters_in, in, opcode,
300 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS);
301 MLX5_SET(fpga_query_qp_counters_in, in, clear, clear);
302 MLX5_SET(fpga_query_qp_counters_in, in, fpga_qpn, fpga_qpn);
303
304 ret = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
305 if (ret)
306 return ret;
307
308 data->rx_ack_packets = MLX5_GET64(fpga_query_qp_counters_out, out,
309 rx_ack_packets);
310 data->rx_send_packets = MLX5_GET64(fpga_query_qp_counters_out, out,
311 rx_send_packets);
312 data->tx_ack_packets = MLX5_GET64(fpga_query_qp_counters_out, out,
313 tx_ack_packets);
314 data->tx_send_packets = MLX5_GET64(fpga_query_qp_counters_out, out,
315 tx_send_packets);
316 data->rx_total_drop = MLX5_GET64(fpga_query_qp_counters_out, out,
317 rx_total_drop);
318
319 return ret;
320 }
321
mlx5_fpga_shell_counters(struct mlx5_core_dev * dev,bool clear,struct mlx5_fpga_shell_counters * data)322 int mlx5_fpga_shell_counters(struct mlx5_core_dev *dev, bool clear,
323 struct mlx5_fpga_shell_counters *data)
324 {
325 u32 in[MLX5_ST_SZ_DW(fpga_shell_counters)] = {0};
326 u32 out[MLX5_ST_SZ_DW(fpga_shell_counters)];
327 int err;
328
329 MLX5_SET(fpga_shell_counters, in, clear, clear);
330 err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
331 MLX5_REG_FPGA_SHELL_CNTR, 0, false);
332 if (err)
333 goto out;
334 if (data) {
335 data->ddr_read_requests = MLX5_GET64(fpga_shell_counters, out,
336 ddr_read_requests);
337 data->ddr_write_requests = MLX5_GET64(fpga_shell_counters, out,
338 ddr_write_requests);
339 data->ddr_read_bytes = MLX5_GET64(fpga_shell_counters, out,
340 ddr_read_bytes);
341 data->ddr_write_bytes = MLX5_GET64(fpga_shell_counters, out,
342 ddr_write_bytes);
343 }
344
345 out:
346 return err;
347 }
348