1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 /* Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved. */ 3 4 #ifndef MLX5_IFC_DR_STE_V1_H 5 #define MLX5_IFC_DR_STE_V1_H 6 7 enum mlx5_ifc_ste_v1_modify_hdr_offset { 8 MLX5_MODIFY_HEADER_V1_QW_OFFSET = 0x20, 9 }; 10 11 struct mlx5_ifc_ste_single_action_flow_tag_v1_bits { 12 u8 action_id[0x8]; 13 u8 flow_tag[0x18]; 14 }; 15 16 struct mlx5_ifc_ste_single_action_modify_list_v1_bits { 17 u8 action_id[0x8]; 18 u8 num_of_modify_actions[0x8]; 19 u8 modify_actions_ptr[0x10]; 20 }; 21 22 struct mlx5_ifc_ste_single_action_remove_header_v1_bits { 23 u8 action_id[0x8]; 24 u8 reserved_at_8[0x2]; 25 u8 start_anchor[0x6]; 26 u8 reserved_at_10[0x2]; 27 u8 end_anchor[0x6]; 28 u8 reserved_at_18[0x4]; 29 u8 decap[0x1]; 30 u8 vni_to_cqe[0x1]; 31 u8 qos_profile[0x2]; 32 }; 33 34 struct mlx5_ifc_ste_single_action_remove_header_size_v1_bits { 35 u8 action_id[0x8]; 36 u8 reserved_at_8[0x2]; 37 u8 start_anchor[0x6]; 38 u8 outer_l4_remove[0x1]; 39 u8 reserved_at_11[0x1]; 40 u8 start_offset[0x7]; 41 u8 reserved_at_18[0x1]; 42 u8 remove_size[0x6]; 43 }; 44 45 struct mlx5_ifc_ste_double_action_copy_v1_bits { 46 u8 action_id[0x8]; 47 u8 destination_dw_offset[0x8]; 48 u8 reserved_at_10[0x2]; 49 u8 destination_left_shifter[0x6]; 50 u8 reserved_at_17[0x2]; 51 u8 destination_length[0x6]; 52 53 u8 reserved_at_20[0x8]; 54 u8 source_dw_offset[0x8]; 55 u8 reserved_at_30[0x2]; 56 u8 source_right_shifter[0x6]; 57 u8 reserved_at_38[0x8]; 58 }; 59 60 struct mlx5_ifc_ste_double_action_set_v1_bits { 61 u8 action_id[0x8]; 62 u8 destination_dw_offset[0x8]; 63 u8 reserved_at_10[0x2]; 64 u8 destination_left_shifter[0x6]; 65 u8 reserved_at_18[0x2]; 66 u8 destination_length[0x6]; 67 68 u8 inline_data[0x20]; 69 }; 70 71 struct mlx5_ifc_ste_double_action_add_v1_bits { 72 u8 action_id[0x8]; 73 u8 destination_dw_offset[0x8]; 74 u8 reserved_at_10[0x2]; 75 u8 destination_left_shifter[0x6]; 76 u8 reserved_at_18[0x2]; 77 u8 destination_length[0x6]; 78 79 u8 add_value[0x20]; 80 }; 81 82 struct mlx5_ifc_ste_double_action_insert_with_inline_v1_bits { 83 u8 action_id[0x8]; 84 u8 reserved_at_8[0x2]; 85 u8 start_anchor[0x6]; 86 u8 start_offset[0x7]; 87 u8 reserved_at_17[0x9]; 88 89 u8 inline_data[0x20]; 90 }; 91 92 struct mlx5_ifc_ste_double_action_insert_with_ptr_v1_bits { 93 u8 action_id[0x8]; 94 u8 reserved_at_8[0x2]; 95 u8 start_anchor[0x6]; 96 u8 start_offset[0x7]; 97 u8 size[0x6]; 98 u8 attributes[0x3]; 99 100 u8 pointer[0x20]; 101 }; 102 103 struct mlx5_ifc_ste_double_action_accelerated_modify_action_list_v1_bits { 104 u8 action_id[0x8]; 105 u8 modify_actions_pattern_pointer[0x18]; 106 107 u8 number_of_modify_actions[0x8]; 108 u8 modify_actions_argument_pointer[0x18]; 109 }; 110 111 struct mlx5_ifc_ste_match_bwc_v1_bits { 112 u8 entry_format[0x8]; 113 u8 counter_id[0x18]; 114 115 u8 miss_address_63_48[0x10]; 116 u8 match_definer_ctx_idx[0x8]; 117 u8 miss_address_39_32[0x8]; 118 119 u8 miss_address_31_6[0x1a]; 120 u8 reserved_at_5a[0x1]; 121 u8 match_polarity[0x1]; 122 u8 reparse[0x1]; 123 u8 reserved_at_5d[0x3]; 124 125 u8 next_table_base_63_48[0x10]; 126 u8 hash_definer_ctx_idx[0x8]; 127 u8 next_table_base_39_32_size[0x8]; 128 129 u8 next_table_base_31_5_size[0x1b]; 130 u8 hash_type[0x2]; 131 u8 hash_after_actions[0x1]; 132 u8 reserved_at_9e[0x2]; 133 134 u8 byte_mask[0x10]; 135 u8 next_entry_format[0x1]; 136 u8 mask_mode[0x1]; 137 u8 gvmi[0xe]; 138 139 u8 action[0x40]; 140 }; 141 142 struct mlx5_ifc_ste_mask_and_match_v1_bits { 143 u8 entry_format[0x8]; 144 u8 counter_id[0x18]; 145 146 u8 miss_address_63_48[0x10]; 147 u8 match_definer_ctx_idx[0x8]; 148 u8 miss_address_39_32[0x8]; 149 150 u8 miss_address_31_6[0x1a]; 151 u8 reserved_at_5a[0x1]; 152 u8 match_polarity[0x1]; 153 u8 reparse[0x1]; 154 u8 reserved_at_5d[0x3]; 155 156 u8 next_table_base_63_48[0x10]; 157 u8 hash_definer_ctx_idx[0x8]; 158 u8 next_table_base_39_32_size[0x8]; 159 160 u8 next_table_base_31_5_size[0x1b]; 161 u8 hash_type[0x2]; 162 u8 hash_after_actions[0x1]; 163 u8 reserved_at_9e[0x2]; 164 165 u8 action[0x60]; 166 }; 167 168 struct mlx5_ifc_ste_match_ranges_v1_bits { 169 u8 entry_format[0x8]; 170 u8 counter_id[0x18]; 171 172 u8 miss_address_63_48[0x10]; 173 u8 match_definer_ctx_idx[0x8]; 174 u8 miss_address_39_32[0x8]; 175 176 u8 miss_address_31_6[0x1a]; 177 u8 reserved_at_5a[0x1]; 178 u8 match_polarity[0x1]; 179 u8 reparse[0x1]; 180 u8 reserved_at_5d[0x3]; 181 182 u8 next_table_base_63_48[0x10]; 183 u8 hash_definer_ctx_idx[0x8]; 184 u8 next_table_base_39_32_size[0x8]; 185 186 u8 next_table_base_31_5_size[0x1b]; 187 u8 hash_type[0x2]; 188 u8 hash_after_actions[0x1]; 189 u8 reserved_at_9e[0x2]; 190 191 u8 action[0x60]; 192 193 u8 max_value_0[0x20]; 194 u8 min_value_0[0x20]; 195 u8 max_value_1[0x20]; 196 u8 min_value_1[0x20]; 197 u8 max_value_2[0x20]; 198 u8 min_value_2[0x20]; 199 u8 max_value_3[0x20]; 200 u8 min_value_3[0x20]; 201 }; 202 203 struct mlx5_ifc_ste_eth_l2_src_v1_bits { 204 u8 reserved_at_0[0x1]; 205 u8 sx_sniffer[0x1]; 206 u8 functional_loopback[0x1]; 207 u8 ip_fragmented[0x1]; 208 u8 qp_type[0x2]; 209 u8 encapsulation_type[0x2]; 210 u8 port[0x2]; 211 u8 l3_type[0x2]; 212 u8 l4_type[0x2]; 213 u8 first_vlan_qualifier[0x2]; 214 u8 first_priority[0x3]; 215 u8 first_cfi[0x1]; 216 u8 first_vlan_id[0xc]; 217 218 u8 smac_47_16[0x20]; 219 220 u8 smac_15_0[0x10]; 221 u8 l3_ethertype[0x10]; 222 223 u8 reserved_at_60[0x6]; 224 u8 tcp_syn[0x1]; 225 u8 reserved_at_67[0x3]; 226 u8 force_loopback[0x1]; 227 u8 l2_ok[0x1]; 228 u8 l3_ok[0x1]; 229 u8 l4_ok[0x1]; 230 u8 second_vlan_qualifier[0x2]; 231 232 u8 second_priority[0x3]; 233 u8 second_cfi[0x1]; 234 u8 second_vlan_id[0xc]; 235 }; 236 237 struct mlx5_ifc_ste_eth_l2_dst_v1_bits { 238 u8 reserved_at_0[0x1]; 239 u8 sx_sniffer[0x1]; 240 u8 functional_lb[0x1]; 241 u8 ip_fragmented[0x1]; 242 u8 qp_type[0x2]; 243 u8 encapsulation_type[0x2]; 244 u8 port[0x2]; 245 u8 l3_type[0x2]; 246 u8 l4_type[0x2]; 247 u8 first_vlan_qualifier[0x2]; 248 u8 first_priority[0x3]; 249 u8 first_cfi[0x1]; 250 u8 first_vlan_id[0xc]; 251 252 u8 dmac_47_16[0x20]; 253 254 u8 dmac_15_0[0x10]; 255 u8 l3_ethertype[0x10]; 256 257 u8 reserved_at_60[0x6]; 258 u8 tcp_syn[0x1]; 259 u8 reserved_at_67[0x3]; 260 u8 force_lb[0x1]; 261 u8 l2_ok[0x1]; 262 u8 l3_ok[0x1]; 263 u8 l4_ok[0x1]; 264 u8 second_vlan_qualifier[0x2]; 265 u8 second_priority[0x3]; 266 u8 second_cfi[0x1]; 267 u8 second_vlan_id[0xc]; 268 }; 269 270 struct mlx5_ifc_ste_eth_l2_src_dst_v1_bits { 271 u8 dmac_47_16[0x20]; 272 273 u8 smac_47_16[0x20]; 274 275 u8 dmac_15_0[0x10]; 276 u8 reserved_at_50[0x2]; 277 u8 functional_lb[0x1]; 278 u8 reserved_at_53[0x5]; 279 u8 port[0x2]; 280 u8 l3_type[0x2]; 281 u8 reserved_at_5c[0x2]; 282 u8 first_vlan_qualifier[0x2]; 283 284 u8 first_priority[0x3]; 285 u8 first_cfi[0x1]; 286 u8 first_vlan_id[0xc]; 287 u8 smac_15_0[0x10]; 288 }; 289 290 struct mlx5_ifc_ste_eth_l3_ipv4_5_tuple_v1_bits { 291 u8 source_address[0x20]; 292 293 u8 destination_address[0x20]; 294 295 u8 source_port[0x10]; 296 u8 destination_port[0x10]; 297 298 u8 reserved_at_60[0x4]; 299 u8 l4_ok[0x1]; 300 u8 l3_ok[0x1]; 301 u8 fragmented[0x1]; 302 u8 tcp_ns[0x1]; 303 u8 tcp_cwr[0x1]; 304 u8 tcp_ece[0x1]; 305 u8 tcp_urg[0x1]; 306 u8 tcp_ack[0x1]; 307 u8 tcp_psh[0x1]; 308 u8 tcp_rst[0x1]; 309 u8 tcp_syn[0x1]; 310 u8 tcp_fin[0x1]; 311 u8 dscp[0x6]; 312 u8 ecn[0x2]; 313 u8 protocol[0x8]; 314 }; 315 316 struct mlx5_ifc_ste_eth_l2_tnl_v1_bits { 317 u8 l2_tunneling_network_id[0x20]; 318 319 u8 dmac_47_16[0x20]; 320 321 u8 dmac_15_0[0x10]; 322 u8 l3_ethertype[0x10]; 323 324 u8 reserved_at_60[0x3]; 325 u8 ip_fragmented[0x1]; 326 u8 reserved_at_64[0x2]; 327 u8 encp_type[0x2]; 328 u8 reserved_at_68[0x2]; 329 u8 l3_type[0x2]; 330 u8 l4_type[0x2]; 331 u8 first_vlan_qualifier[0x2]; 332 u8 first_priority[0x3]; 333 u8 first_cfi[0x1]; 334 u8 first_vlan_id[0xc]; 335 }; 336 337 struct mlx5_ifc_ste_eth_l3_ipv4_misc_v1_bits { 338 u8 identification[0x10]; 339 u8 flags[0x3]; 340 u8 fragment_offset[0xd]; 341 342 u8 total_length[0x10]; 343 u8 checksum[0x10]; 344 345 u8 version[0x4]; 346 u8 ihl[0x4]; 347 u8 time_to_live[0x8]; 348 u8 reserved_at_50[0x10]; 349 350 u8 reserved_at_60[0x1c]; 351 u8 voq_internal_prio[0x4]; 352 }; 353 354 struct mlx5_ifc_ste_eth_l4_v1_bits { 355 u8 ipv6_version[0x4]; 356 u8 reserved_at_4[0x4]; 357 u8 dscp[0x6]; 358 u8 ecn[0x2]; 359 u8 ipv6_hop_limit[0x8]; 360 u8 protocol[0x8]; 361 362 u8 src_port[0x10]; 363 u8 dst_port[0x10]; 364 365 u8 first_fragment[0x1]; 366 u8 reserved_at_41[0xb]; 367 u8 flow_label[0x14]; 368 369 u8 tcp_data_offset[0x4]; 370 u8 l4_ok[0x1]; 371 u8 l3_ok[0x1]; 372 u8 fragmented[0x1]; 373 u8 tcp_ns[0x1]; 374 u8 tcp_cwr[0x1]; 375 u8 tcp_ece[0x1]; 376 u8 tcp_urg[0x1]; 377 u8 tcp_ack[0x1]; 378 u8 tcp_psh[0x1]; 379 u8 tcp_rst[0x1]; 380 u8 tcp_syn[0x1]; 381 u8 tcp_fin[0x1]; 382 u8 ipv6_paylen[0x10]; 383 }; 384 385 struct mlx5_ifc_ste_eth_l4_misc_v1_bits { 386 u8 window_size[0x10]; 387 u8 urgent_pointer[0x10]; 388 389 u8 ack_num[0x20]; 390 391 u8 seq_num[0x20]; 392 393 u8 length[0x10]; 394 u8 checksum[0x10]; 395 }; 396 397 struct mlx5_ifc_ste_mpls_v1_bits { 398 u8 reserved_at_0[0x15]; 399 u8 mpls_ok[0x1]; 400 u8 mpls4_s_bit[0x1]; 401 u8 mpls4_qualifier[0x1]; 402 u8 mpls3_s_bit[0x1]; 403 u8 mpls3_qualifier[0x1]; 404 u8 mpls2_s_bit[0x1]; 405 u8 mpls2_qualifier[0x1]; 406 u8 mpls1_s_bit[0x1]; 407 u8 mpls1_qualifier[0x1]; 408 u8 mpls0_s_bit[0x1]; 409 u8 mpls0_qualifier[0x1]; 410 411 u8 mpls0_label[0x14]; 412 u8 mpls0_exp[0x3]; 413 u8 mpls0_s_bos[0x1]; 414 u8 mpls0_ttl[0x8]; 415 416 u8 mpls1_label[0x20]; 417 418 u8 mpls2_label[0x20]; 419 }; 420 421 struct mlx5_ifc_ste_gre_v1_bits { 422 u8 gre_c_present[0x1]; 423 u8 reserved_at_1[0x1]; 424 u8 gre_k_present[0x1]; 425 u8 gre_s_present[0x1]; 426 u8 strict_src_route[0x1]; 427 u8 recur[0x3]; 428 u8 flags[0x5]; 429 u8 version[0x3]; 430 u8 gre_protocol[0x10]; 431 432 u8 reserved_at_20[0x20]; 433 434 u8 gre_key_h[0x18]; 435 u8 gre_key_l[0x8]; 436 437 u8 reserved_at_60[0x20]; 438 }; 439 440 struct mlx5_ifc_ste_src_gvmi_qp_v1_bits { 441 u8 loopback_synd[0x8]; 442 u8 reserved_at_8[0x7]; 443 u8 functional_lb[0x1]; 444 u8 source_gvmi[0x10]; 445 446 u8 force_lb[0x1]; 447 u8 reserved_at_21[0x1]; 448 u8 source_is_requestor[0x1]; 449 u8 reserved_at_23[0x5]; 450 u8 source_qp[0x18]; 451 452 u8 reserved_at_40[0x20]; 453 454 u8 reserved_at_60[0x20]; 455 }; 456 457 struct mlx5_ifc_ste_icmp_v1_bits { 458 u8 icmp_payload_data[0x20]; 459 460 u8 icmp_header_data[0x20]; 461 462 u8 icmp_type[0x8]; 463 u8 icmp_code[0x8]; 464 u8 reserved_at_50[0x10]; 465 466 u8 reserved_at_60[0x20]; 467 }; 468 469 #endif /* MLX5_IFC_DR_STE_V1_H */ 470