xref: /freebsd/sys/contrib/device-tree/src/arm64/amlogic/meson-gxl.dtsi (revision fac71e4e09885bb2afa3d984a0c239a52e1a7418) 
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2016 Endless Computers, Inc.
4 * Author: Carlo Caione <carlo@endlessm.com>
5 */
6
7#include "meson-gx.dtsi"
8#include <dt-bindings/clock/gxbb-clkc.h>
9#include <dt-bindings/clock/gxbb-aoclkc.h>
10#include <dt-bindings/gpio/meson-gxl-gpio.h>
11#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
12
13/ {
14	compatible = "amlogic,meson-gxl";
15
16	soc {
17		usb: usb@d0078080 {
18			compatible = "amlogic,meson-gxl-usb-ctrl";
19			reg = <0x0 0xd0078080 0x0 0x20>;
20			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
21			#address-cells = <2>;
22			#size-cells = <2>;
23			ranges;
24
25			clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>;
26			clock-names = "usb_ctrl", "ddr";
27			resets = <&reset RESET_USB_OTG>;
28
29			dr_mode = "otg";
30
31			phys = <&usb2_phy0>, <&usb2_phy1>;
32			phy-names = "usb2-phy0", "usb2-phy1";
33
34			dwc2: usb@c9100000 {
35				compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
36				reg = <0x0 0xc9100000 0x0 0x40000>;
37				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
38				clocks = <&clkc CLKID_USB1>;
39				clock-names = "otg";
40				phys = <&usb2_phy1>;
41				dr_mode = "peripheral";
42				g-rx-fifo-size = <192>;
43				g-np-tx-fifo-size = <128>;
44				g-tx-fifo-size = <128 128 16 16 16>;
45			};
46
47			dwc3: usb@c9000000 {
48				compatible = "snps,dwc3";
49				reg = <0x0 0xc9000000 0x0 0x100000>;
50				interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
51				dr_mode = "host";
52				maximum-speed = "high-speed";
53				snps,dis_u2_susphy_quirk;
54			};
55		};
56
57		acodec: audio-controller@c8832000 {
58			compatible = "amlogic,t9015";
59			reg = <0x0 0xc8832000 0x0 0x14>;
60			#sound-dai-cells = <0>;
61			sound-name-prefix = "ACODEC";
62			clocks = <&clkc CLKID_ACODEC>;
63			clock-names = "pclk";
64			resets = <&reset RESET_ACODEC>;
65			status = "disabled";
66		};
67
68		crypto: crypto@c883e000 {
69			compatible = "amlogic,gxl-crypto";
70			reg = <0x0 0xc883e000 0x0 0x36>;
71			interrupts = <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>,
72				     <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
73			clocks = <&clkc CLKID_BLKMV>;
74			clock-names = "blkmv";
75			status = "okay";
76		};
77	};
78};
79
80&aiu {
81	compatible = "amlogic,aiu-gxl", "amlogic,aiu";
82	clocks = <&clkc CLKID_AIU_GLUE>,
83		 <&clkc CLKID_I2S_OUT>,
84		 <&clkc CLKID_AOCLK_GATE>,
85		 <&clkc CLKID_CTS_AMCLK>,
86		 <&clkc CLKID_MIXER_IFACE>,
87		 <&clkc CLKID_IEC958>,
88		 <&clkc CLKID_IEC958_GATE>,
89		 <&clkc CLKID_CTS_MCLK_I958>,
90		 <&clkc CLKID_CTS_I958>;
91	clock-names = "pclk",
92		      "i2s_pclk",
93		      "i2s_aoclk",
94		      "i2s_mclk",
95		      "i2s_mixer",
96		      "spdif_pclk",
97		      "spdif_aoclk",
98		      "spdif_mclk",
99		      "spdif_mclk_sel";
100	resets = <&reset RESET_AIU>;
101};
102
103&apb {
104	usb2_phy0: phy@78000 {
105		compatible = "amlogic,meson-gxl-usb2-phy";
106		#phy-cells = <0>;
107		reg = <0x0 0x78000 0x0 0x20>;
108		clocks = <&clkc CLKID_USB>;
109		clock-names = "phy";
110		resets = <&reset RESET_USB_OTG>;
111		reset-names = "phy";
112		status = "okay";
113	};
114
115	usb2_phy1: phy@78020 {
116		compatible = "amlogic,meson-gxl-usb2-phy";
117		#phy-cells = <0>;
118		reg = <0x0 0x78020 0x0 0x20>;
119		clocks = <&clkc CLKID_USB>;
120		clock-names = "phy";
121		resets = <&reset RESET_USB_OTG>;
122		reset-names = "phy";
123		status = "okay";
124	};
125};
126
127&efuse {
128	clocks = <&clkc CLKID_EFUSE>;
129};
130
131&ethmac {
132	clocks = <&clkc CLKID_ETH>,
133		 <&clkc CLKID_FCLK_DIV2>,
134		 <&clkc CLKID_MPLL2>,
135		 <&clkc CLKID_FCLK_DIV2>;
136	clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
137
138	mdio0: mdio {
139		#address-cells = <1>;
140		#size-cells = <0>;
141		compatible = "snps,dwmac-mdio";
142	};
143};
144
145&aobus {
146	pinctrl_aobus: pinctrl@14 {
147		compatible = "amlogic,meson-gxl-aobus-pinctrl";
148		#address-cells = <2>;
149		#size-cells = <2>;
150		ranges;
151
152		gpio_ao: bank@14 {
153			reg = <0x0 0x00014 0x0 0x8>,
154			      <0x0 0x0002c 0x0 0x4>,
155			      <0x0 0x00024 0x0 0x8>;
156			reg-names = "mux", "pull", "gpio";
157			gpio-controller;
158			#gpio-cells = <2>;
159			gpio-ranges = <&pinctrl_aobus 0 0 14>;
160		};
161
162		uart_ao_a_pins: uart_ao_a {
163			mux {
164				groups = "uart_tx_ao_a", "uart_rx_ao_a";
165				function = "uart_ao";
166				bias-disable;
167			};
168		};
169
170		uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
171			mux {
172				groups = "uart_cts_ao_a",
173				       "uart_rts_ao_a";
174				function = "uart_ao";
175				bias-disable;
176			};
177		};
178
179		uart_ao_b_pins: uart_ao_b {
180			mux {
181				groups = "uart_tx_ao_b", "uart_rx_ao_b";
182				function = "uart_ao_b";
183				bias-disable;
184			};
185		};
186
187		uart_ao_b_0_1_pins: uart_ao_b_0_1 {
188			mux {
189				groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1";
190				function = "uart_ao_b";
191				bias-disable;
192			};
193		};
194
195		uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
196			mux {
197				groups = "uart_cts_ao_b",
198				       "uart_rts_ao_b";
199				function = "uart_ao_b";
200				bias-disable;
201			};
202		};
203
204		remote_input_ao_pins: remote_input_ao {
205			mux {
206				groups = "remote_input_ao";
207				function = "remote_input_ao";
208				bias-disable;
209			};
210		};
211
212		i2c_ao_pins: i2c_ao {
213			mux {
214				groups = "i2c_sck_ao",
215				       "i2c_sda_ao";
216				function = "i2c_ao";
217				bias-disable;
218			};
219		};
220
221		pwm_ao_a_3_pins: pwm_ao_a_3 {
222			mux {
223				groups = "pwm_ao_a_3";
224				function = "pwm_ao_a";
225				bias-disable;
226			};
227		};
228
229		pwm_ao_a_8_pins: pwm_ao_a_8 {
230			mux {
231				groups = "pwm_ao_a_8";
232				function = "pwm_ao_a";
233				bias-disable;
234			};
235		};
236
237		pwm_ao_b_pins: pwm_ao_b {
238			mux {
239				groups = "pwm_ao_b";
240				function = "pwm_ao_b";
241				bias-disable;
242			};
243		};
244
245		pwm_ao_b_6_pins: pwm_ao_b_6 {
246			mux {
247				groups = "pwm_ao_b_6";
248				function = "pwm_ao_b";
249				bias-disable;
250			};
251		};
252
253		i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
254			mux {
255				groups = "i2s_out_ch23_ao";
256				function = "i2s_out_ao";
257				bias-disable;
258			};
259		};
260
261		i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
262			mux {
263				groups = "i2s_out_ch45_ao";
264				function = "i2s_out_ao";
265				bias-disable;
266			};
267		};
268
269		spdif_out_ao_6_pins: spdif_out_ao_6 {
270			mux {
271				groups = "spdif_out_ao_6";
272				function = "spdif_out_ao";
273				bias-disable;
274			};
275		};
276
277		spdif_out_ao_9_pins: spdif_out_ao_9 {
278			mux {
279				groups = "spdif_out_ao_9";
280				function = "spdif_out_ao";
281				bias-disable;
282			};
283		};
284
285		ao_cec_pins: ao_cec {
286			mux {
287				groups = "ao_cec";
288				function = "cec_ao";
289				bias-disable;
290			};
291		};
292
293		ee_cec_pins: ee_cec {
294			mux {
295				groups = "ee_cec";
296				function = "cec_ao";
297				bias-disable;
298			};
299		};
300	};
301};
302
303&cec_AO {
304	clocks = <&clkc_AO CLKID_AO_CEC_32K>;
305	clock-names = "core";
306};
307
308&clkc_AO {
309	compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc";
310	clocks = <&xtal>, <&clkc CLKID_CLK81>;
311	clock-names = "xtal", "mpeg-clk";
312};
313
314&gpio_intc {
315	compatible = "amlogic,meson-gxl-gpio-intc",
316		     "amlogic,meson-gpio-intc";
317	status = "okay";
318};
319
320&hdmi_tx {
321	compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
322	resets = <&reset RESET_HDMITX_CAPB3>,
323		 <&reset RESET_HDMI_SYSTEM_RESET>,
324		 <&reset RESET_HDMI_TX>;
325	reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
326	clocks = <&clkc CLKID_HDMI_PCLK>,
327		 <&clkc CLKID_CLK81>,
328		 <&clkc CLKID_GCLK_VENCI_INT0>;
329	clock-names = "isfr", "iahb", "venci";
330};
331
332&sysctrl {
333	clkc: clock-controller {
334		compatible = "amlogic,gxl-clkc";
335		#clock-cells = <1>;
336		clocks = <&xtal>;
337		clock-names = "xtal";
338	};
339};
340
341&hwrng {
342	clocks = <&clkc CLKID_RNG0>;
343	clock-names = "core";
344};
345
346&i2c_A {
347	clocks = <&clkc CLKID_I2C>;
348};
349
350&i2c_AO {
351	clocks = <&clkc CLKID_AO_I2C>;
352};
353
354&i2c_B {
355	clocks = <&clkc CLKID_I2C>;
356};
357
358&i2c_C {
359	clocks = <&clkc CLKID_I2C>;
360};
361
362&periphs {
363	pinctrl_periphs: pinctrl@4b0 {
364		compatible = "amlogic,meson-gxl-periphs-pinctrl";
365		#address-cells = <2>;
366		#size-cells = <2>;
367		ranges;
368
369		gpio: bank@4b0 {
370			reg = <0x0 0x004b0 0x0 0x28>,
371			      <0x0 0x004e8 0x0 0x14>,
372			      <0x0 0x00520 0x0 0x14>,
373			      <0x0 0x00430 0x0 0x40>;
374			reg-names = "mux", "pull", "pull-enable", "gpio";
375			gpio-controller;
376			#gpio-cells = <2>;
377			gpio-ranges = <&pinctrl_periphs 0 0 100>;
378		};
379
380		emmc_pins: emmc {
381			mux-0 {
382				groups = "emmc_nand_d07",
383				       "emmc_cmd";
384				function = "emmc";
385				bias-pull-up;
386			};
387
388			mux-1 {
389				groups = "emmc_clk";
390				function = "emmc";
391				bias-disable;
392			};
393		};
394
395		emmc_ds_pins: emmc-ds {
396			mux {
397				groups = "emmc_ds";
398				function = "emmc";
399				bias-pull-down;
400			};
401		};
402
403		emmc_clk_gate_pins: emmc_clk_gate {
404			mux {
405				groups = "BOOT_8";
406				function = "gpio_periphs";
407				bias-pull-down;
408			};
409		};
410
411		nor_pins: nor {
412			mux {
413				groups = "nor_d",
414				       "nor_q",
415				       "nor_c",
416				       "nor_cs";
417				function = "nor";
418				bias-disable;
419			};
420		};
421
422		spi_pins: spi-pins {
423			mux {
424				groups = "spi_miso",
425					"spi_mosi",
426					"spi_sclk";
427				function = "spi";
428				bias-disable;
429			};
430		};
431
432		spi_idle_high_pins: spi-idle-high-pins {
433			mux {
434				groups = "spi_sclk";
435				bias-pull-up;
436			};
437		};
438
439		spi_idle_low_pins: spi-idle-low-pins {
440			mux {
441				groups = "spi_sclk";
442				bias-pull-down;
443			};
444		};
445
446		spi_ss0_pins: spi-ss0 {
447			mux {
448				groups = "spi_ss0";
449				function = "spi";
450				bias-disable;
451			};
452		};
453
454		sdcard_pins: sdcard {
455			mux-0 {
456				groups = "sdcard_d0",
457				       "sdcard_d1",
458				       "sdcard_d2",
459				       "sdcard_d3",
460				       "sdcard_cmd";
461				function = "sdcard";
462				bias-pull-up;
463			};
464
465			mux-1 {
466				groups = "sdcard_clk";
467				function = "sdcard";
468				bias-disable;
469			};
470		};
471
472		sdcard_clk_gate_pins: sdcard_clk_gate {
473			mux {
474				groups = "CARD_2";
475				function = "gpio_periphs";
476				bias-pull-down;
477			};
478		};
479
480		sdio_pins: sdio {
481			mux-0 {
482				groups = "sdio_d0",
483				       "sdio_d1",
484				       "sdio_d2",
485				       "sdio_d3",
486				       "sdio_cmd";
487				function = "sdio";
488				bias-pull-up;
489			};
490
491			mux-1 {
492				groups = "sdio_clk";
493				function = "sdio";
494				bias-disable;
495			};
496		};
497
498		sdio_clk_gate_pins: sdio_clk_gate {
499			mux {
500				groups = "GPIOX_4";
501				function = "gpio_periphs";
502				bias-pull-down;
503			};
504		};
505
506		sdio_irq_pins: sdio_irq {
507			mux {
508				groups = "sdio_irq";
509				function = "sdio";
510				bias-disable;
511			};
512		};
513
514		uart_a_pins: uart_a {
515			mux {
516				groups = "uart_tx_a",
517				       "uart_rx_a";
518				function = "uart_a";
519				bias-disable;
520			};
521		};
522
523		uart_a_cts_rts_pins: uart_a_cts_rts {
524			mux {
525				groups = "uart_cts_a",
526				       "uart_rts_a";
527				function = "uart_a";
528				bias-disable;
529			};
530		};
531
532		uart_b_pins: uart_b {
533			mux {
534				groups = "uart_tx_b",
535				       "uart_rx_b";
536				function = "uart_b";
537				bias-disable;
538			};
539		};
540
541		uart_b_cts_rts_pins: uart_b_cts_rts {
542			mux {
543				groups = "uart_cts_b",
544				       "uart_rts_b";
545				function = "uart_b";
546				bias-disable;
547			};
548		};
549
550		uart_c_pins: uart_c {
551			mux {
552				groups = "uart_tx_c",
553				       "uart_rx_c";
554				function = "uart_c";
555				bias-disable;
556			};
557		};
558
559		uart_c_cts_rts_pins: uart_c_cts_rts {
560			mux {
561				groups = "uart_cts_c",
562				       "uart_rts_c";
563				function = "uart_c";
564				bias-disable;
565			};
566		};
567
568		i2c_a_pins: i2c_a {
569			mux {
570				groups = "i2c_sck_a",
571				     "i2c_sda_a";
572				function = "i2c_a";
573				bias-disable;
574			};
575		};
576
577		i2c_b_pins: i2c_b {
578			mux {
579				groups = "i2c_sck_b",
580				      "i2c_sda_b";
581				function = "i2c_b";
582				bias-disable;
583			};
584		};
585
586		i2c_c_pins: i2c_c {
587			mux {
588				groups = "i2c_sck_c",
589				      "i2c_sda_c";
590				function = "i2c_c";
591				bias-disable;
592			};
593		};
594
595		i2c_c_dv18_pins: i2c_c_dv18 {
596			mux {
597				groups = "i2c_sck_c_dv19",
598				      "i2c_sda_c_dv18";
599				function = "i2c_c";
600				bias-disable;
601			};
602		};
603
604		eth_pins: eth_c {
605			mux {
606				groups = "eth_mdio",
607				       "eth_mdc",
608				       "eth_clk_rx_clk",
609				       "eth_rx_dv",
610				       "eth_rxd0",
611				       "eth_rxd1",
612				       "eth_rxd2",
613				       "eth_rxd3",
614				       "eth_rgmii_tx_clk",
615				       "eth_tx_en",
616				       "eth_txd0",
617				       "eth_txd1",
618				       "eth_txd2",
619				       "eth_txd3";
620				function = "eth";
621				bias-disable;
622			};
623		};
624
625		eth_link_led_pins: eth_link_led {
626			mux {
627				groups = "eth_link_led";
628				function = "eth_led";
629				bias-disable;
630			};
631		};
632
633		eth_act_led_pins: eth_act_led {
634			mux {
635				groups = "eth_act_led";
636				function = "eth_led";
637			};
638		};
639
640		pwm_a_pins: pwm_a {
641			mux {
642				groups = "pwm_a";
643				function = "pwm_a";
644				bias-disable;
645			};
646		};
647
648		pwm_b_pins: pwm_b {
649			mux {
650				groups = "pwm_b";
651				function = "pwm_b";
652				bias-disable;
653			};
654		};
655
656		pwm_c_pins: pwm_c {
657			mux {
658				groups = "pwm_c";
659				function = "pwm_c";
660				bias-disable;
661			};
662		};
663
664		pwm_d_pins: pwm_d {
665			mux {
666				groups = "pwm_d";
667				function = "pwm_d";
668				bias-disable;
669			};
670		};
671
672		pwm_e_pins: pwm_e {
673			mux {
674				groups = "pwm_e";
675				function = "pwm_e";
676				bias-disable;
677			};
678		};
679
680		pwm_f_clk_pins: pwm_f_clk {
681			mux {
682				groups = "pwm_f_clk";
683				function = "pwm_f";
684				bias-disable;
685			};
686		};
687
688		pwm_f_x_pins: pwm_f_x {
689			mux {
690				groups = "pwm_f_x";
691				function = "pwm_f";
692				bias-disable;
693			};
694		};
695
696		hdmi_hpd_pins: hdmi_hpd {
697			mux {
698				groups = "hdmi_hpd";
699				function = "hdmi_hpd";
700				bias-disable;
701			};
702		};
703
704		hdmi_i2c_pins: hdmi_i2c {
705			mux {
706				groups = "hdmi_sda", "hdmi_scl";
707				function = "hdmi_i2c";
708				bias-disable;
709			};
710		};
711
712		i2s_am_clk_pins: i2s_am_clk {
713			mux {
714				groups = "i2s_am_clk";
715				function = "i2s_out";
716				bias-disable;
717			};
718		};
719
720		i2s_out_ao_clk_pins: i2s_out_ao_clk {
721			mux {
722				groups = "i2s_out_ao_clk";
723				function = "i2s_out";
724				bias-disable;
725			};
726		};
727
728		i2s_out_lr_clk_pins: i2s_out_lr_clk {
729			mux {
730				groups = "i2s_out_lr_clk";
731				function = "i2s_out";
732				bias-disable;
733			};
734		};
735
736		i2s_out_ch01_pins: i2s_out_ch01 {
737			mux {
738				groups = "i2s_out_ch01";
739				function = "i2s_out";
740				bias-disable;
741			};
742		};
743		i2sout_ch23_z_pins: i2sout_ch23_z {
744			mux {
745				groups = "i2sout_ch23_z";
746				function = "i2s_out";
747				bias-disable;
748			};
749		};
750
751		i2sout_ch45_z_pins: i2sout_ch45_z {
752			mux {
753				groups = "i2sout_ch45_z";
754				function = "i2s_out";
755				bias-disable;
756			};
757		};
758
759		i2sout_ch67_z_pins: i2sout_ch67_z {
760			mux {
761				groups = "i2sout_ch67_z";
762				function = "i2s_out";
763				bias-disable;
764			};
765		};
766
767		spdif_out_h_pins: spdif_out_ao_h {
768			mux {
769				groups = "spdif_out_h";
770				function = "spdif_out";
771				bias-disable;
772			};
773		};
774	};
775
776	eth_phy_mux: mdio@558 {
777		reg = <0x0 0x558 0x0 0xc>;
778		compatible = "amlogic,gxl-mdio-mux";
779		#address-cells = <1>;
780		#size-cells = <0>;
781		clocks = <&clkc CLKID_FCLK_DIV4>;
782		clock-names = "ref";
783		mdio-parent-bus = <&mdio0>;
784
785		external_mdio: mdio@0 {
786			reg = <0x0>;
787			#address-cells = <1>;
788			#size-cells = <0>;
789		};
790
791		internal_mdio: mdio@1 {
792			reg = <0x1>;
793			#address-cells = <1>;
794			#size-cells = <0>;
795
796			internal_phy: ethernet-phy@8 {
797				compatible = "ethernet-phy-id0181.4400";
798				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
799				reg = <8>;
800				max-speed = <100>;
801			};
802		};
803	};
804};
805
806&pwrc {
807	resets = <&reset RESET_VIU>,
808		 <&reset RESET_VENC>,
809		 <&reset RESET_VCBUS>,
810		 <&reset RESET_BT656>,
811		 <&reset RESET_DVIN_RESET>,
812		 <&reset RESET_RDMA>,
813		 <&reset RESET_VENCI>,
814		 <&reset RESET_VENCP>,
815		 <&reset RESET_VDAC>,
816		 <&reset RESET_VDI6>,
817		 <&reset RESET_VENCL>,
818		 <&reset RESET_VID_LOCK>;
819	reset-names = "viu", "venc", "vcbus", "bt656",
820		      "dvin", "rdma", "venci", "vencp",
821		      "vdac", "vdi6", "vencl", "vid_lock";
822	clocks = <&clkc CLKID_VPU>,
823	         <&clkc CLKID_VAPB>;
824	clock-names = "vpu", "vapb";
825	/*
826	 * VPU clocking is provided by two identical clock paths
827	 * VPU_0 and VPU_1 muxed to a single clock by a glitch
828	 * free mux to safely change frequency while running.
829	 * Same for VAPB but with a final gate after the glitch free mux.
830	 */
831	assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
832			  <&clkc CLKID_VPU_0>,
833			  <&clkc CLKID_VPU>, /* Glitch free mux */
834			  <&clkc CLKID_VAPB_0_SEL>,
835			  <&clkc CLKID_VAPB_0>,
836			  <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
837	assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
838				 <0>, /* Do Nothing */
839				 <&clkc CLKID_VPU_0>,
840				 <&clkc CLKID_FCLK_DIV4>,
841				 <0>, /* Do Nothing */
842				 <&clkc CLKID_VAPB_0>;
843	assigned-clock-rates = <0>, /* Do Nothing */
844			       <666666666>,
845			       <0>, /* Do Nothing */
846			       <0>, /* Do Nothing */
847			       <250000000>,
848			       <0>; /* Do Nothing */
849};
850
851&saradc {
852	compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
853	clocks = <&xtal>,
854		 <&clkc CLKID_SAR_ADC>,
855		 <&clkc CLKID_SAR_ADC_CLK>,
856		 <&clkc CLKID_SAR_ADC_SEL>;
857	clock-names = "clkin", "core", "adc_clk", "adc_sel";
858};
859
860&sd_emmc_a {
861	clocks = <&clkc CLKID_SD_EMMC_A>,
862		 <&clkc CLKID_SD_EMMC_A_CLK0>,
863		 <&clkc CLKID_FCLK_DIV2>;
864	clock-names = "core", "clkin0", "clkin1";
865	resets = <&reset RESET_SD_EMMC_A>;
866};
867
868&sd_emmc_b {
869	clocks = <&clkc CLKID_SD_EMMC_B>,
870		 <&clkc CLKID_SD_EMMC_B_CLK0>,
871		 <&clkc CLKID_FCLK_DIV2>;
872	clock-names = "core", "clkin0", "clkin1";
873	resets = <&reset RESET_SD_EMMC_B>;
874};
875
876&sd_emmc_c {
877	clocks = <&clkc CLKID_SD_EMMC_C>,
878		 <&clkc CLKID_SD_EMMC_C_CLK0>,
879		 <&clkc CLKID_FCLK_DIV2>;
880	clock-names = "core", "clkin0", "clkin1";
881	resets = <&reset RESET_SD_EMMC_C>;
882};
883
884&simplefb_hdmi {
885	clocks = <&clkc CLKID_HDMI_PCLK>,
886		 <&clkc CLKID_CLK81>,
887		 <&clkc CLKID_GCLK_VENCI_INT0>;
888};
889
890&spicc {
891	clocks = <&clkc CLKID_SPICC>;
892	clock-names = "core";
893	resets = <&reset RESET_PERIPHS_SPICC>;
894	num-cs = <1>;
895};
896
897&spifc {
898	clocks = <&clkc CLKID_SPI>;
899};
900
901&uart_A {
902	clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
903	clock-names = "xtal", "pclk", "baud";
904};
905
906&uart_AO {
907	clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
908	clock-names = "xtal", "pclk", "baud";
909};
910
911&uart_AO_B {
912	clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
913	clock-names = "xtal", "pclk", "baud";
914};
915
916&uart_B {
917	clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
918	clock-names = "xtal", "pclk", "baud";
919};
920
921&uart_C {
922	clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
923	clock-names = "xtal", "pclk", "baud";
924};
925
926&vpu {
927	compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
928	power-domains = <&pwrc PWRC_GXBB_VPU_ID>;
929};
930
931&vdec {
932	compatible = "amlogic,gxl-vdec", "amlogic,gx-vdec";
933	clocks = <&clkc CLKID_DOS_PARSER>,
934		 <&clkc CLKID_DOS>,
935		 <&clkc CLKID_VDEC_1>,
936		 <&clkc CLKID_VDEC_HEVC>;
937	clock-names = "dos_parser", "dos", "vdec_1", "vdec_hevc";
938	resets = <&reset RESET_PARSER>;
939	reset-names = "esparser";
940};
941