1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2019 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/amlogic,a1-pll-clkc.h> 7#include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h> 8#include <dt-bindings/gpio/meson-a1-gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/power/meson-a1-power.h> 12#include <dt-bindings/reset/amlogic,meson-a1-reset.h> 13 14/ { 15 compatible = "amlogic,a1"; 16 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 cpus { 22 #address-cells = <2>; 23 #size-cells = <0>; 24 25 cpu0: cpu@0 { 26 device_type = "cpu"; 27 compatible = "arm,cortex-a35"; 28 reg = <0x0 0x0>; 29 enable-method = "psci"; 30 next-level-cache = <&l2>; 31 #cooling-cells = <2>; 32 }; 33 34 cpu1: cpu@1 { 35 device_type = "cpu"; 36 compatible = "arm,cortex-a35"; 37 reg = <0x0 0x1>; 38 enable-method = "psci"; 39 next-level-cache = <&l2>; 40 #cooling-cells = <2>; 41 }; 42 43 l2: l2-cache0 { 44 compatible = "cache"; 45 cache-level = <2>; 46 cache-unified; 47 }; 48 }; 49 50 efuse: efuse { 51 compatible = "amlogic,meson-gxbb-efuse"; 52 clocks = <&clkc_periphs CLKID_OTP>; 53 #address-cells = <1>; 54 #size-cells = <1>; 55 secure-monitor = <&sm>; 56 power-domains = <&pwrc PWRC_OTP_ID>; 57 }; 58 59 psci { 60 compatible = "arm,psci-1.0"; 61 method = "smc"; 62 }; 63 64 reserved-memory { 65 #address-cells = <2>; 66 #size-cells = <2>; 67 ranges; 68 69 linux,cma { 70 compatible = "shared-dma-pool"; 71 reusable; 72 size = <0x0 0x800000>; 73 alignment = <0x0 0x400000>; 74 linux,cma-default; 75 }; 76 }; 77 78 sm: secure-monitor { 79 compatible = "amlogic,meson-gxbb-sm"; 80 81 pwrc: power-controller { 82 compatible = "amlogic,meson-a1-pwrc"; 83 #power-domain-cells = <1>; 84 }; 85 }; 86 87 soc { 88 compatible = "simple-bus"; 89 #address-cells = <2>; 90 #size-cells = <2>; 91 ranges; 92 93 spifc: spi@fd000400 { 94 compatible = "amlogic,a1-spifc"; 95 reg = <0x0 0xfd000400 0x0 0x290>; 96 clocks = <&clkc_periphs CLKID_SPIFC>; 97 #address-cells = <1>; 98 #size-cells = <0>; 99 power-domains = <&pwrc PWRC_SPIFC_ID>; 100 status = "disabled"; 101 }; 102 103 apb: bus@fe000000 { 104 compatible = "simple-bus"; 105 reg = <0x0 0xfe000000 0x0 0x1000000>; 106 #address-cells = <2>; 107 #size-cells = <2>; 108 ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>; 109 110 reset: reset-controller@0 { 111 compatible = "amlogic,meson-a1-reset"; 112 reg = <0x0 0x0 0x0 0x8c>; 113 #reset-cells = <1>; 114 }; 115 116 periphs_pinctrl: pinctrl@400 { 117 compatible = "amlogic,meson-a1-periphs-pinctrl"; 118 #address-cells = <2>; 119 #size-cells = <2>; 120 ranges; 121 122 gpio: bank@400 { 123 reg = <0x0 0x0400 0x0 0x003c>, 124 <0x0 0x0480 0x0 0x0118>; 125 reg-names = "mux", "gpio"; 126 gpio-controller; 127 #gpio-cells = <2>; 128 gpio-ranges = <&periphs_pinctrl 0 0 62>; 129 }; 130 131 i2c0_f11_pins: i2c0-f11 { 132 mux { 133 groups = "i2c0_sck_f11", 134 "i2c0_sda_f12"; 135 function = "i2c0"; 136 bias-pull-up; 137 drive-strength-microamp = <3000>; 138 }; 139 }; 140 141 i2c0_f9_pins: i2c0-f9 { 142 mux { 143 groups = "i2c0_sck_f9", 144 "i2c0_sda_f10"; 145 function = "i2c0"; 146 bias-pull-up; 147 drive-strength-microamp = <3000>; 148 }; 149 }; 150 151 i2c1_x_pins: i2c1-x { 152 mux { 153 groups = "i2c1_sck_x", 154 "i2c1_sda_x"; 155 function = "i2c1"; 156 bias-pull-up; 157 drive-strength-microamp = <3000>; 158 }; 159 }; 160 161 i2c1_a_pins: i2c1-a { 162 mux { 163 groups = "i2c1_sck_a", 164 "i2c1_sda_a"; 165 function = "i2c1"; 166 bias-pull-up; 167 drive-strength-microamp = <3000>; 168 }; 169 }; 170 171 i2c2_x0_pins: i2c2-x0 { 172 mux { 173 groups = "i2c2_sck_x0", 174 "i2c2_sda_x1"; 175 function = "i2c2"; 176 bias-pull-up; 177 drive-strength-microamp = <3000>; 178 }; 179 }; 180 181 i2c2_x15_pins: i2c2-x15 { 182 mux { 183 groups = "i2c2_sck_x15", 184 "i2c2_sda_x16"; 185 function = "i2c2"; 186 bias-pull-up; 187 drive-strength-microamp = <3000>; 188 }; 189 }; 190 191 i2c2_a4_pins: i2c2-a4 { 192 mux { 193 groups = "i2c2_sck_a4", 194 "i2c2_sda_a5"; 195 function = "i2c2"; 196 bias-pull-up; 197 drive-strength-microamp = <3000>; 198 }; 199 }; 200 201 i2c2_a8_pins: i2c2-a8 { 202 mux { 203 groups = "i2c2_sck_a8", 204 "i2c2_sda_a9"; 205 function = "i2c2"; 206 bias-pull-up; 207 drive-strength-microamp = <3000>; 208 }; 209 }; 210 211 i2c3_x_pins: i2c3-x { 212 mux { 213 groups = "i2c3_sck_x", 214 "i2c3_sda_x"; 215 function = "i2c3"; 216 bias-pull-up; 217 drive-strength-microamp = <3000>; 218 }; 219 }; 220 221 i2c3_f_pins: i2c3-f { 222 mux { 223 groups = "i2c3_sck_f", 224 "i2c3_sda_f"; 225 function = "i2c3"; 226 bias-pull-up; 227 drive-strength-microamp = <3000>; 228 }; 229 }; 230 231 uart_a_pins: uart-a { 232 mux { 233 groups = "uart_a_tx", 234 "uart_a_rx"; 235 function = "uart_a"; 236 bias-pull-up; 237 }; 238 }; 239 240 uart_a_cts_rts_pins: uart-a-cts-rts { 241 mux { 242 groups = "uart_a_cts", 243 "uart_a_rts"; 244 function = "uart_a"; 245 bias-pull-down; 246 }; 247 }; 248 249 pwm_a_pins1: pwm-a-pins1 { 250 mux { 251 groups = "pwm_a_x6"; 252 function = "pwm_a"; 253 }; 254 }; 255 256 pwm_a_pins2: pwm-a-pins2 { 257 mux { 258 groups = "pwm_a_x7"; 259 function = "pwm_a"; 260 }; 261 }; 262 263 pwm_a_pins3: pwm-a-pins3 { 264 mux { 265 groups = "pwm_a_f10"; 266 function = "pwm_a"; 267 }; 268 }; 269 270 pwm_a_pins4: pwm-a-pins4 { 271 mux { 272 groups = "pwm_a_f6"; 273 function = "pwm_a"; 274 }; 275 }; 276 277 pwm_a_pins5: pwm-a-pins5 { 278 mux { 279 groups = "pwm_a_a"; 280 function = "pwm_a"; 281 }; 282 }; 283 284 pwm_b_pins1: pwm-b-pins1 { 285 mux { 286 groups = "pwm_b_x"; 287 function = "pwm_b"; 288 }; 289 }; 290 291 pwm_b_pins2: pwm-b-pins2 { 292 mux { 293 groups = "pwm_b_f"; 294 function = "pwm_b"; 295 }; 296 }; 297 298 pwm_b_pins3: pwm-b-pins3 { 299 mux { 300 groups = "pwm_b_a"; 301 function = "pwm_b"; 302 }; 303 }; 304 305 pwm_c_pins1: pwm-c-pins1 { 306 mux { 307 groups = "pwm_c_x"; 308 function = "pwm_c"; 309 }; 310 }; 311 312 pwm_c_pins2: pwm-c-pins2 { 313 mux { 314 groups = "pwm_c_f3"; 315 function = "pwm_c"; 316 }; 317 }; 318 319 pwm_c_pins3: pwm-c-pins3 { 320 mux { 321 groups = "pwm_c_f8"; 322 function = "pwm_c"; 323 }; 324 }; 325 326 pwm_c_pins4: pwm-c-pins4 { 327 mux { 328 groups = "pwm_c_a"; 329 function = "pwm_c"; 330 }; 331 }; 332 333 pwm_d_pins1: pwm-d-pins1 { 334 mux { 335 groups = "pwm_d_x15"; 336 function = "pwm_d"; 337 }; 338 }; 339 340 pwm_d_pins2: pwm-d-pins2 { 341 mux { 342 groups = "pwm_d_x13"; 343 function = "pwm_d"; 344 }; 345 }; 346 347 pwm_d_pins3: pwm-d-pins3 { 348 mux { 349 groups = "pwm_d_x10"; 350 function = "pwm_d"; 351 }; 352 }; 353 354 pwm_d_pins4: pwm-d-pins4 { 355 mux { 356 groups = "pwm_d_f"; 357 function = "pwm_d"; 358 }; 359 }; 360 361 pwm_e_pins1: pwm-e-pins1 { 362 mux { 363 groups = "pwm_e_p"; 364 function = "pwm_e"; 365 }; 366 }; 367 368 pwm_e_pins2: pwm-e-pins2 { 369 mux { 370 groups = "pwm_e_x16"; 371 function = "pwm_e"; 372 }; 373 }; 374 375 pwm_e_pins3: pwm-e-pins3 { 376 mux { 377 groups = "pwm_e_x14"; 378 function = "pwm_e"; 379 }; 380 }; 381 382 pwm_e_pins4: pwm-e-pins4 { 383 mux { 384 groups = "pwm_e_x2"; 385 function = "pwm_e"; 386 }; 387 }; 388 389 pwm_e_pins5: pwm-e-pins5 { 390 mux { 391 groups = "pwm_e_f"; 392 function = "pwm_e"; 393 }; 394 }; 395 396 pwm_e_pins6: pwm-e-pins6 { 397 mux { 398 groups = "pwm_e_a"; 399 function = "pwm_e"; 400 }; 401 }; 402 403 pwm_f_pins1: pwm-f-pins1 { 404 mux { 405 groups = "pwm_f_b"; 406 function = "pwm_f"; 407 }; 408 }; 409 410 pwm_f_pins2: pwm-f-pins2 { 411 mux { 412 groups = "pwm_f_x"; 413 function = "pwm_f"; 414 }; 415 }; 416 417 pwm_f_pins3: pwm-f-pins3 { 418 mux { 419 groups = "pwm_f_f4"; 420 function = "pwm_f"; 421 }; 422 }; 423 424 pwm_f_pins4: pwm-f-pins4 { 425 mux { 426 groups = "pwm_f_f12"; 427 function = "pwm_f"; 428 }; 429 }; 430 431 sdio_pins: sdio { 432 mux0 { 433 groups = "sdcard_d0_x", 434 "sdcard_d1_x", 435 "sdcard_d2_x", 436 "sdcard_d3_x", 437 "sdcard_cmd_x"; 438 function = "sdcard"; 439 bias-pull-up; 440 }; 441 442 mux1 { 443 groups = "sdcard_clk_x"; 444 function = "sdcard"; 445 bias-disable; 446 }; 447 }; 448 449 sdio_clk_gate_pins: sdio-clk-gate { 450 mux { 451 groups = "sdcard_clk_x"; 452 function = "sdcard"; 453 bias-pull-down; 454 }; 455 }; 456 457 spifc_pins: spifc { 458 mux { 459 groups = "spif_mo", 460 "spif_mi", 461 "spif_clk", 462 "spif_cs", 463 "spif_hold_n", 464 "spif_wp_n"; 465 function = "spif"; 466 }; 467 }; 468 }; 469 470 gpio_intc: interrupt-controller@440 { 471 compatible = "amlogic,meson-a1-gpio-intc", 472 "amlogic,meson-gpio-intc"; 473 reg = <0x0 0x0440 0x0 0x14>; 474 interrupt-controller; 475 #interrupt-cells = <2>; 476 amlogic,channel-interrupts = 477 <49 50 51 52 53 54 55 56>; 478 }; 479 480 clkc_periphs: clock-controller@800 { 481 compatible = "amlogic,a1-peripherals-clkc"; 482 reg = <0 0x800 0 0x104>; 483 #clock-cells = <1>; 484 clocks = <&clkc_pll CLKID_FCLK_DIV2>, 485 <&clkc_pll CLKID_FCLK_DIV3>, 486 <&clkc_pll CLKID_FCLK_DIV5>, 487 <&clkc_pll CLKID_FCLK_DIV7>, 488 <&clkc_pll CLKID_HIFI_PLL>, 489 <&xtal>; 490 clock-names = "fclk_div2", "fclk_div3", 491 "fclk_div5", "fclk_div7", 492 "hifi_pll", "xtal"; 493 }; 494 495 i2c0: i2c@1400 { 496 compatible = "amlogic,meson-axg-i2c"; 497 status = "disabled"; 498 reg = <0x0 0x1400 0x0 0x20>; 499 interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>; 500 #address-cells = <1>; 501 #size-cells = <0>; 502 clocks = <&clkc_periphs CLKID_I2C_M_A>; 503 power-domains = <&pwrc PWRC_I2C_ID>; 504 }; 505 506 uart_AO: serial@1c00 { 507 compatible = "amlogic,meson-a1-uart", 508 "amlogic,meson-ao-uart"; 509 reg = <0x0 0x1c00 0x0 0x18>; 510 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; 511 clocks = <&xtal>, <&xtal>, <&xtal>; 512 clock-names = "xtal", "pclk", "baud"; 513 status = "disabled"; 514 }; 515 516 uart_AO_B: serial@2000 { 517 compatible = "amlogic,meson-a1-uart", 518 "amlogic,meson-ao-uart"; 519 reg = <0x0 0x2000 0x0 0x18>; 520 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 521 clocks = <&xtal>, <&xtal>, <&xtal>; 522 clock-names = "xtal", "pclk", "baud"; 523 status = "disabled"; 524 }; 525 526 pwm_ab: pwm@2400 { 527 compatible = "amlogic,meson-a1-pwm", 528 "amlogic,meson-s4-pwm"; 529 reg = <0x0 0x2400 0x0 0x24>; 530 #pwm-cells = <3>; 531 clocks = <&clkc_periphs CLKID_PWM_A>, 532 <&clkc_periphs CLKID_PWM_B>; 533 power-domains = <&pwrc PWRC_I2C_ID>; 534 status = "disabled"; 535 }; 536 537 pwm_cd: pwm@2800 { 538 compatible = "amlogic,meson-a1-pwm", 539 "amlogic,meson-s4-pwm"; 540 reg = <0x0 0x2800 0x0 0x24>; 541 #pwm-cells = <3>; 542 clocks = <&clkc_periphs CLKID_PWM_C>, 543 <&clkc_periphs CLKID_PWM_D>; 544 power-domains = <&pwrc PWRC_I2C_ID>; 545 status = "disabled"; 546 }; 547 548 saradc: adc@2c00 { 549 compatible = "amlogic,meson-g12a-saradc", 550 "amlogic,meson-saradc"; 551 reg = <0x0 0x2c00 0x0 0x48>; 552 #io-channel-cells = <1>; 553 power-domains = <&pwrc PWRC_I2C_ID>; 554 interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>; 555 clocks = <&xtal>, 556 <&clkc_periphs CLKID_SARADC_EN>, 557 <&clkc_periphs CLKID_SARADC>, 558 <&clkc_periphs CLKID_SARADC_SEL>; 559 clock-names = "clkin", "core", 560 "adc_clk", "adc_sel"; 561 status = "disabled"; 562 }; 563 564 i2c1: i2c@5c00 { 565 compatible = "amlogic,meson-axg-i2c"; 566 status = "disabled"; 567 reg = <0x0 0x5c00 0x0 0x20>; 568 interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>; 569 #address-cells = <1>; 570 #size-cells = <0>; 571 clocks = <&clkc_periphs CLKID_I2C_M_B>; 572 power-domains = <&pwrc PWRC_I2C_ID>; 573 }; 574 575 i2c2: i2c@6800 { 576 compatible = "amlogic,meson-axg-i2c"; 577 status = "disabled"; 578 reg = <0x0 0x6800 0x0 0x20>; 579 interrupts = <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>; 580 #address-cells = <1>; 581 #size-cells = <0>; 582 clocks = <&clkc_periphs CLKID_I2C_M_C>; 583 power-domains = <&pwrc PWRC_I2C_ID>; 584 }; 585 586 i2c3: i2c@6c00 { 587 compatible = "amlogic,meson-axg-i2c"; 588 status = "disabled"; 589 reg = <0x0 0x6c00 0x0 0x20>; 590 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>; 591 #address-cells = <1>; 592 #size-cells = <0>; 593 clocks = <&clkc_periphs CLKID_I2C_M_D>; 594 power-domains = <&pwrc PWRC_I2C_ID>; 595 }; 596 597 usb2_phy1: phy@4000 { 598 compatible = "amlogic,a1-usb2-phy"; 599 clocks = <&clkc_periphs CLKID_USB_PHY_IN>; 600 clock-names = "xtal"; 601 reg = <0x0 0x4000 0x0 0x60>; 602 resets = <&reset RESET_USBPHY>; 603 reset-names = "phy"; 604 #phy-cells = <0>; 605 power-domains = <&pwrc PWRC_USB_ID>; 606 }; 607 608 cpu_temp: temperature-sensor@4c00 { 609 compatible = "amlogic,a1-cpu-thermal"; 610 reg = <0x0 0x4c00 0x0 0x50>; 611 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 612 clocks = <&clkc_periphs CLKID_TS>; 613 assigned-clocks = <&clkc_periphs CLKID_TS>; 614 assigned-clock-rates = <500000>; 615 #thermal-sensor-cells = <0>; 616 amlogic,ao-secure = <&sec_AO>; 617 power-domains = <&pwrc PWRC_I2C_ID>; 618 }; 619 620 hwrng: rng@5118 { 621 compatible = "amlogic,meson-rng"; 622 reg = <0x0 0x5118 0x0 0x4>; 623 power-domains = <&pwrc PWRC_OTP_ID>; 624 }; 625 626 sec_AO: ao-secure@5a20 { 627 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 628 reg = <0x0 0x5a20 0x0 0x140>; 629 amlogic,has-chip-id; 630 }; 631 632 pwm_ef: pwm@5400 { 633 compatible = "amlogic,meson-a1-pwm", 634 "amlogic,meson-s4-pwm"; 635 reg = <0x0 0x5400 0x0 0x24>; 636 #pwm-cells = <3>; 637 clocks = <&clkc_periphs CLKID_PWM_E>, 638 <&clkc_periphs CLKID_PWM_F>; 639 power-domains = <&pwrc PWRC_I2C_ID>; 640 status = "disabled"; 641 }; 642 643 clkc_pll: pll-clock-controller@7c80 { 644 compatible = "amlogic,a1-pll-clkc"; 645 reg = <0 0x7c80 0 0x18c>; 646 #clock-cells = <1>; 647 clocks = <&clkc_periphs CLKID_FIXPLL_IN>, 648 <&clkc_periphs CLKID_HIFIPLL_IN>; 649 clock-names = "fixpll_in", "hifipll_in"; 650 }; 651 652 sd_emmc: mmc@10000 { 653 compatible = "amlogic,meson-axg-mmc"; 654 reg = <0x0 0x10000 0x0 0x800>; 655 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 656 clocks = <&clkc_periphs CLKID_SD_EMMC_A>, 657 <&clkc_periphs CLKID_SD_EMMC>, 658 <&clkc_pll CLKID_FCLK_DIV2>; 659 clock-names = "core", 660 "clkin0", 661 "clkin1"; 662 assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_SEL2>; 663 assigned-clock-parents = <&xtal>; 664 resets = <&reset RESET_SD_EMMC_A>; 665 power-domains = <&pwrc PWRC_SD_EMMC_ID>; 666 status = "disabled"; 667 }; 668 }; 669 670 usb: usb@fe004400 { 671 status = "disabled"; 672 compatible = "amlogic,meson-a1-usb-ctrl"; 673 reg = <0x0 0xfe004400 0x0 0xa0>; 674 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 675 #address-cells = <2>; 676 #size-cells = <2>; 677 ranges; 678 679 clocks = <&clkc_periphs CLKID_USB_CTRL>, 680 <&clkc_periphs CLKID_USB_BUS>, 681 <&clkc_periphs CLKID_USB_CTRL_IN>; 682 clock-names = "usb_ctrl", "usb_bus", "xtal_usb_ctrl"; 683 assigned-clocks = <&clkc_periphs CLKID_USB_BUS>; 684 assigned-clock-rates = <64000000>; 685 resets = <&reset RESET_USBCTRL>; 686 687 dr_mode = "otg"; 688 689 phys = <&usb2_phy1>; 690 phy-names = "usb2-phy1"; 691 692 dwc3: usb@ff400000 { 693 compatible = "snps,dwc3"; 694 reg = <0x0 0xff400000 0x0 0x100000>; 695 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 696 dr_mode = "host"; 697 snps,dis_u2_susphy_quirk; 698 snps,quirk-frame-length-adjustment = <0x20>; 699 snps,parkmode-disable-ss-quirk; 700 }; 701 702 dwc2: usb@ff500000 { 703 compatible = "amlogic,meson-a1-usb", "snps,dwc2"; 704 reg = <0x0 0xff500000 0x0 0x40000>; 705 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 706 phys = <&usb2_phy1>; 707 phy-names = "usb2-phy"; 708 clocks = <&clkc_periphs CLKID_USB_PHY>; 709 clock-names = "otg"; 710 dr_mode = "peripheral"; 711 g-rx-fifo-size = <192>; 712 g-np-tx-fifo-size = <128>; 713 g-tx-fifo-size = <128 128 16 16 16>; 714 }; 715 }; 716 717 gic: interrupt-controller@ff901000 { 718 compatible = "arm,gic-400"; 719 reg = <0x0 0xff901000 0x0 0x1000>, 720 <0x0 0xff902000 0x0 0x2000>, 721 <0x0 0xff904000 0x0 0x2000>, 722 <0x0 0xff906000 0x0 0x2000>; 723 interrupt-controller; 724 interrupts = <GIC_PPI 9 725 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 726 #interrupt-cells = <3>; 727 #address-cells = <0>; 728 }; 729 }; 730 731 timer { 732 compatible = "arm,armv8-timer"; 733 interrupts = <GIC_PPI 13 734 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 735 <GIC_PPI 14 736 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 737 <GIC_PPI 11 738 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 739 <GIC_PPI 10 740 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 741 }; 742 743 xtal: xtal-clk { 744 compatible = "fixed-clock"; 745 clock-frequency = <24000000>; 746 clock-output-names = "xtal"; 747 #clock-cells = <0>; 748 }; 749}; 750