xref: /illumos-gate/usr/src/uts/intel/sys/mca_amd.h (revision 2d6eb4a5e0a47d30189497241345dc5466bb68ab)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #ifndef _SYS_MCA_AMD_H
28 #define	_SYS_MCA_AMD_H
29 
30 #include <sys/mca_x86.h>
31 
32 /*
33  * Constants for the Machine Check Architecture as implemented on AMD CPUs.
34  */
35 
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39 
40 #define	AMD_MSR_MCG_CAP			0x179
41 #define	AMD_MSR_MCG_STATUS		0x17a
42 #define	AMD_MSR_MCG_CTL			0x17b
43 
44 #define	AMD_MCA_BANK_DC			0	/* Data Cache */
45 #define	AMD_MCA_BANK_IC			1	/* Instruction Cache */
46 #define	AMD_MCA_BANK_BU			2	/* Bus Unit */
47 #define	AMD_MCA_BANK_LS			3	/* Load/Store Unit */
48 #define	AMD_MCA_BANK_NB			4	/* Northbridge */
49 #define	AMD_MCA_BANK_COUNT		5
50 
51 #define	AMD_MSR_DC_CTL			0x400
52 #define	AMD_MSR_DC_MASK			0xc0010044
53 #define	AMD_MSR_DC_STATUS		0x401
54 #define	AMD_MSR_DC_ADDR			0x402
55 #define	AMD_MSR_DC_MISC			0x403
56 
57 #define	AMD_MSR_IC_CTL			0x404
58 #define	AMD_MSR_IC_MASK			0xc0010045
59 #define	AMD_MSR_IC_STATUS		0x405
60 #define	AMD_MSR_IC_ADDR			0x406
61 #define	AMD_MSR_IC_MISC			0x407
62 
63 #define	AMD_MSR_BU_CTL			0x408
64 #define	AMD_MSR_BU_MASK			0xc0010046
65 #define	AMD_MSR_BU_STATUS		0x409
66 #define	AMD_MSR_BU_ADDR			0x40a
67 #define	AMD_MSR_BU_MISC			0x40b
68 
69 #define	AMD_MSR_LS_CTL			0x40c
70 #define	AMD_MSR_LS_MASK			0xc0010047
71 #define	AMD_MSR_LS_STATUS		0x40d
72 #define	AMD_MSR_LS_ADDR			0x40e
73 #define	AMD_MSR_LS_MISC			0x40f
74 
75 #define	AMD_MSR_NB_CTL			0x410
76 #define	AMD_MSR_NB_MASK			0xc0010048
77 #define	AMD_MSR_NB_STATUS		0x411
78 #define	AMD_MSR_NB_ADDR			0x412
79 #define	AMD_MSR_NB_MISC			0x413
80 
81 #define	AMD_MCG_EN_DC			0x01
82 #define	AMD_MCG_EN_IC			0x02
83 #define	AMD_MCG_EN_BU			0x04
84 #define	AMD_MCG_EN_LS			0x08
85 #define	AMD_MCG_EN_NB			0x10
86 
87 /*
88  * Data Cache (DC) bank error-detection enabling bits and CTL register
89  * initializer value.
90  */
91 
92 #define	AMD_DC_EN_ECCI			0x00000001ULL
93 #define	AMD_DC_EN_ECCM			0x00000002ULL
94 #define	AMD_DC_EN_DECC			0x00000004ULL
95 #define	AMD_DC_EN_DMTP			0x00000008ULL
96 #define	AMD_DC_EN_DSTP			0x00000010ULL
97 #define	AMD_DC_EN_L1TP			0x00000020ULL
98 #define	AMD_DC_EN_L2TP			0x00000040ULL
99 
100 #define	AMD_DC_CTL_INIT_CMN \
101 	(AMD_DC_EN_ECCI | AMD_DC_EN_ECCM | AMD_DC_EN_DECC | AMD_DC_EN_DMTP | \
102 	AMD_DC_EN_DSTP | AMD_DC_EN_L1TP | AMD_DC_EN_L2TP)
103 
104 /*
105  * Instruction Cache (IC) bank error-detection enabling bits and CTL register
106  * initializer value.
107  *
108  * The Northbridge will handle Read Data errors.  Our initializer will enable
109  * all but the RDDE detector.
110  */
111 
112 #define	AMD_IC_EN_ECCI			0x00000001ULL
113 #define	AMD_IC_EN_ECCM			0x00000002ULL
114 #define	AMD_IC_EN_IDP			0x00000004ULL
115 #define	AMD_IC_EN_IMTP			0x00000008ULL
116 #define	AMD_IC_EN_ISTP			0x00000010ULL
117 #define	AMD_IC_EN_L1TP			0x00000020ULL
118 #define	AMD_IC_EN_L2TP			0x00000040ULL
119 #define	AMD_IC_EN_RDDE			0x00000200ULL
120 
121 #define	AMD_IC_CTL_INIT_CMN \
122 	(AMD_IC_EN_ECCI | AMD_IC_EN_ECCM | AMD_IC_EN_IDP | AMD_IC_EN_IMTP | \
123 	AMD_IC_EN_ISTP | AMD_IC_EN_L1TP | AMD_IC_EN_L2TP)
124 
125 /*
126  * Bus Unit (BU) bank error-detection enabling bits and CTL register
127  * initializer value.
128  *
129  * The Northbridge will handle Read Data errors.  Our initializer will enable
130  * all but the S_RDE_* detectors.
131  */
132 
133 #define	AMD_BU_EN_S_RDE_HP		0x00000001ULL
134 #define	AMD_BU_EN_S_RDE_TLB		0x00000002ULL
135 #define	AMD_BU_EN_S_RDE_ALL		0x00000004ULL
136 #define	AMD_BU_EN_S_ECC1_TLB		0x00000008ULL
137 #define	AMD_BU_EN_S_ECC1_HP		0x00000010ULL
138 #define	AMD_BU_EN_S_ECCM_TLB		0x00000020ULL
139 #define	AMD_BU_EN_S_ECCM_HP		0x00000040ULL
140 #define	AMD_BU_EN_L2T_PAR_ICDC		0x00000080ULL
141 #define	AMD_BU_EN_L2T_PAR_TLB		0x00000100ULL
142 #define	AMD_BU_EN_L2T_PAR_SNP		0x00000200ULL
143 #define	AMD_BU_EN_L2T_PAR_CPB		0x00000400ULL
144 #define	AMD_BU_EN_L2T_PAR_SCR		0x00000800ULL
145 #define	AMD_BU_EN_L2D_ECC1_TLB		0x00001000ULL
146 #define	AMD_BU_EN_L2D_ECC1_SNP		0x00002000ULL
147 #define	AMD_BU_EN_L2D_ECC1_CPB		0x00004000ULL
148 #define	AMD_BU_EN_L2D_ECCM_TLB		0x00008000ULL
149 #define	AMD_BU_EN_L2D_ECCM_SNP		0x00010000ULL
150 #define	AMD_BU_EN_L2D_ECCM_CPB		0x00020000ULL
151 #define	AMD_BU_EN_L2T_ECC1_SCR		0x00040000ULL
152 #define	AMD_BU_EN_L2T_ECCM_SCR		0x00080000ULL
153 
154 #define	AMD_BU_CTL_INIT_CMN \
155 	(AMD_BU_EN_S_ECC1_TLB | AMD_BU_EN_S_ECC1_HP | \
156 	AMD_BU_EN_S_ECCM_TLB | AMD_BU_EN_S_ECCM_HP | \
157 	AMD_BU_EN_L2T_PAR_ICDC | AMD_BU_EN_L2T_PAR_TLB | \
158 	AMD_BU_EN_L2T_PAR_SNP |	AMD_BU_EN_L2T_PAR_CPB | \
159 	AMD_BU_EN_L2T_PAR_SCR |	AMD_BU_EN_L2D_ECC1_TLB | \
160 	AMD_BU_EN_L2D_ECC1_SNP | AMD_BU_EN_L2D_ECC1_CPB | \
161 	AMD_BU_EN_L2D_ECCM_TLB | AMD_BU_EN_L2D_ECCM_SNP | \
162 	AMD_BU_EN_L2D_ECCM_CPB | AMD_BU_EN_L2T_ECC1_SCR | \
163 	AMD_BU_EN_L2T_ECCM_SCR)
164 
165 /*
166  * Load/Store (LS) bank error-detection enabling bits and CTL register
167  * initializer value.
168  *
169  * The Northbridge will handle Read Data errors.  That's the only type of
170  * error the LS unit can detect at present, so we won't be enabling any
171  * LS detectors.
172  */
173 
174 #define	AMD_LS_EN_S_RDE_S		0x00000001ULL
175 #define	AMD_LS_EN_S_RDE_L		0x00000002ULL
176 
177 #define	AMD_LS_CTL_INIT_CMN			0ULL
178 
179 /*
180  * NorthBridge (NB) MCi_MISC - DRAM Errors Threshold Register.
181  */
182 #define	AMD_NB_MISC_VALID		(0x1ULL << 63)
183 #define	AMD_NB_MISC_CTRP		(0x1ULL << 62)
184 #define	AMD_NB_MISC_LOCKED		(0x1ULL << 61)
185 #define	AMD_NB_MISC_CNTEN		(0x1ULL << 51)
186 #define	AMD_NB_MISC_INTTYPE		(0x1ULL << 49)
187 #define	AMD_NB_MISC_INTTYPE_MASK	(0x3ULL << 49)
188 #define	AMD_NB_MISC_OVRFLW		(0x1ULL << 48)
189 #define	AMD_NB_MISC_ERRCOUNT_MASK	(0xfffULL << 32)
190 
191 /*
192  * The Northbridge (NB) is configured using both the standard MCA CTL register
193  * and a NB-specific configuration register (NB CFG).  The AMD_NB_EN_* macros
194  * are the detector enabling bits for the NB MCA CTL register.  The
195  * AMD_NB_CFG_* bits are for the NB CFG register.
196  *
197  * The CTL register can be initialized statically, but portions of the NB CFG
198  * register must be initialized based on the current machine's configuration.
199  *
200  * The MCA NB Control Register maps to MC4_CTL[31:0], but we initialize it
201  * via and MSR write of 64 bits so define all as ULL.
202  *
203  */
204 #define	AMD_NB_EN_CORRECC		0x00000001ULL
205 #define	AMD_NB_EN_UNCORRECC		0x00000002ULL
206 #define	AMD_NB_EN_CRCERR0		0x00000004ULL
207 #define	AMD_NB_EN_CRCERR1		0x00000008ULL
208 #define	AMD_NB_EN_CRCERR2		0x00000010ULL
209 #define	AMD_NB_EN_SYNCPKT0		0x00000020ULL
210 #define	AMD_NB_EN_SYNCPKT1		0x00000040ULL
211 #define	AMD_NB_EN_SYNCPKT2		0x00000080ULL
212 #define	AMD_NB_EN_MSTRABRT		0x00000100ULL
213 #define	AMD_NB_EN_TGTABRT		0x00000200ULL
214 #define	AMD_NB_EN_GARTTBLWK		0x00000400ULL
215 #define	AMD_NB_EN_ATOMICRMW		0x00000800ULL
216 #define	AMD_NB_EN_WCHDOGTMR		0x00001000ULL
217 #define	AMD_NB_EN_DRAMPAR		0x00040000ULL	/* revs F and G */
218 
219 #define	AMD_NB_CTL_INIT_CMN /* Revs B to G; All but GARTTBLWK */ \
220 	(AMD_NB_EN_CORRECC | AMD_NB_EN_UNCORRECC | \
221 	AMD_NB_EN_CRCERR0 | AMD_NB_EN_CRCERR1 | AMD_NB_EN_CRCERR2 | \
222 	AMD_NB_EN_SYNCPKT0 | AMD_NB_EN_SYNCPKT1 | AMD_NB_EN_SYNCPKT2 | \
223 	AMD_NB_EN_MSTRABRT | AMD_NB_EN_TGTABRT | \
224 	AMD_NB_EN_ATOMICRMW | AMD_NB_EN_WCHDOGTMR)
225 
226 #define	AMD_NB_CTL_INIT_REV_FG /* Additional bits for revs F and G */ \
227 	AMD_NB_EN_DRAMPAR
228 
229 /*
230  * NB MCA Configuration register
231  */
232 #define	AMD_NB_CFG_CPUECCERREN			0x00000001
233 #define	AMD_NB_CFG_CPURDDATERREN		0x00000002
234 #define	AMD_NB_CFG_SYNCONUCECCEN		0x00000004
235 #define	AMD_NB_CFG_SYNCPKTGENDIS		0x00000008
236 #define	AMD_NB_CFG_SYNCPKTPROPDIS		0x00000010
237 #define	AMD_NB_CFG_IOMSTABORTDIS		0x00000020
238 #define	AMD_NB_CFG_CPUERRDIS			0x00000040
239 #define	AMD_NB_CFG_IOERRDIS			0x00000080
240 #define	AMD_NB_CFG_WDOGTMRDIS			0x00000100
241 #define	AMD_NB_CFG_SYNCONWDOGEN			0x00100000
242 #define	AMD_NB_CFG_SYNCONANYERREN		0x00200000
243 #define	AMD_NB_CFG_ECCEN			0x00400000
244 #define	AMD_NB_CFG_CHIPKILLECCEN		0x00800000
245 #define	AMD_NB_CFG_IORDDATERREN			0x01000000
246 #define	AMD_NB_CFG_DISPCICFGCPUERRRSP		0x02000000
247 #define	AMD_NB_CFG_NBMCATOMSTCPUEN		0x08000000
248 #define	AMD_NB_CFG_DISTGTABTCPUERRRSP		0x10000000
249 #define	AMD_NB_CFG_DISMSTABTCPUERRRSP		0x20000000
250 #define	AMD_NB_CFG_SYNCONDRAMADRPARERREN	0x40000000 /* Revs F & G */
251 
252 /*
253  * We do not initialize the NB config with an absolute value; instead we
254  * selectively add some bits and remove others.  Note that
255  * AMD_NB_CFG_{ADD,REMOVE}_{CMN,REV_FG} below are not the whole
256  * story here - additional config is performed regarding the watchdog (see
257  * ao_mca.c for details).
258  */
259 #define	AMD_NB_CFG_ADD_CMN		/* Revs B to G */ \
260 	(AMD_NB_CFG_DISPCICFGCPUERRRSP | AMD_NB_CFG_SYNCONUCECCEN | \
261 	AMD_NB_CFG_CPUECCERREN)
262 
263 #define	AMD_NB_CFG_REMOVE_CMN		/* Revs B to G */ \
264 	(AMD_NB_CFG_NBMCATOMSTCPUEN | \
265 	AMD_NB_CFG_IORDDATERREN | AMD_NB_CFG_SYNCONANYERREN | \
266 	AMD_NB_CFG_SYNCONWDOGEN | AMD_NB_CFG_IOERRDIS | \
267 	AMD_NB_CFG_IOMSTABORTDIS | AMD_NB_CFG_SYNCPKTPROPDIS | \
268 	AMD_NB_CFG_SYNCPKTGENDIS)
269 
270 #define	AMD_NB_CFG_ADD_REV_FG		/* Revs F and G */ \
271 	AMD_NB_CFG_SYNCONDRAMADRPARERREN
272 
273 #define	AMD_NB_CFG_REMOVE_REV_FG 0x0	/* Revs F and G */
274 
275 #define	AMD_NB_CFG_WDOGTMRCNTSEL_4095	0x00000000
276 #define	AMD_NB_CFG_WDOGTMRCNTSEL_2047	0x00000200
277 #define	AMD_NB_CFG_WDOGTMRCNTSEL_1023	0x00000400
278 #define	AMD_NB_CFG_WDOGTMRCNTSEL_511	0x00000600
279 #define	AMD_NB_CFG_WDOGTMRCNTSEL_255	0x00000800
280 #define	AMD_NB_CFG_WDOGTMRCNTSEL_127	0x00000a00
281 #define	AMD_NB_CFG_WDOGTMRCNTSEL_63	0x00000c00
282 #define	AMD_NB_CFG_WDOGTMRCNTSEL_31	0x00000e00
283 #define	AMD_NB_CFG_WDOGTMRCNTSEL_MASK	0x00000e00
284 #define	AMD_NB_CFG_WDOGTMRCNTSEL_SHIFT	9
285 
286 #define	AMD_NB_CFG_WDOGTMRBASESEL_1MS	0x00000000
287 #define	AMD_NB_CFG_WDOGTMRBASESEL_1US	0x00001000
288 #define	AMD_NB_CFG_WDOGTMRBASESEL_5NS	0x00002000
289 #define	AMD_NB_CFG_WDOGTMRBASESEL_MASK	0x00003000
290 #define	AMD_NB_CFG_WDOGTMRBASESEL_SHIFT	12
291 
292 #define	AMD_NB_CFG_LDTLINKSEL_MASK	0x0000c000
293 #define	AMD_NB_CFG_LDTLINKSEL_SHIFT	14
294 
295 #define	AMD_NB_CFG_GENCRCERRBYTE0	0x00010000
296 #define	AMD_NB_CFG_GENCRCERRBYTE1	0x00020000
297 
298 /*
299  * The AMD extended error code is just one nibble of the upper 16 bits
300  * of the bank status (the resy being used for syndrome etc).  So we use
301  * AMD_EXT_ERRCODE to retrieve that extended error code, not the generic
302  * MCAX86_MSERRCODE.
303  */
304 #define	_AMD_ERREXT_MASK		0x00000000000f0000ULL
305 #define	_AMD_ERREXT_SHIFT		16
306 #define	AMD_EXT_ERRCODE(stat) \
307 	(((stat) & _AMD_ERREXT_MASK) >> _AMD_ERREXT_SHIFT)
308 #define	AMD_EXT_MKERRCODE(errcode) \
309 	(((errcode) << _AMD_ERREXT_SHIFT) & _AMD_ERREXT_MASK)
310 
311 #define	AMD_BANK_STAT_CECC		0x0000400000000000ULL
312 #define	AMD_BANK_STAT_UECC		0x0000200000000000ULL
313 #define	AMD_BANK_STAT_SCRUB		0x0000010000000000ULL
314 
315 	/* syndrome[7:0] */
316 #define	AMD_BANK_STAT_SYND_MASK		0x007f800000000000ULL
317 #define	AMD_BANK_STAT_SYND_SHIFT	47
318 
319 #define	AMD_BANK_SYND(stat) \
320 	(((stat) & AMD_BANK_STAT_SYND_MASK) >> AMD_BANK_STAT_SYND_SHIFT)
321 #define	AMD_BANK_MKSYND(synd) \
322 	(((uint64_t)(synd) << AMD_BANK_STAT_SYND_SHIFT) & \
323 	AMD_BANK_STAT_SYND_MASK)
324 
325 #define	AMD_NB_STAT_DRAMCHANNEL		0x0000020000000000ULL
326 #define	AMD_NB_STAT_LDTLINK_MASK	0x0000007000000000ULL
327 #define	AMD_NB_STAT_LDTLINK_SHIFT	4
328 #define	AMD_NB_STAT_ERRCPU1		0x0000000200000000ULL
329 #define	AMD_NB_STAT_ERRCPU0		0x0000000100000000ULL
330 
331 #define	AMD_NB_STAT_CKSYND_MASK		0x00000000ff000000 /* syndrome[15:8] */
332 #define	AMD_NB_STAT_CKSYND_SHIFT	(24 - 8) /* shift [31:24] to [15:8] */
333 
334 #define	AMD_NB_STAT_CKSYND(stat) \
335 	((((stat) & AMD_NB_STAT_CKSYND_MASK) >> AMD_NB_STAT_CKSYND_SHIFT) | \
336 	AMD_BANK_SYND((stat)))
337 
338 #define	AMD_NB_STAT_MKCKSYND(synd) \
339 	((((uint64_t)(synd) << AMD_NB_STAT_CKSYND_SHIFT) & \
340 	AMD_NB_STAT_CKSYND_MASK) | AMD_BANK_MKSYND(synd))
341 
342 #define	AMD_ERREXT_MASK			0x00000000000f0000ULL
343 #define	AMD_ERREXT_SHIFT		16
344 
345 #define	AMD_ERRCODE_TLB_BIT		4
346 #define	AMD_ERRCODE_MEM_BIT		8
347 #define	AMD_ERRCODE_BUS_BIT		11
348 
349 #define	AMD_ERRCODE_TLB_MASK		0xfff0
350 #define	AMD_ERRCODE_MEM_MASK		0xff00
351 #define	AMD_ERRCODE_BUS_MASK		0xf800
352 
353 #define	AMD_ERRCODE_MKTLB(tt, ll) MCAX86_MKERRCODE_TLB(tt, ll)
354 #define	AMD_ERRCODE_ISTLB(code) MCAX86_ERRCODE_ISTLB(code)
355 
356 #define	AMD_ERRCODE_MKMEM(r4, tt, ll) MCAX86_MKERRCODE_MEMHIER(r4, tt, ll)
357 #define	AMD_ERRCODE_ISMEM(code) MCAX86_ERRCODE_ISMEMHIER(code)
358 
359 #define	AMD_ERRCODE_MKBUS(pp, t, r4, ii, ll) \
360 	MCAX86_MKERRCODE_BUS_INTERCONNECT(pp, t, r4, ii, ll)
361 #define	AMD_ERRCODE_ISBUS(code) MCAX86_ERRCODE_ISBUS_INTERCONNECT(code)
362 
363 #define	AMD_NB_ADDRLO_MASK		0xfffffff8
364 #define	AMD_NB_ADDRHI_MASK		0x000000ff
365 
366 #define	AMD_SYNDTYPE_ECC		0
367 #define	AMD_SYNDTYPE_CHIPKILL		1
368 
369 #define	AMD_NB_SCRUBCTL_DRAM_MASK	0x0000001f
370 #define	AMD_NB_SCRUBCTL_DRAM_SHIFT	0
371 #define	AMD_NB_SCRUBCTL_L2_MASK		0x00001f00
372 #define	AMD_NB_SCRUBCTL_L2_SHIFT	8
373 #define	AMD_NB_SCRUBCTL_DC_MASK		0x001f0000
374 #define	AMD_NB_SCRUBCTL_DC_SHIFT	16
375 #define	AMD_NB_SCRUBCTL_L3_MASK		0x1f000000
376 #define	AMD_NB_SCRUBCTL_L3_SHIFT	24
377 
378 #define	AMD_NB_SCRUBCTL_RATE_NONE	0
379 #define	AMD_NB_SCRUBCTL_RATE_MAX	0x16
380 
381 #define	AMD_NB_SCRUBADDR_LO_MASK	0xffffffc0
382 #define	AMD_NB_SCRUBADDR_LO_SHIFT	6
383 #define	AMD_NB_SCRUBADDR_LO_SCRUBREDIREN 0x1
384 #define	AMD_NB_SCRUBADDR_HI_MASK	0x000000ff
385 
386 #define	AMD_NB_SCRUBADDR_MKLO(addr) \
387 	(((addr) & AMD_NB_SCRUBADDR_LO_MASK) >> AMD_NB_SCRUBADDR_LO_SHIFT)
388 
389 #define	AMD_NB_SCRUBADDR_MKHI(addr) \
390 	(((addr) >> 32) & AMD_NB_SCRUBADDR_HI_MASK)
391 
392 #define	AMD_NB_MKSCRUBCTL(l3, dc, l2, dr) ( \
393 	(((l3) << AMD_NB_SCRUBCTL_L3_SHIFT) & AMD_NB_SCRUBCTL_L3_MASK) | \
394 	(((dc) << AMD_NB_SCRUBCTL_DC_SHIFT) & AMD_NB_SCRUBCTL_DC_MASK) | \
395 	(((l2) << AMD_NB_SCRUBCTL_L2_SHIFT) & AMD_NB_SCRUBCTL_L2_MASK) | \
396 	(((dr) << AMD_NB_SCRUBCTL_DRAM_SHIFT) & AMD_NB_SCRUBCTL_DRAM_MASK))
397 
398 #ifdef __cplusplus
399 }
400 #endif
401 
402 #endif /* _SYS_MCA_AMD_H */
403