1//===-- llvm/Support/TargetOpcodes.def - Target Indep Opcodes ---*- C++ -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the target independent instruction opcodes. 10// 11//===----------------------------------------------------------------------===// 12 13// NOTE: NO INCLUDE GUARD DESIRED! 14 15/// HANDLE_TARGET_OPCODE defines an opcode and its associated enum value. 16/// 17#ifndef HANDLE_TARGET_OPCODE 18#define HANDLE_TARGET_OPCODE(OPC, NUM) 19#endif 20 21/// HANDLE_TARGET_OPCODE_MARKER defines an alternative identifier for an opcode. 22/// 23#ifndef HANDLE_TARGET_OPCODE_MARKER 24#define HANDLE_TARGET_OPCODE_MARKER(IDENT, OPC) 25#endif 26 27/// Every instruction defined here must also appear in Target.td. 28/// 29HANDLE_TARGET_OPCODE(PHI) 30HANDLE_TARGET_OPCODE(INLINEASM) 31HANDLE_TARGET_OPCODE(INLINEASM_BR) 32HANDLE_TARGET_OPCODE(CFI_INSTRUCTION) 33HANDLE_TARGET_OPCODE(EH_LABEL) 34HANDLE_TARGET_OPCODE(GC_LABEL) 35HANDLE_TARGET_OPCODE(ANNOTATION_LABEL) 36 37/// KILL - This instruction is a noop that is used only to adjust the 38/// liveness of registers. This can be useful when dealing with 39/// sub-registers. 40HANDLE_TARGET_OPCODE(KILL) 41 42/// EXTRACT_SUBREG - This instruction takes two operands: a register 43/// that has subregisters, and a subregister index. It returns the 44/// extracted subregister value. This is commonly used to implement 45/// truncation operations on target architectures which support it. 46HANDLE_TARGET_OPCODE(EXTRACT_SUBREG) 47 48/// INSERT_SUBREG - This instruction takes three operands: a register that 49/// has subregisters, a register providing an insert value, and a 50/// subregister index. It returns the value of the first register with the 51/// value of the second register inserted. The first register is often 52/// defined by an IMPLICIT_DEF, because it is commonly used to implement 53/// anyext operations on target architectures which support it. 54HANDLE_TARGET_OPCODE(INSERT_SUBREG) 55 56/// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef. 57HANDLE_TARGET_OPCODE(IMPLICIT_DEF) 58 59/// SUBREG_TO_REG - Assert the value of bits in a super register. 60/// The result of this instruction is the value of the second operand inserted 61/// into the subregister specified by the third operand. All other bits are 62/// assumed to be equal to the bits in the immediate integer constant in the 63/// first operand. This instruction just communicates information; No code 64/// should be generated. 65/// This is typically used after an instruction where the write to a subregister 66/// implicitly cleared the bits in the super registers. 67HANDLE_TARGET_OPCODE(SUBREG_TO_REG) 68 69/// COPY_TO_REGCLASS - This instruction is a placeholder for a plain 70/// register-to-register copy into a specific register class. This is only 71/// used between instruction selection and MachineInstr creation, before 72/// virtual registers have been created for all the instructions, and it's 73/// only needed in cases where the register classes implied by the 74/// instructions are insufficient. It is emitted as a COPY MachineInstr. 75HANDLE_TARGET_OPCODE(COPY_TO_REGCLASS) 76 77/// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic 78HANDLE_TARGET_OPCODE(DBG_VALUE) 79 80/// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic with a variadic 81/// list of locations 82HANDLE_TARGET_OPCODE(DBG_VALUE_LIST) 83 84/// DBG_INSTR_REF - A mapping of llvm.dbg.value referring to the instruction 85/// that defines the value, rather than a virtual register. 86HANDLE_TARGET_OPCODE(DBG_INSTR_REF) 87 88/// DBG_PHI - remainder of a PHI, identifies a program point where values 89/// merge under control flow. 90HANDLE_TARGET_OPCODE(DBG_PHI) 91 92/// DBG_LABEL - a mapping of the llvm.dbg.label intrinsic 93HANDLE_TARGET_OPCODE(DBG_LABEL) 94 95/// REG_SEQUENCE - This variadic instruction is used to form a register that 96/// represents a consecutive sequence of sub-registers. It's used as a 97/// register coalescing / allocation aid and must be eliminated before code 98/// emission. 99// In SDNode form, the first operand encodes the register class created by 100// the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index 101// pair. Once it has been lowered to a MachineInstr, the regclass operand 102// is no longer present. 103/// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5 104/// After register coalescing references of v1024 should be replace with 105/// v1027:3, v1025 with v1027:4, etc. 106HANDLE_TARGET_OPCODE(REG_SEQUENCE) 107 108/// COPY - Target-independent register copy. This instruction can also be 109/// used to copy between subregisters of virtual registers. 110HANDLE_TARGET_OPCODE(COPY) 111 112/// BUNDLE - This instruction represents an instruction bundle. Instructions 113/// which immediately follow a BUNDLE instruction which are marked with 114/// 'InsideBundle' flag are inside the bundle. 115HANDLE_TARGET_OPCODE(BUNDLE) 116 117/// Lifetime markers. 118HANDLE_TARGET_OPCODE(LIFETIME_START) 119HANDLE_TARGET_OPCODE(LIFETIME_END) 120 121/// Pseudo probe 122HANDLE_TARGET_OPCODE(PSEUDO_PROBE) 123 124/// Arithmetic fence. 125HANDLE_TARGET_OPCODE(ARITH_FENCE) 126 127/// A Stackmap instruction captures the location of live variables at its 128/// position in the instruction stream. It is followed by a shadow of bytes 129/// that must lie within the function and not contain another stackmap. 130HANDLE_TARGET_OPCODE(STACKMAP) 131 132/// FEntry all - This is a marker instruction which gets translated into a raw fentry call. 133HANDLE_TARGET_OPCODE(FENTRY_CALL) 134 135/// Patchable call instruction - this instruction represents a call to a 136/// constant address, followed by a series of NOPs. It is intended to 137/// support optimizations for dynamic languages (such as javascript) that 138/// rewrite calls to runtimes with more efficient code sequences. 139/// This also implies a stack map. 140HANDLE_TARGET_OPCODE(PATCHPOINT) 141 142/// This pseudo-instruction loads the stack guard value. Targets which need 143/// to prevent the stack guard value or address from being spilled to the 144/// stack should override TargetLowering::emitLoadStackGuardNode and 145/// additionally expand this pseudo after register allocation. 146HANDLE_TARGET_OPCODE(LOAD_STACK_GUARD) 147 148/// These are used to support call sites that must have the stack adjusted 149/// before the call (e.g. to initialize an argument passed by value). 150/// See llvm.call.preallocated.{setup,arg} in the LangRef for more details. 151HANDLE_TARGET_OPCODE(PREALLOCATED_SETUP) 152HANDLE_TARGET_OPCODE(PREALLOCATED_ARG) 153 154/// Call instruction with associated vm state for deoptimization and list 155/// of live pointers for relocation by the garbage collector. It is 156/// intended to support garbage collection with fully precise relocating 157/// collectors and deoptimizations in either the callee or caller. 158HANDLE_TARGET_OPCODE(STATEPOINT) 159 160/// Instruction that records the offset of a local stack allocation passed to 161/// llvm.localescape. It has two arguments: the symbol for the label and the 162/// frame index of the local stack allocation. 163HANDLE_TARGET_OPCODE(LOCAL_ESCAPE) 164 165/// Wraps a machine instruction which can fault, bundled with associated 166/// information on how to handle such a fault. 167/// For example loading instruction that may page fault, bundled with associated 168/// information on how to handle such a page fault. It is intended to support 169/// "zero cost" null checks in managed languages by allowing LLVM to fold 170/// comparisons into existing memory operations. 171HANDLE_TARGET_OPCODE(FAULTING_OP) 172 173/// Precedes a machine instruction to add patchability constraints. An 174/// instruction after PATCHABLE_OP has to either have a minimum 175/// size or be preceded with a nop of that size. The first operand is 176/// an immediate denoting the minimum size of the following instruction. 177HANDLE_TARGET_OPCODE(PATCHABLE_OP) 178 179/// This is a marker instruction which gets translated into a nop sled, useful 180/// for inserting instrumentation instructions at runtime. 181HANDLE_TARGET_OPCODE(PATCHABLE_FUNCTION_ENTER) 182 183/// Wraps a return instruction and its operands to enable adding nop sleds 184/// either before or after the return. The nop sleds are useful for inserting 185/// instrumentation instructions at runtime. 186/// The patch here replaces the return instruction. 187HANDLE_TARGET_OPCODE(PATCHABLE_RET) 188 189/// This is a marker instruction which gets translated into a nop sled, useful 190/// for inserting instrumentation instructions at runtime. 191/// The patch here prepends the return instruction. 192/// The same thing as in x86_64 is not possible for ARM because it has multiple 193/// return instructions. Furthermore, CPU allows parametrized and even 194/// conditional return instructions. In the current ARM implementation we are 195/// making use of the fact that currently LLVM doesn't seem to generate 196/// conditional return instructions. 197/// On ARM, the same instruction can be used for popping multiple registers 198/// from the stack and returning (it just pops pc register too), and LLVM 199/// generates it sometimes. So we can't insert the sled between this stack 200/// adjustment and the return without splitting the original instruction into 2 201/// instructions. So on ARM, rather than jumping into the exit trampoline, we 202/// call it, it does the tracing, preserves the stack and returns. 203HANDLE_TARGET_OPCODE(PATCHABLE_FUNCTION_EXIT) 204 205/// Wraps a tail call instruction and its operands to enable adding nop sleds 206/// either before or after the tail exit. We use this as a disambiguation from 207/// PATCHABLE_RET which specifically only works for return instructions. 208HANDLE_TARGET_OPCODE(PATCHABLE_TAIL_CALL) 209 210/// Wraps a logging call and its arguments with nop sleds. At runtime, this can 211/// be patched to insert instrumentation instructions. 212HANDLE_TARGET_OPCODE(PATCHABLE_EVENT_CALL) 213 214/// Wraps a typed logging call and its argument with nop sleds. At runtime, this 215/// can be patched to insert instrumentation instructions. 216HANDLE_TARGET_OPCODE(PATCHABLE_TYPED_EVENT_CALL) 217 218HANDLE_TARGET_OPCODE(ICALL_BRANCH_FUNNEL) 219 220// This is a fence with the singlethread scope. It represents a compiler memory 221// barrier, but does not correspond to any generated instruction. 222HANDLE_TARGET_OPCODE(MEMBARRIER) 223 224// Provides information about what jump table the following indirect branch is 225// using. 226HANDLE_TARGET_OPCODE(JUMP_TABLE_DEBUG_INFO) 227 228HANDLE_TARGET_OPCODE(CONVERGENCECTRL_ENTRY) 229HANDLE_TARGET_OPCODE(CONVERGENCECTRL_ANCHOR) 230HANDLE_TARGET_OPCODE(CONVERGENCECTRL_LOOP) 231HANDLE_TARGET_OPCODE(CONVERGENCECTRL_GLUE) 232 233/// The following generic opcodes are not supposed to appear after ISel. 234/// This is something we might want to relax, but for now, this is convenient 235/// to produce diagnostics. 236 237/// Instructions which should not exist past instruction selection, but do not 238/// generate code. These instructions only act as optimization hints. 239HANDLE_TARGET_OPCODE(G_ASSERT_SEXT) 240HANDLE_TARGET_OPCODE(G_ASSERT_ZEXT) 241HANDLE_TARGET_OPCODE(G_ASSERT_ALIGN) 242HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPTIMIZATION_HINT_START, 243 G_ASSERT_SEXT) 244HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPTIMIZATION_HINT_END, 245 G_ASSERT_ALIGN) 246 247/// Generic ADD instruction. This is an integer add. 248HANDLE_TARGET_OPCODE(G_ADD) 249HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_START, G_ADD) 250 251/// Generic SUB instruction. This is an integer sub. 252HANDLE_TARGET_OPCODE(G_SUB) 253 254// Generic multiply instruction. 255HANDLE_TARGET_OPCODE(G_MUL) 256 257// Generic signed division instruction. 258HANDLE_TARGET_OPCODE(G_SDIV) 259 260// Generic unsigned division instruction. 261HANDLE_TARGET_OPCODE(G_UDIV) 262 263// Generic signed remainder instruction. 264HANDLE_TARGET_OPCODE(G_SREM) 265 266// Generic unsigned remainder instruction. 267HANDLE_TARGET_OPCODE(G_UREM) 268 269// Generic signed divrem instruction. 270HANDLE_TARGET_OPCODE(G_SDIVREM) 271 272// Generic unsigned divrem instruction. 273HANDLE_TARGET_OPCODE(G_UDIVREM) 274 275/// Generic bitwise and instruction. 276HANDLE_TARGET_OPCODE(G_AND) 277 278/// Generic bitwise or instruction. 279HANDLE_TARGET_OPCODE(G_OR) 280 281/// Generic bitwise exclusive-or instruction. 282HANDLE_TARGET_OPCODE(G_XOR) 283 284 285HANDLE_TARGET_OPCODE(G_IMPLICIT_DEF) 286 287/// Generic PHI instruction with types. 288HANDLE_TARGET_OPCODE(G_PHI) 289 290/// Generic instruction to materialize the address of an alloca or other 291/// stack-based object. 292HANDLE_TARGET_OPCODE(G_FRAME_INDEX) 293 294/// Generic reference to global value. 295HANDLE_TARGET_OPCODE(G_GLOBAL_VALUE) 296 297/// Generic ptrauth-signed reference to global value. 298HANDLE_TARGET_OPCODE(G_PTRAUTH_GLOBAL_VALUE) 299 300/// Generic instruction to materialize the address of an object in the constant 301/// pool. 302HANDLE_TARGET_OPCODE(G_CONSTANT_POOL) 303 304/// Generic instruction to extract blocks of bits from the register given 305/// (typically a sub-register COPY after instruction selection). 306HANDLE_TARGET_OPCODE(G_EXTRACT) 307 308HANDLE_TARGET_OPCODE(G_UNMERGE_VALUES) 309 310/// Generic instruction to insert blocks of bits from the registers given into 311/// the source. 312HANDLE_TARGET_OPCODE(G_INSERT) 313 314/// Generic instruction to paste a variable number of components together into a 315/// larger register. 316HANDLE_TARGET_OPCODE(G_MERGE_VALUES) 317 318/// Generic instruction to create a vector value from a number of scalar 319/// components. 320HANDLE_TARGET_OPCODE(G_BUILD_VECTOR) 321 322/// Generic instruction to create a vector value from a number of scalar 323/// components, which have types larger than the result vector elt type. 324HANDLE_TARGET_OPCODE(G_BUILD_VECTOR_TRUNC) 325 326/// Generic instruction to create a vector by concatenating multiple vectors. 327HANDLE_TARGET_OPCODE(G_CONCAT_VECTORS) 328 329/// Generic pointer to int conversion. 330HANDLE_TARGET_OPCODE(G_PTRTOINT) 331 332/// Generic int to pointer conversion. 333HANDLE_TARGET_OPCODE(G_INTTOPTR) 334 335/// Generic bitcast. The source and destination types must be different, or a 336/// COPY is the relevant instruction. 337HANDLE_TARGET_OPCODE(G_BITCAST) 338 339/// Generic freeze. 340HANDLE_TARGET_OPCODE(G_FREEZE) 341 342/// Constant folding barrier. 343HANDLE_TARGET_OPCODE(G_CONSTANT_FOLD_BARRIER) 344 345// INTRINSIC fptrunc_round intrinsic. 346HANDLE_TARGET_OPCODE(G_INTRINSIC_FPTRUNC_ROUND) 347 348/// INTRINSIC trunc intrinsic. 349HANDLE_TARGET_OPCODE(G_INTRINSIC_TRUNC) 350 351/// INTRINSIC round intrinsic. 352HANDLE_TARGET_OPCODE(G_INTRINSIC_ROUND) 353 354/// INTRINSIC round to integer intrinsic. 355HANDLE_TARGET_OPCODE(G_INTRINSIC_LRINT) 356 357/// INTRINSIC long round to integer intrinsic. 358HANDLE_TARGET_OPCODE(G_INTRINSIC_LLRINT) 359 360/// INTRINSIC roundeven intrinsic. 361HANDLE_TARGET_OPCODE(G_INTRINSIC_ROUNDEVEN) 362 363/// INTRINSIC readcyclecounter 364HANDLE_TARGET_OPCODE(G_READCYCLECOUNTER) 365 366/// INTRINSIC readsteadycounter 367HANDLE_TARGET_OPCODE(G_READSTEADYCOUNTER) 368 369/// Generic load (including anyext load) 370HANDLE_TARGET_OPCODE(G_LOAD) 371 372/// Generic signext load 373HANDLE_TARGET_OPCODE(G_SEXTLOAD) 374 375/// Generic zeroext load 376HANDLE_TARGET_OPCODE(G_ZEXTLOAD) 377 378/// Generic indexed load (including anyext load) 379HANDLE_TARGET_OPCODE(G_INDEXED_LOAD) 380 381/// Generic indexed signext load 382HANDLE_TARGET_OPCODE(G_INDEXED_SEXTLOAD) 383 384/// Generic indexed zeroext load 385HANDLE_TARGET_OPCODE(G_INDEXED_ZEXTLOAD) 386 387/// Generic store. 388HANDLE_TARGET_OPCODE(G_STORE) 389 390/// Generic indexed store. 391HANDLE_TARGET_OPCODE(G_INDEXED_STORE) 392 393/// Generic atomic cmpxchg with internal success check. 394HANDLE_TARGET_OPCODE(G_ATOMIC_CMPXCHG_WITH_SUCCESS) 395 396/// Generic atomic cmpxchg. 397HANDLE_TARGET_OPCODE(G_ATOMIC_CMPXCHG) 398 399/// Generic atomicrmw. 400HANDLE_TARGET_OPCODE(G_ATOMICRMW_XCHG) 401HANDLE_TARGET_OPCODE(G_ATOMICRMW_ADD) 402HANDLE_TARGET_OPCODE(G_ATOMICRMW_SUB) 403HANDLE_TARGET_OPCODE(G_ATOMICRMW_AND) 404HANDLE_TARGET_OPCODE(G_ATOMICRMW_NAND) 405HANDLE_TARGET_OPCODE(G_ATOMICRMW_OR) 406HANDLE_TARGET_OPCODE(G_ATOMICRMW_XOR) 407HANDLE_TARGET_OPCODE(G_ATOMICRMW_MAX) 408HANDLE_TARGET_OPCODE(G_ATOMICRMW_MIN) 409HANDLE_TARGET_OPCODE(G_ATOMICRMW_UMAX) 410HANDLE_TARGET_OPCODE(G_ATOMICRMW_UMIN) 411HANDLE_TARGET_OPCODE(G_ATOMICRMW_FADD) 412HANDLE_TARGET_OPCODE(G_ATOMICRMW_FSUB) 413HANDLE_TARGET_OPCODE(G_ATOMICRMW_FMAX) 414HANDLE_TARGET_OPCODE(G_ATOMICRMW_FMIN) 415HANDLE_TARGET_OPCODE(G_ATOMICRMW_UINC_WRAP) 416HANDLE_TARGET_OPCODE(G_ATOMICRMW_UDEC_WRAP) 417 418// Marker for start of Generic AtomicRMW opcodes 419HANDLE_TARGET_OPCODE_MARKER(GENERIC_ATOMICRMW_OP_START, G_ATOMICRMW_XCHG) 420 421// Marker for end of Generic AtomicRMW opcodes 422HANDLE_TARGET_OPCODE_MARKER(GENERIC_ATOMICRMW_OP_END, G_ATOMICRMW_UDEC_WRAP) 423 424// Generic atomic fence 425HANDLE_TARGET_OPCODE(G_FENCE) 426 427/// Generic prefetch 428HANDLE_TARGET_OPCODE(G_PREFETCH) 429 430/// Generic conditional branch instruction. 431HANDLE_TARGET_OPCODE(G_BRCOND) 432 433/// Generic indirect branch instruction. 434HANDLE_TARGET_OPCODE(G_BRINDIRECT) 435 436/// Begin an invoke region marker. 437HANDLE_TARGET_OPCODE(G_INVOKE_REGION_START) 438 439/// Generic intrinsic use (without side effects). 440HANDLE_TARGET_OPCODE(G_INTRINSIC) 441 442/// Generic intrinsic use (with side effects). 443HANDLE_TARGET_OPCODE(G_INTRINSIC_W_SIDE_EFFECTS) 444 445/// Generic intrinsic use (without side effects). 446HANDLE_TARGET_OPCODE(G_INTRINSIC_CONVERGENT) 447 448/// Generic intrinsic use (with side effects). 449HANDLE_TARGET_OPCODE(G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS) 450 451/// Generic extension allowing rubbish in high bits. 452HANDLE_TARGET_OPCODE(G_ANYEXT) 453 454/// Generic instruction to discard the high bits of a register. This differs 455/// from (G_EXTRACT val, 0) on its action on vectors: G_TRUNC will truncate 456/// each element individually, G_EXTRACT will typically discard the high 457/// elements of the vector. 458HANDLE_TARGET_OPCODE(G_TRUNC) 459 460/// Generic integer constant. 461HANDLE_TARGET_OPCODE(G_CONSTANT) 462 463/// Generic floating constant. 464HANDLE_TARGET_OPCODE(G_FCONSTANT) 465 466/// Generic va_start instruction. Stores to its one pointer operand. 467HANDLE_TARGET_OPCODE(G_VASTART) 468 469/// Generic va_arg instruction. Stores to its one pointer operand. 470HANDLE_TARGET_OPCODE(G_VAARG) 471 472// Generic sign extend 473HANDLE_TARGET_OPCODE(G_SEXT) 474HANDLE_TARGET_OPCODE(G_SEXT_INREG) 475 476// Generic zero extend 477HANDLE_TARGET_OPCODE(G_ZEXT) 478 479// Generic left-shift 480HANDLE_TARGET_OPCODE(G_SHL) 481 482// Generic logical right-shift 483HANDLE_TARGET_OPCODE(G_LSHR) 484 485// Generic arithmetic right-shift 486HANDLE_TARGET_OPCODE(G_ASHR) 487 488// Generic funnel left shift 489HANDLE_TARGET_OPCODE(G_FSHL) 490 491// Generic funnel right shift 492HANDLE_TARGET_OPCODE(G_FSHR) 493 494// Generic right rotate 495HANDLE_TARGET_OPCODE(G_ROTR) 496 497// Generic left rotate 498HANDLE_TARGET_OPCODE(G_ROTL) 499 500/// Generic integer-base comparison, also applicable to vectors of integers. 501HANDLE_TARGET_OPCODE(G_ICMP) 502 503/// Generic floating-point comparison, also applicable to vectors. 504HANDLE_TARGET_OPCODE(G_FCMP) 505 506/// Generic signed 3-way comparison. 507HANDLE_TARGET_OPCODE(G_SCMP) 508 509/// Generic unsigned 3-way comparison. 510HANDLE_TARGET_OPCODE(G_UCMP) 511 512/// Generic select. 513HANDLE_TARGET_OPCODE(G_SELECT) 514 515/// Generic unsigned add instruction, consuming the normal operands and 516/// producing the result and a carry flag. 517HANDLE_TARGET_OPCODE(G_UADDO) 518 519/// Generic unsigned add instruction, consuming the normal operands plus a carry 520/// flag, and similarly producing the result and a carry flag. 521HANDLE_TARGET_OPCODE(G_UADDE) 522 523/// Generic unsigned sub instruction, consuming the normal operands and 524/// producing the result and a carry flag. 525HANDLE_TARGET_OPCODE(G_USUBO) 526 527/// Generic unsigned subtract instruction, consuming the normal operands plus a 528/// carry flag, and similarly producing the result and a carry flag. 529HANDLE_TARGET_OPCODE(G_USUBE) 530 531/// Generic signed add instruction, producing the result and a signed overflow 532/// flag. 533HANDLE_TARGET_OPCODE(G_SADDO) 534 535/// Generic signed add instruction, consuming the normal operands plus a carry 536/// flag, and similarly producing the result and a carry flag. 537HANDLE_TARGET_OPCODE(G_SADDE) 538 539/// Generic signed subtract instruction, producing the result and a signed 540/// overflow flag. 541HANDLE_TARGET_OPCODE(G_SSUBO) 542 543/// Generic signed sub instruction, consuming the normal operands plus a carry 544/// flag, and similarly producing the result and a carry flag. 545HANDLE_TARGET_OPCODE(G_SSUBE) 546 547/// Generic unsigned multiply instruction, producing the result and a signed 548/// overflow flag. 549HANDLE_TARGET_OPCODE(G_UMULO) 550 551/// Generic signed multiply instruction, producing the result and a signed 552/// overflow flag. 553HANDLE_TARGET_OPCODE(G_SMULO) 554 555// Multiply two numbers at twice the incoming bit width (unsigned) and return 556// the high half of the result. 557HANDLE_TARGET_OPCODE(G_UMULH) 558 559// Multiply two numbers at twice the incoming bit width (signed) and return 560// the high half of the result. 561HANDLE_TARGET_OPCODE(G_SMULH) 562 563/// Generic saturating unsigned addition. 564HANDLE_TARGET_OPCODE(G_UADDSAT) 565 566/// Generic saturating signed addition. 567HANDLE_TARGET_OPCODE(G_SADDSAT) 568 569/// Generic saturating unsigned subtraction. 570HANDLE_TARGET_OPCODE(G_USUBSAT) 571 572/// Generic saturating signed subtraction. 573HANDLE_TARGET_OPCODE(G_SSUBSAT) 574 575/// Generic saturating unsigned left shift. 576HANDLE_TARGET_OPCODE(G_USHLSAT) 577 578/// Generic saturating signed left shift. 579HANDLE_TARGET_OPCODE(G_SSHLSAT) 580 581// Perform signed fixed point multiplication 582HANDLE_TARGET_OPCODE(G_SMULFIX) 583 584// Perform unsigned fixed point multiplication 585HANDLE_TARGET_OPCODE(G_UMULFIX) 586 587// Perform signed, saturating fixed point multiplication 588HANDLE_TARGET_OPCODE(G_SMULFIXSAT) 589 590// Perform unsigned, saturating fixed point multiplication 591HANDLE_TARGET_OPCODE(G_UMULFIXSAT) 592 593// Perform signed fixed point division 594HANDLE_TARGET_OPCODE(G_SDIVFIX) 595 596// Perform unsigned fixed point division 597HANDLE_TARGET_OPCODE(G_UDIVFIX) 598 599// Perform signed, saturating fixed point division 600HANDLE_TARGET_OPCODE(G_SDIVFIXSAT) 601 602// Perform unsigned, saturating fixed point division 603HANDLE_TARGET_OPCODE(G_UDIVFIXSAT) 604 605/// Generic FP addition. 606HANDLE_TARGET_OPCODE(G_FADD) 607 608/// Generic FP subtraction. 609HANDLE_TARGET_OPCODE(G_FSUB) 610 611/// Generic FP multiplication. 612HANDLE_TARGET_OPCODE(G_FMUL) 613 614/// Generic FMA multiplication. Behaves like llvm fma intrinsic 615HANDLE_TARGET_OPCODE(G_FMA) 616 617/// Generic FP multiply and add. Behaves as separate fmul and fadd. 618HANDLE_TARGET_OPCODE(G_FMAD) 619 620/// Generic FP division. 621HANDLE_TARGET_OPCODE(G_FDIV) 622 623/// Generic FP remainder. 624HANDLE_TARGET_OPCODE(G_FREM) 625 626/// Generic FP exponentiation. 627HANDLE_TARGET_OPCODE(G_FPOW) 628 629/// Generic FP exponentiation, with an integer exponent. 630HANDLE_TARGET_OPCODE(G_FPOWI) 631 632/// Generic base-e exponential of a value. 633HANDLE_TARGET_OPCODE(G_FEXP) 634 635/// Generic base-2 exponential of a value. 636HANDLE_TARGET_OPCODE(G_FEXP2) 637 638/// Generic base-10 exponential of a value. 639HANDLE_TARGET_OPCODE(G_FEXP10) 640 641/// Floating point base-e logarithm of a value. 642HANDLE_TARGET_OPCODE(G_FLOG) 643 644/// Floating point base-2 logarithm of a value. 645HANDLE_TARGET_OPCODE(G_FLOG2) 646 647/// Floating point base-10 logarithm of a value. 648HANDLE_TARGET_OPCODE(G_FLOG10) 649 650/// Floating point x * 2^n 651HANDLE_TARGET_OPCODE(G_FLDEXP) 652 653/// Floating point extract fraction and exponent. 654HANDLE_TARGET_OPCODE(G_FFREXP) 655 656/// Generic FP negation. 657HANDLE_TARGET_OPCODE(G_FNEG) 658 659/// Generic FP extension. 660HANDLE_TARGET_OPCODE(G_FPEXT) 661 662/// Generic float to signed-int conversion 663HANDLE_TARGET_OPCODE(G_FPTRUNC) 664 665/// Generic float to signed-int conversion 666HANDLE_TARGET_OPCODE(G_FPTOSI) 667 668/// Generic float to unsigned-int conversion 669HANDLE_TARGET_OPCODE(G_FPTOUI) 670 671/// Generic signed-int to float conversion 672HANDLE_TARGET_OPCODE(G_SITOFP) 673 674/// Generic unsigned-int to float conversion 675HANDLE_TARGET_OPCODE(G_UITOFP) 676 677/// Generic FP absolute value. 678HANDLE_TARGET_OPCODE(G_FABS) 679 680/// FCOPYSIGN(X, Y) - Return the value of X with the sign of Y. NOTE: This does 681/// not require that X and Y have the same type, just that they are both 682/// floating point. X and the result must have the same type. FCOPYSIGN(f32, 683/// f64) is allowed. 684HANDLE_TARGET_OPCODE(G_FCOPYSIGN) 685 686/// Generic test for floating-point class. 687HANDLE_TARGET_OPCODE(G_IS_FPCLASS) 688 689/// Generic FP canonicalize value. 690HANDLE_TARGET_OPCODE(G_FCANONICALIZE) 691 692/// FP min/max matching libm's fmin/fmax 693HANDLE_TARGET_OPCODE(G_FMINNUM) 694HANDLE_TARGET_OPCODE(G_FMAXNUM) 695 696/// FP min/max matching IEEE-754 2008's minnum/maxnum semantics. 697HANDLE_TARGET_OPCODE(G_FMINNUM_IEEE) 698HANDLE_TARGET_OPCODE(G_FMAXNUM_IEEE) 699 700/// FP min/max matching IEEE-754 2018 draft semantics. 701HANDLE_TARGET_OPCODE(G_FMINIMUM) 702HANDLE_TARGET_OPCODE(G_FMAXIMUM) 703 704/// Access to FP environment. 705HANDLE_TARGET_OPCODE(G_GET_FPENV) 706HANDLE_TARGET_OPCODE(G_SET_FPENV) 707HANDLE_TARGET_OPCODE(G_RESET_FPENV) 708HANDLE_TARGET_OPCODE(G_GET_FPMODE) 709HANDLE_TARGET_OPCODE(G_SET_FPMODE) 710HANDLE_TARGET_OPCODE(G_RESET_FPMODE) 711 712/// Generic pointer offset 713HANDLE_TARGET_OPCODE(G_PTR_ADD) 714 715/// Clear the specified bits in a pointer. 716HANDLE_TARGET_OPCODE(G_PTRMASK) 717 718/// Generic signed integer minimum. 719HANDLE_TARGET_OPCODE(G_SMIN) 720 721/// Generic signed integer maximum. 722HANDLE_TARGET_OPCODE(G_SMAX) 723 724/// Generic unsigned integer maximum. 725HANDLE_TARGET_OPCODE(G_UMIN) 726 727/// Generic unsigned integer maximum. 728HANDLE_TARGET_OPCODE(G_UMAX) 729 730/// Generic integer absolute value. 731HANDLE_TARGET_OPCODE(G_ABS) 732 733HANDLE_TARGET_OPCODE(G_LROUND) 734HANDLE_TARGET_OPCODE(G_LLROUND) 735 736/// Generic BRANCH instruction. This is an unconditional branch. 737HANDLE_TARGET_OPCODE(G_BR) 738 739/// Generic branch to jump table entry. 740HANDLE_TARGET_OPCODE(G_BRJT) 741 742/// Generic vscale. 743HANDLE_TARGET_OPCODE(G_VSCALE) 744 745/// Generic insert subvector. 746HANDLE_TARGET_OPCODE(G_INSERT_SUBVECTOR) 747 748/// Generic extract subvector. 749HANDLE_TARGET_OPCODE(G_EXTRACT_SUBVECTOR) 750 751/// Generic insertelement. 752HANDLE_TARGET_OPCODE(G_INSERT_VECTOR_ELT) 753 754/// Generic extractelement. 755HANDLE_TARGET_OPCODE(G_EXTRACT_VECTOR_ELT) 756 757/// Generic shufflevector. 758HANDLE_TARGET_OPCODE(G_SHUFFLE_VECTOR) 759 760/// Generic splatvector. 761HANDLE_TARGET_OPCODE(G_SPLAT_VECTOR) 762 763/// Generic masked compress. 764HANDLE_TARGET_OPCODE(G_VECTOR_COMPRESS) 765 766/// Generic count trailing zeroes. 767HANDLE_TARGET_OPCODE(G_CTTZ) 768 769/// Same as above, undefined for zero inputs. 770HANDLE_TARGET_OPCODE(G_CTTZ_ZERO_UNDEF) 771 772/// Generic count leading zeroes. 773HANDLE_TARGET_OPCODE(G_CTLZ) 774 775/// Same as above, undefined for zero inputs. 776HANDLE_TARGET_OPCODE(G_CTLZ_ZERO_UNDEF) 777 778/// Generic count bits. 779HANDLE_TARGET_OPCODE(G_CTPOP) 780 781/// Generic byte swap. 782HANDLE_TARGET_OPCODE(G_BSWAP) 783 784/// Generic bit reverse. 785HANDLE_TARGET_OPCODE(G_BITREVERSE) 786 787/// Floating point ceil. 788HANDLE_TARGET_OPCODE(G_FCEIL) 789 790/// Floating point cosine. 791HANDLE_TARGET_OPCODE(G_FCOS) 792 793/// Floating point sine. 794HANDLE_TARGET_OPCODE(G_FSIN) 795 796/// Floating point tangent. 797HANDLE_TARGET_OPCODE(G_FTAN) 798 799/// Floating point arccosine. 800HANDLE_TARGET_OPCODE(G_FACOS) 801 802/// Floating point arcsine. 803HANDLE_TARGET_OPCODE(G_FASIN) 804 805/// Floating point arctangent. 806HANDLE_TARGET_OPCODE(G_FATAN) 807 808/// Floating point hyperbolic cosine. 809HANDLE_TARGET_OPCODE(G_FCOSH) 810 811/// Floating point hyperbolic sine. 812HANDLE_TARGET_OPCODE(G_FSINH) 813 814/// Floating point hyperbolic tangent. 815HANDLE_TARGET_OPCODE(G_FTANH) 816 817/// Floating point square root. 818HANDLE_TARGET_OPCODE(G_FSQRT) 819 820/// Floating point floor. 821HANDLE_TARGET_OPCODE(G_FFLOOR) 822 823/// Floating point round to next integer. 824HANDLE_TARGET_OPCODE(G_FRINT) 825 826/// Floating point round to nearest integer. 827HANDLE_TARGET_OPCODE(G_FNEARBYINT) 828 829/// Generic AddressSpaceCast. 830HANDLE_TARGET_OPCODE(G_ADDRSPACE_CAST) 831 832/// Generic block address 833HANDLE_TARGET_OPCODE(G_BLOCK_ADDR) 834 835/// Generic jump table address 836HANDLE_TARGET_OPCODE(G_JUMP_TABLE) 837 838/// Generic dynamic stack allocation. 839HANDLE_TARGET_OPCODE(G_DYN_STACKALLOC) 840 841/// Generic stack pointer save. 842HANDLE_TARGET_OPCODE(G_STACKSAVE) 843 844/// Generic stack pointer restore. 845HANDLE_TARGET_OPCODE(G_STACKRESTORE) 846 847/// Strict floating point instructions. 848HANDLE_TARGET_OPCODE(G_STRICT_FADD) 849HANDLE_TARGET_OPCODE(G_STRICT_FSUB) 850HANDLE_TARGET_OPCODE(G_STRICT_FMUL) 851HANDLE_TARGET_OPCODE(G_STRICT_FDIV) 852HANDLE_TARGET_OPCODE(G_STRICT_FREM) 853HANDLE_TARGET_OPCODE(G_STRICT_FMA) 854HANDLE_TARGET_OPCODE(G_STRICT_FSQRT) 855HANDLE_TARGET_OPCODE(G_STRICT_FLDEXP) 856 857/// read_register intrinsic 858HANDLE_TARGET_OPCODE(G_READ_REGISTER) 859 860/// write_register intrinsic 861HANDLE_TARGET_OPCODE(G_WRITE_REGISTER) 862 863/// llvm.memcpy intrinsic 864HANDLE_TARGET_OPCODE(G_MEMCPY) 865 866/// llvm.memcpy.inline intrinsic 867HANDLE_TARGET_OPCODE(G_MEMCPY_INLINE) 868 869/// llvm.memmove intrinsic 870HANDLE_TARGET_OPCODE(G_MEMMOVE) 871 872/// llvm.memset intrinsic 873HANDLE_TARGET_OPCODE(G_MEMSET) 874HANDLE_TARGET_OPCODE(G_BZERO) 875 876/// llvm.trap, llvm.debugtrap and llvm.ubsantrap intrinsics 877HANDLE_TARGET_OPCODE(G_TRAP) 878HANDLE_TARGET_OPCODE(G_DEBUGTRAP) 879HANDLE_TARGET_OPCODE(G_UBSANTRAP) 880 881/// Vector reductions 882HANDLE_TARGET_OPCODE(G_VECREDUCE_SEQ_FADD) 883HANDLE_TARGET_OPCODE(G_VECREDUCE_SEQ_FMUL) 884HANDLE_TARGET_OPCODE(G_VECREDUCE_FADD) 885HANDLE_TARGET_OPCODE(G_VECREDUCE_FMUL) 886HANDLE_TARGET_OPCODE(G_VECREDUCE_FMAX) 887HANDLE_TARGET_OPCODE(G_VECREDUCE_FMIN) 888HANDLE_TARGET_OPCODE(G_VECREDUCE_FMAXIMUM) 889HANDLE_TARGET_OPCODE(G_VECREDUCE_FMINIMUM) 890HANDLE_TARGET_OPCODE(G_VECREDUCE_ADD) 891HANDLE_TARGET_OPCODE(G_VECREDUCE_MUL) 892HANDLE_TARGET_OPCODE(G_VECREDUCE_AND) 893HANDLE_TARGET_OPCODE(G_VECREDUCE_OR) 894HANDLE_TARGET_OPCODE(G_VECREDUCE_XOR) 895HANDLE_TARGET_OPCODE(G_VECREDUCE_SMAX) 896HANDLE_TARGET_OPCODE(G_VECREDUCE_SMIN) 897HANDLE_TARGET_OPCODE(G_VECREDUCE_UMAX) 898HANDLE_TARGET_OPCODE(G_VECREDUCE_UMIN) 899 900HANDLE_TARGET_OPCODE(G_SBFX) 901HANDLE_TARGET_OPCODE(G_UBFX) 902 903/// Marker for the end of the generic opcode. 904/// This is used to check if an opcode is in the range of the 905/// generic opcodes. 906HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_END, G_UBFX) 907 908/// BUILTIN_OP_END - This must be the last enum value in this list. 909/// The target-specific post-isel opcode values start here. 910HANDLE_TARGET_OPCODE_MARKER(GENERIC_OP_END, PRE_ISEL_GENERIC_OPCODE_END) 911