1//===-- IR/VPIntrinsics.def - Describes llvm.vp.* Intrinsics -*- C++ -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file contains descriptions of the various Vector Predication intrinsics. 10// This is used as a central place for enumerating the different instructions 11// and should eventually be the place to put comments about the instructions. 12// 13//===----------------------------------------------------------------------===// 14 15// NOTE: NO INCLUDE GUARD DESIRED! 16 17// Provide definitions of macros so that users of this file do not have to 18// define everything to use it... 19// 20// Register a VP intrinsic and begin its property scope. 21// All VP intrinsic scopes are top level, ie it is illegal to place a 22// BEGIN_REGISTER_VP_INTRINSIC within a VP intrinsic scope. 23// \p VPID The VP intrinsic id. 24// \p MASKPOS The mask operand position. 25// \p EVLPOS The explicit vector length operand position. 26#ifndef BEGIN_REGISTER_VP_INTRINSIC 27#define BEGIN_REGISTER_VP_INTRINSIC(VPID, MASKPOS, EVLPOS) 28#endif 29 30// End the property scope of a VP intrinsic. 31#ifndef END_REGISTER_VP_INTRINSIC 32#define END_REGISTER_VP_INTRINSIC(VPID) 33#endif 34 35// Register a new VP SDNode and begin its property scope. 36// When the SDNode scope is nested within a VP intrinsic scope, it is 37// implicitly registered as the canonical SDNode for this VP intrinsic. There 38// is one VP intrinsic that maps directly to one SDNode that goes by the 39// same name. Since the operands are also the same, we open the property 40// scopes for both the VPIntrinsic and the SDNode at once. 41// \p VPSD The SelectionDAG Node id (eg VP_ADD). 42// \p LEGALPOS The operand position of the SDNode that is used for legalizing. 43// If LEGALPOS < 0, then the return type given by 44// TheNode->getValueType(-1-LEGALPOS) is used. 45// \p TDNAME The name of the TableGen definition of this SDNode. 46// \p MASKPOS The mask operand position. 47// \p EVLPOS The explicit vector length operand position. 48#ifndef BEGIN_REGISTER_VP_SDNODE 49#define BEGIN_REGISTER_VP_SDNODE(VPSD, LEGALPOS, TDNAME, MASKPOS, EVLPOS) 50#endif 51 52// End the property scope of a new VP SDNode. 53#ifndef END_REGISTER_VP_SDNODE 54#define END_REGISTER_VP_SDNODE(VPSD) 55#endif 56 57// Helper macro to set up the mapping from VP intrinsic to ISD opcode. 58// Note: More than one VP intrinsic may map to one ISD opcode. 59#ifndef HELPER_MAP_VPID_TO_VPSD 60#define HELPER_MAP_VPID_TO_VPSD(VPID, VPSD) 61#endif 62 63// Helper macros for the common "1:1 - Intrinsic : SDNode" case. 64// 65// There is one VP intrinsic that maps directly to one SDNode that goes by the 66// same name. Since the operands are also the same, we open the property 67// scopes for both the VPIntrinsic and the SDNode at once. 68// 69// \p VPID The canonical name (eg `vp_add`, which at the same time is the 70// name of the intrinsic and the TableGen def of the SDNode). 71// \p MASKPOS The mask operand position. 72// \p EVLPOS The explicit vector length operand position. 73// \p VPSD The SelectionDAG Node id (eg VP_ADD). 74// \p LEGALPOS The operand position of the SDNode that is used for legalizing 75// this SDNode. This can be `-1`, in which case the return type of 76// the SDNode is used. 77#define BEGIN_REGISTER_VP(VPID, MASKPOS, EVLPOS, VPSD, LEGALPOS) \ 78 BEGIN_REGISTER_VP_INTRINSIC(VPID, MASKPOS, EVLPOS) \ 79 BEGIN_REGISTER_VP_SDNODE(VPSD, LEGALPOS, VPID, MASKPOS, EVLPOS) \ 80 HELPER_MAP_VPID_TO_VPSD(VPID, VPSD) 81 82#define END_REGISTER_VP(VPID, VPSD) \ 83 END_REGISTER_VP_INTRINSIC(VPID) \ 84 END_REGISTER_VP_SDNODE(VPSD) 85 86// The following macros attach properties to the scope they are placed in. This 87// assigns the property to the VP Intrinsic and/or SDNode that belongs to the 88// scope. 89// 90// Property Macros { 91 92// The intrinsic and/or SDNode has the same function as this LLVM IR Opcode. 93// \p OPC The opcode of the instruction with the same function. 94#ifndef VP_PROPERTY_FUNCTIONAL_OPC 95#define VP_PROPERTY_FUNCTIONAL_OPC(OPC) 96#endif 97 98// Whether the intrinsic may have a rounding mode or exception behavior operand 99// bundle. 100// \p HASROUND '1' if the intrinsic can have a rounding mode operand bundle, 101// '0' otherwise. 102// \p HASEXCEPT '1' if the intrinsic can have an exception behavior operand 103// bundle, '0' otherwise. 104// \p INTRINID The constrained fp intrinsic this VP intrinsic corresponds to. 105#ifndef VP_PROPERTY_CONSTRAINEDFP 106#define VP_PROPERTY_CONSTRAINEDFP(HASROUND, HASEXCEPT, INTRINID) 107#endif 108 109// The intrinsic and/or SDNode has the same function as this ISD Opcode. 110// \p SDOPC The opcode of the instruction with the same function. 111#ifndef VP_PROPERTY_FUNCTIONAL_SDOPC 112#define VP_PROPERTY_FUNCTIONAL_SDOPC(SDOPC) 113#endif 114 115// Map this VP intrinsic to its canonical functional intrinsic. 116// \p INTRIN The non-VP intrinsics with the same function. 117#ifndef VP_PROPERTY_FUNCTIONAL_INTRINSIC 118#define VP_PROPERTY_FUNCTIONAL_INTRINSIC(INTRIN) 119#endif 120 121// This VP Intrinsic has no functionally-equivalent non-VP opcode or intrinsic. 122#ifndef VP_PROPERTY_NO_FUNCTIONAL 123#define VP_PROPERTY_NO_FUNCTIONAL 124#endif 125 126// This VP Intrinsic is a memory operation 127// The pointer arg is at POINTERPOS and the data arg is at DATAPOS. 128#ifndef VP_PROPERTY_MEMOP 129#define VP_PROPERTY_MEMOP(POINTERPOS, DATAPOS) 130#endif 131 132// Map this VP reduction intrinsic to its reduction operand positions. 133#ifndef VP_PROPERTY_REDUCTION 134#define VP_PROPERTY_REDUCTION(STARTPOS, VECTORPOS) 135#endif 136 137// A property to infer VP binary-op SDNode opcodes automatically. 138#ifndef VP_PROPERTY_BINARYOP 139#define VP_PROPERTY_BINARYOP 140#endif 141 142// A property to infer VP type casts automatically. 143#ifndef VP_PROPERTY_CASTOP 144#define VP_PROPERTY_CASTOP 145#endif 146 147// This VP Intrinsic is a comparison operation 148// The condition code arg is at CCPOS and accepts floating-point condition 149// codes if ISFP is set, else it accepts integer condition codes. 150#ifndef VP_PROPERTY_CMP 151#define VP_PROPERTY_CMP(CCPOS, ISFP) 152#endif 153 154/// } Property Macros 155 156///// Integer Arithmetic { 157 158// Specialized helper macro for integer binary operators (%x, %y, %mask, %evl). 159#ifdef HELPER_REGISTER_BINARY_INT_VP 160#error \ 161 "The internal helper macro HELPER_REGISTER_BINARY_INT_VP is already defined!" 162#endif 163#define HELPER_REGISTER_BINARY_INT_VP(VPID, VPSD, IROPC, SDOPC) \ 164 BEGIN_REGISTER_VP(VPID, 2, 3, VPSD, -1) \ 165 VP_PROPERTY_FUNCTIONAL_OPC(IROPC) \ 166 VP_PROPERTY_FUNCTIONAL_SDOPC(SDOPC) \ 167 VP_PROPERTY_BINARYOP \ 168 END_REGISTER_VP(VPID, VPSD) 169 170// llvm.vp.add(x,y,mask,vlen) 171HELPER_REGISTER_BINARY_INT_VP(vp_add, VP_ADD, Add, ADD) 172 173// llvm.vp.and(x,y,mask,vlen) 174HELPER_REGISTER_BINARY_INT_VP(vp_and, VP_AND, And, AND) 175 176// llvm.vp.ashr(x,y,mask,vlen) 177HELPER_REGISTER_BINARY_INT_VP(vp_ashr, VP_SRA, AShr, SRA) 178 179// llvm.vp.lshr(x,y,mask,vlen) 180HELPER_REGISTER_BINARY_INT_VP(vp_lshr, VP_SRL, LShr, SRL) 181 182// llvm.vp.mul(x,y,mask,vlen) 183HELPER_REGISTER_BINARY_INT_VP(vp_mul, VP_MUL, Mul, MUL) 184 185// llvm.vp.or(x,y,mask,vlen) 186HELPER_REGISTER_BINARY_INT_VP(vp_or, VP_OR, Or, OR) 187 188// llvm.vp.sdiv(x,y,mask,vlen) 189HELPER_REGISTER_BINARY_INT_VP(vp_sdiv, VP_SDIV, SDiv, SDIV) 190 191// llvm.vp.shl(x,y,mask,vlen) 192HELPER_REGISTER_BINARY_INT_VP(vp_shl, VP_SHL, Shl, SHL) 193 194// llvm.vp.srem(x,y,mask,vlen) 195HELPER_REGISTER_BINARY_INT_VP(vp_srem, VP_SREM, SRem, SREM) 196 197// llvm.vp.sub(x,y,mask,vlen) 198HELPER_REGISTER_BINARY_INT_VP(vp_sub, VP_SUB, Sub, SUB) 199 200// llvm.vp.udiv(x,y,mask,vlen) 201HELPER_REGISTER_BINARY_INT_VP(vp_udiv, VP_UDIV, UDiv, UDIV) 202 203// llvm.vp.urem(x,y,mask,vlen) 204HELPER_REGISTER_BINARY_INT_VP(vp_urem, VP_UREM, URem, UREM) 205 206// llvm.vp.xor(x,y,mask,vlen) 207HELPER_REGISTER_BINARY_INT_VP(vp_xor, VP_XOR, Xor, XOR) 208 209#undef HELPER_REGISTER_BINARY_INT_VP 210 211// llvm.vp.smin(x,y,mask,vlen) 212BEGIN_REGISTER_VP(vp_smin, 2, 3, VP_SMIN, -1) 213VP_PROPERTY_BINARYOP 214VP_PROPERTY_FUNCTIONAL_SDOPC(SMIN) 215VP_PROPERTY_FUNCTIONAL_INTRINSIC(smin) 216END_REGISTER_VP(vp_smin, VP_SMIN) 217 218// llvm.vp.smax(x,y,mask,vlen) 219BEGIN_REGISTER_VP(vp_smax, 2, 3, VP_SMAX, -1) 220VP_PROPERTY_BINARYOP 221VP_PROPERTY_FUNCTIONAL_SDOPC(SMAX) 222VP_PROPERTY_FUNCTIONAL_INTRINSIC(smax) 223END_REGISTER_VP(vp_smax, VP_SMAX) 224 225// llvm.vp.umin(x,y,mask,vlen) 226BEGIN_REGISTER_VP(vp_umin, 2, 3, VP_UMIN, -1) 227VP_PROPERTY_BINARYOP 228VP_PROPERTY_FUNCTIONAL_SDOPC(UMIN) 229VP_PROPERTY_FUNCTIONAL_INTRINSIC(umin) 230END_REGISTER_VP(vp_umin, VP_UMIN) 231 232// llvm.vp.umax(x,y,mask,vlen) 233BEGIN_REGISTER_VP(vp_umax, 2, 3, VP_UMAX, -1) 234VP_PROPERTY_BINARYOP 235VP_PROPERTY_FUNCTIONAL_SDOPC(UMAX) 236VP_PROPERTY_FUNCTIONAL_INTRINSIC(umax) 237END_REGISTER_VP(vp_umax, VP_UMAX) 238 239// llvm.vp.abs(x,is_int_min_poison,mask,vlen) 240BEGIN_REGISTER_VP_INTRINSIC(vp_abs, 2, 3) 241BEGIN_REGISTER_VP_SDNODE(VP_ABS, -1, vp_abs, 1, 2) 242HELPER_MAP_VPID_TO_VPSD(vp_abs, VP_ABS) 243VP_PROPERTY_FUNCTIONAL_INTRINSIC(abs) 244VP_PROPERTY_FUNCTIONAL_SDOPC(ABS) 245END_REGISTER_VP(vp_abs, VP_ABS) 246 247// llvm.vp.bswap(x,mask,vlen) 248BEGIN_REGISTER_VP(vp_bswap, 1, 2, VP_BSWAP, -1) 249VP_PROPERTY_FUNCTIONAL_INTRINSIC(bswap) 250VP_PROPERTY_FUNCTIONAL_SDOPC(BSWAP) 251END_REGISTER_VP(vp_bswap, VP_BSWAP) 252 253// llvm.vp.bitreverse(x,mask,vlen) 254BEGIN_REGISTER_VP(vp_bitreverse, 1, 2, VP_BITREVERSE, -1) 255VP_PROPERTY_FUNCTIONAL_INTRINSIC(bitreverse) 256VP_PROPERTY_FUNCTIONAL_SDOPC(BITREVERSE) 257END_REGISTER_VP(vp_bitreverse, VP_BITREVERSE) 258 259// llvm.vp.ctpop(x,mask,vlen) 260BEGIN_REGISTER_VP(vp_ctpop, 1, 2, VP_CTPOP, -1) 261VP_PROPERTY_FUNCTIONAL_INTRINSIC(ctpop) 262VP_PROPERTY_FUNCTIONAL_SDOPC(CTPOP) 263END_REGISTER_VP(vp_ctpop, VP_CTPOP) 264 265// llvm.vp.ctlz(x,is_zero_poison,mask,vlen) 266BEGIN_REGISTER_VP_INTRINSIC(vp_ctlz, 2, 3) 267BEGIN_REGISTER_VP_SDNODE(VP_CTLZ, -1, vp_ctlz, 1, 2) 268VP_PROPERTY_FUNCTIONAL_INTRINSIC(ctlz) 269VP_PROPERTY_FUNCTIONAL_SDOPC(CTLZ) 270END_REGISTER_VP_SDNODE(VP_CTLZ) 271BEGIN_REGISTER_VP_SDNODE(VP_CTLZ_ZERO_UNDEF, -1, vp_ctlz_zero_undef, 1, 2) 272END_REGISTER_VP_SDNODE(VP_CTLZ_ZERO_UNDEF) 273END_REGISTER_VP_INTRINSIC(vp_ctlz) 274 275// llvm.vp.cttz(x,is_zero_poison,mask,vlen) 276BEGIN_REGISTER_VP_INTRINSIC(vp_cttz, 2, 3) 277BEGIN_REGISTER_VP_SDNODE(VP_CTTZ, -1, vp_cttz, 1, 2) 278VP_PROPERTY_FUNCTIONAL_INTRINSIC(cttz) 279VP_PROPERTY_FUNCTIONAL_SDOPC(CTTZ) 280END_REGISTER_VP_SDNODE(VP_CTTZ) 281BEGIN_REGISTER_VP_SDNODE(VP_CTTZ_ZERO_UNDEF, -1, vp_cttz_zero_undef, 1, 2) 282END_REGISTER_VP_SDNODE(VP_CTTZ_ZERO_UNDEF) 283END_REGISTER_VP_INTRINSIC(vp_cttz) 284 285// llvm.vp.cttz.elts(x,is_zero_poison,mask,vl) 286BEGIN_REGISTER_VP_INTRINSIC(vp_cttz_elts, 2, 3) 287VP_PROPERTY_NO_FUNCTIONAL 288BEGIN_REGISTER_VP_SDNODE(VP_CTTZ_ELTS, 0, vp_cttz_elts, 1, 2) 289END_REGISTER_VP_SDNODE(VP_CTTZ_ELTS) 290BEGIN_REGISTER_VP_SDNODE(VP_CTTZ_ELTS_ZERO_UNDEF, 0, vp_cttz_elts_zero_undef, 1, 2) 291END_REGISTER_VP_SDNODE(VP_CTTZ_ELTS_ZERO_UNDEF) 292END_REGISTER_VP_INTRINSIC(vp_cttz_elts) 293 294// llvm.vp.fshl(x,y,z,mask,vlen) 295BEGIN_REGISTER_VP(vp_fshl, 3, 4, VP_FSHL, -1) 296VP_PROPERTY_FUNCTIONAL_INTRINSIC(fshl) 297VP_PROPERTY_FUNCTIONAL_SDOPC(FSHL) 298END_REGISTER_VP(vp_fshl, VP_FSHL) 299 300// llvm.vp.fshr(x,y,z,mask,vlen) 301BEGIN_REGISTER_VP(vp_fshr, 3, 4, VP_FSHR, -1) 302VP_PROPERTY_FUNCTIONAL_INTRINSIC(fshr) 303VP_PROPERTY_FUNCTIONAL_SDOPC(FSHR) 304END_REGISTER_VP(vp_fshr, VP_FSHR) 305 306// llvm.vp.sadd.sat(x,y,mask,vlen) 307BEGIN_REGISTER_VP(vp_sadd_sat, 2, 3, VP_SADDSAT, -1) 308VP_PROPERTY_FUNCTIONAL_INTRINSIC(sadd_sat) 309VP_PROPERTY_FUNCTIONAL_SDOPC(SADDSAT) 310END_REGISTER_VP(vp_sadd_sat, VP_SADDSAT) 311 312// llvm.vp.uadd.sat(x,y,mask,vlen) 313BEGIN_REGISTER_VP(vp_uadd_sat, 2, 3, VP_UADDSAT, -1) 314VP_PROPERTY_FUNCTIONAL_INTRINSIC(uadd_sat) 315VP_PROPERTY_FUNCTIONAL_SDOPC(UADDSAT) 316END_REGISTER_VP(vp_uadd_sat, VP_UADDSAT) 317 318// llvm.vp.ssub.sat(x,y,mask,vlen) 319BEGIN_REGISTER_VP(vp_ssub_sat, 2, 3, VP_SSUBSAT, -1) 320VP_PROPERTY_FUNCTIONAL_INTRINSIC(ssub_sat) 321VP_PROPERTY_FUNCTIONAL_SDOPC(SSUBSAT) 322END_REGISTER_VP(vp_ssub_sat, VP_SSUBSAT) 323 324// llvm.vp.usub.sat(x,y,mask,vlen) 325BEGIN_REGISTER_VP(vp_usub_sat, 2, 3, VP_USUBSAT, -1) 326VP_PROPERTY_FUNCTIONAL_INTRINSIC(usub_sat) 327VP_PROPERTY_FUNCTIONAL_SDOPC(USUBSAT) 328END_REGISTER_VP(vp_usub_sat, VP_USUBSAT) 329///// } Integer Arithmetic 330 331///// Floating-Point Arithmetic { 332 333// Specialized helper macro for floating-point binary operators 334// <operation>(%x, %y, %mask, %evl). 335#ifdef HELPER_REGISTER_BINARY_FP_VP 336#error \ 337 "The internal helper macro HELPER_REGISTER_BINARY_FP_VP is already defined!" 338#endif 339#define HELPER_REGISTER_BINARY_FP_VP(OPSUFFIX, VPSD, IROPC, SDOPC) \ 340 BEGIN_REGISTER_VP(vp_##OPSUFFIX, 2, 3, VPSD, -1) \ 341 VP_PROPERTY_FUNCTIONAL_OPC(IROPC) \ 342 VP_PROPERTY_CONSTRAINEDFP(1, 1, experimental_constrained_##OPSUFFIX) \ 343 VP_PROPERTY_FUNCTIONAL_SDOPC(SDOPC) \ 344 VP_PROPERTY_BINARYOP \ 345 END_REGISTER_VP(vp_##OPSUFFIX, VPSD) 346 347// llvm.vp.fadd(x,y,mask,vlen) 348HELPER_REGISTER_BINARY_FP_VP(fadd, VP_FADD, FAdd, FADD) 349 350// llvm.vp.fsub(x,y,mask,vlen) 351HELPER_REGISTER_BINARY_FP_VP(fsub, VP_FSUB, FSub, FSUB) 352 353// llvm.vp.fmul(x,y,mask,vlen) 354HELPER_REGISTER_BINARY_FP_VP(fmul, VP_FMUL, FMul, FMUL) 355 356// llvm.vp.fdiv(x,y,mask,vlen) 357HELPER_REGISTER_BINARY_FP_VP(fdiv, VP_FDIV, FDiv, FDIV) 358 359// llvm.vp.frem(x,y,mask,vlen) 360HELPER_REGISTER_BINARY_FP_VP(frem, VP_FREM, FRem, FREM) 361 362#undef HELPER_REGISTER_BINARY_FP_VP 363 364// llvm.vp.fneg(x,mask,vlen) 365BEGIN_REGISTER_VP(vp_fneg, 1, 2, VP_FNEG, -1) 366VP_PROPERTY_FUNCTIONAL_OPC(FNeg) 367VP_PROPERTY_FUNCTIONAL_SDOPC(FNEG) 368END_REGISTER_VP(vp_fneg, VP_FNEG) 369 370// llvm.vp.fabs(x,mask,vlen) 371BEGIN_REGISTER_VP(vp_fabs, 1, 2, VP_FABS, -1) 372VP_PROPERTY_FUNCTIONAL_INTRINSIC(fabs) 373VP_PROPERTY_FUNCTIONAL_SDOPC(FABS) 374END_REGISTER_VP(vp_fabs, VP_FABS) 375 376// llvm.vp.sqrt(x,mask,vlen) 377BEGIN_REGISTER_VP(vp_sqrt, 1, 2, VP_SQRT, -1) 378VP_PROPERTY_FUNCTIONAL_INTRINSIC(sqrt) 379VP_PROPERTY_FUNCTIONAL_SDOPC(FSQRT) 380END_REGISTER_VP(vp_sqrt, VP_SQRT) 381 382// llvm.vp.fma(x,y,z,mask,vlen) 383BEGIN_REGISTER_VP(vp_fma, 3, 4, VP_FMA, -1) 384VP_PROPERTY_CONSTRAINEDFP(1, 1, experimental_constrained_fma) 385VP_PROPERTY_FUNCTIONAL_INTRINSIC(fma) 386VP_PROPERTY_FUNCTIONAL_SDOPC(FMA) 387END_REGISTER_VP(vp_fma, VP_FMA) 388 389// llvm.vp.fmuladd(x,y,z,mask,vlen) 390BEGIN_REGISTER_VP(vp_fmuladd, 3, 4, VP_FMULADD, -1) 391VP_PROPERTY_CONSTRAINEDFP(1, 1, experimental_constrained_fmuladd) 392VP_PROPERTY_FUNCTIONAL_INTRINSIC(fmuladd) 393VP_PROPERTY_FUNCTIONAL_SDOPC(FMAD) 394END_REGISTER_VP(vp_fmuladd, VP_FMULADD) 395 396// llvm.vp.copysign(x,y,mask,vlen) 397BEGIN_REGISTER_VP(vp_copysign, 2, 3, VP_FCOPYSIGN, -1) 398VP_PROPERTY_BINARYOP 399VP_PROPERTY_FUNCTIONAL_SDOPC(FCOPYSIGN) 400VP_PROPERTY_FUNCTIONAL_INTRINSIC(copysign) 401END_REGISTER_VP(vp_copysign, VP_FCOPYSIGN) 402 403// llvm.vp.minnum(x,y,mask,vlen) 404BEGIN_REGISTER_VP(vp_minnum, 2, 3, VP_FMINNUM, -1) 405VP_PROPERTY_BINARYOP 406VP_PROPERTY_FUNCTIONAL_SDOPC(FMINNUM) 407VP_PROPERTY_FUNCTIONAL_INTRINSIC(minnum) 408END_REGISTER_VP(vp_minnum, VP_FMINNUM) 409 410// llvm.vp.maxnum(x,y,mask,vlen) 411BEGIN_REGISTER_VP(vp_maxnum, 2, 3, VP_FMAXNUM, -1) 412VP_PROPERTY_BINARYOP 413VP_PROPERTY_FUNCTIONAL_SDOPC(FMAXNUM) 414VP_PROPERTY_FUNCTIONAL_INTRINSIC(maxnum) 415END_REGISTER_VP(vp_maxnum, VP_FMAXNUM) 416 417// llvm.vp.minimum(x,y,mask,vlen) 418BEGIN_REGISTER_VP(vp_minimum, 2, 3, VP_FMINIMUM, -1) 419VP_PROPERTY_BINARYOP 420VP_PROPERTY_FUNCTIONAL_SDOPC(FMINIMUM) 421VP_PROPERTY_FUNCTIONAL_INTRINSIC(minimum) 422END_REGISTER_VP(vp_minimum, VP_FMINIMUM) 423 424// llvm.vp.maximum(x,y,mask,vlen) 425BEGIN_REGISTER_VP(vp_maximum, 2, 3, VP_FMAXIMUM, -1) 426VP_PROPERTY_BINARYOP 427VP_PROPERTY_FUNCTIONAL_SDOPC(FMAXIMUM) 428VP_PROPERTY_FUNCTIONAL_INTRINSIC(maximum) 429END_REGISTER_VP(vp_maximum, VP_FMAXIMUM) 430 431// llvm.vp.ceil(x,mask,vlen) 432BEGIN_REGISTER_VP(vp_ceil, 1, 2, VP_FCEIL, -1) 433VP_PROPERTY_FUNCTIONAL_INTRINSIC(ceil) 434VP_PROPERTY_FUNCTIONAL_SDOPC(FCEIL) 435END_REGISTER_VP(vp_ceil, VP_FCEIL) 436 437// llvm.vp.floor(x,mask,vlen) 438BEGIN_REGISTER_VP(vp_floor, 1, 2, VP_FFLOOR, -1) 439VP_PROPERTY_FUNCTIONAL_INTRINSIC(floor) 440VP_PROPERTY_FUNCTIONAL_SDOPC(FFLOOR) 441END_REGISTER_VP(vp_floor, VP_FFLOOR) 442 443// llvm.vp.round(x,mask,vlen) 444BEGIN_REGISTER_VP(vp_round, 1, 2, VP_FROUND, -1) 445VP_PROPERTY_FUNCTIONAL_INTRINSIC(round) 446VP_PROPERTY_FUNCTIONAL_SDOPC(FROUND) 447END_REGISTER_VP(vp_round, VP_FROUND) 448 449// llvm.vp.roundeven(x,mask,vlen) 450BEGIN_REGISTER_VP(vp_roundeven, 1, 2, VP_FROUNDEVEN, -1) 451VP_PROPERTY_FUNCTIONAL_INTRINSIC(roundeven) 452VP_PROPERTY_FUNCTIONAL_SDOPC(FROUNDEVEN) 453END_REGISTER_VP(vp_roundeven, VP_FROUNDEVEN) 454 455// llvm.vp.roundtozero(x,mask,vlen) 456BEGIN_REGISTER_VP(vp_roundtozero, 1, 2, VP_FROUNDTOZERO, -1) 457VP_PROPERTY_FUNCTIONAL_INTRINSIC(trunc) 458VP_PROPERTY_FUNCTIONAL_SDOPC(FTRUNC) 459END_REGISTER_VP(vp_roundtozero, VP_FROUNDTOZERO) 460 461// llvm.vp.rint(x,mask,vlen) 462BEGIN_REGISTER_VP(vp_rint, 1, 2, VP_FRINT, -1) 463VP_PROPERTY_FUNCTIONAL_INTRINSIC(rint) 464VP_PROPERTY_FUNCTIONAL_SDOPC(FRINT) 465END_REGISTER_VP(vp_rint, VP_FRINT) 466 467// llvm.vp.nearbyint(x,mask,vlen) 468BEGIN_REGISTER_VP(vp_nearbyint, 1, 2, VP_FNEARBYINT, -1) 469VP_PROPERTY_FUNCTIONAL_INTRINSIC(nearbyint) 470VP_PROPERTY_FUNCTIONAL_SDOPC(FNEARBYINT) 471END_REGISTER_VP(vp_nearbyint, VP_FNEARBYINT) 472 473// llvm.vp.lrint(x,mask,vlen) 474BEGIN_REGISTER_VP(vp_lrint, 1, 2, VP_LRINT, 0) 475VP_PROPERTY_FUNCTIONAL_INTRINSIC(lrint) 476VP_PROPERTY_FUNCTIONAL_SDOPC(LRINT) 477END_REGISTER_VP(vp_lrint, VP_LRINT) 478 479// llvm.vp.llrint(x,mask,vlen) 480BEGIN_REGISTER_VP(vp_llrint, 1, 2, VP_LLRINT, 0) 481VP_PROPERTY_FUNCTIONAL_INTRINSIC(llrint) 482VP_PROPERTY_FUNCTIONAL_SDOPC(LLRINT) 483END_REGISTER_VP(vp_llrint, VP_LLRINT) 484 485///// } Floating-Point Arithmetic 486 487///// Type Casts { 488// Specialized helper macro for type conversions. 489// <operation>(%x, %mask, %evl). 490#ifdef HELPER_REGISTER_FP_CAST_VP 491#error \ 492 "The internal helper macro HELPER_REGISTER_FP_CAST_VP is already defined!" 493#endif 494#define HELPER_REGISTER_FP_CAST_VP(OPSUFFIX, VPSD, IROPC, SDOPC, HASROUND) \ 495 BEGIN_REGISTER_VP(vp_##OPSUFFIX, 1, 2, VPSD, -1) \ 496 VP_PROPERTY_FUNCTIONAL_OPC(IROPC) \ 497 VP_PROPERTY_FUNCTIONAL_SDOPC(SDOPC) \ 498 VP_PROPERTY_CONSTRAINEDFP(HASROUND, 1, experimental_constrained_##OPSUFFIX) \ 499 VP_PROPERTY_CASTOP \ 500 END_REGISTER_VP(vp_##OPSUFFIX, VPSD) 501 502// llvm.vp.fptoui(x,mask,vlen) 503HELPER_REGISTER_FP_CAST_VP(fptoui, VP_FP_TO_UINT, FPToUI, FP_TO_UINT, 0) 504 505// llvm.vp.fptosi(x,mask,vlen) 506HELPER_REGISTER_FP_CAST_VP(fptosi, VP_FP_TO_SINT, FPToSI, FP_TO_SINT, 0) 507 508// llvm.vp.uitofp(x,mask,vlen) 509HELPER_REGISTER_FP_CAST_VP(uitofp, VP_UINT_TO_FP, UIToFP, UINT_TO_FP, 1) 510 511// llvm.vp.sitofp(x,mask,vlen) 512HELPER_REGISTER_FP_CAST_VP(sitofp, VP_SINT_TO_FP, SIToFP, SINT_TO_FP, 1) 513 514// llvm.vp.fptrunc(x,mask,vlen) 515HELPER_REGISTER_FP_CAST_VP(fptrunc, VP_FP_ROUND, FPTrunc, FP_ROUND, 1) 516 517// llvm.vp.fpext(x,mask,vlen) 518HELPER_REGISTER_FP_CAST_VP(fpext, VP_FP_EXTEND, FPExt, FP_EXTEND, 0) 519 520#undef HELPER_REGISTER_FP_CAST_VP 521 522// Specialized helper macro for integer type conversions. 523// <operation>(%x, %mask, %evl). 524#ifdef HELPER_REGISTER_INT_CAST_VP 525#error \ 526 "The internal helper macro HELPER_REGISTER_INT_CAST_VP is already defined!" 527#endif 528#define HELPER_REGISTER_INT_CAST_VP(OPSUFFIX, VPSD, IROPC, SDOPC) \ 529 BEGIN_REGISTER_VP(vp_##OPSUFFIX, 1, 2, VPSD, -1) \ 530 VP_PROPERTY_FUNCTIONAL_OPC(IROPC) \ 531 VP_PROPERTY_FUNCTIONAL_SDOPC(SDOPC) \ 532 VP_PROPERTY_CASTOP \ 533 END_REGISTER_VP(vp_##OPSUFFIX, VPSD) 534 535// llvm.vp.trunc(x,mask,vlen) 536HELPER_REGISTER_INT_CAST_VP(trunc, VP_TRUNCATE, Trunc, TRUNCATE) 537 538// llvm.vp.zext(x,mask,vlen) 539HELPER_REGISTER_INT_CAST_VP(zext, VP_ZERO_EXTEND, ZExt, ZERO_EXTEND) 540 541// llvm.vp.sext(x,mask,vlen) 542HELPER_REGISTER_INT_CAST_VP(sext, VP_SIGN_EXTEND, SExt, SIGN_EXTEND) 543 544// llvm.vp.ptrtoint(x,mask,vlen) 545BEGIN_REGISTER_VP(vp_ptrtoint, 1, 2, VP_PTRTOINT, -1) 546VP_PROPERTY_FUNCTIONAL_OPC(PtrToInt) 547VP_PROPERTY_CASTOP 548END_REGISTER_VP(vp_ptrtoint, VP_PTRTOINT) 549 550// llvm.vp.inttoptr(x,mask,vlen) 551BEGIN_REGISTER_VP(vp_inttoptr, 1, 2, VP_INTTOPTR, -1) 552VP_PROPERTY_FUNCTIONAL_OPC(IntToPtr) 553VP_PROPERTY_CASTOP 554END_REGISTER_VP(vp_inttoptr, VP_INTTOPTR) 555 556#undef HELPER_REGISTER_INT_CAST_VP 557 558///// } Type Casts 559 560///// Comparisons { 561 562// VP_SETCC (ISel only) 563BEGIN_REGISTER_VP_SDNODE(VP_SETCC, 0, vp_setcc, 3, 4) 564END_REGISTER_VP_SDNODE(VP_SETCC) 565 566// llvm.vp.fcmp(x,y,cc,mask,vlen) 567BEGIN_REGISTER_VP_INTRINSIC(vp_fcmp, 3, 4) 568HELPER_MAP_VPID_TO_VPSD(vp_fcmp, VP_SETCC) 569VP_PROPERTY_FUNCTIONAL_OPC(FCmp) 570VP_PROPERTY_CMP(2, true) 571VP_PROPERTY_CONSTRAINEDFP(0, 1, experimental_constrained_fcmp) 572END_REGISTER_VP_INTRINSIC(vp_fcmp) 573 574// llvm.vp.icmp(x,y,cc,mask,vlen) 575BEGIN_REGISTER_VP_INTRINSIC(vp_icmp, 3, 4) 576HELPER_MAP_VPID_TO_VPSD(vp_icmp, VP_SETCC) 577VP_PROPERTY_FUNCTIONAL_OPC(ICmp) 578VP_PROPERTY_CMP(2, false) 579END_REGISTER_VP_INTRINSIC(vp_icmp) 580 581///// } Comparisons 582 583// llvm.vp.is.fpclass(on_true,on_false,mask,vlen) 584BEGIN_REGISTER_VP(vp_is_fpclass, 2, 3, VP_IS_FPCLASS, 0) 585VP_PROPERTY_FUNCTIONAL_INTRINSIC(is_fpclass) 586END_REGISTER_VP(vp_is_fpclass, VP_IS_FPCLASS) 587 588///// Memory Operations { 589// llvm.vp.store(val,ptr,mask,vlen) 590BEGIN_REGISTER_VP_INTRINSIC(vp_store, 2, 3) 591// chain = VP_STORE chain,val,base,offset,mask,evl 592BEGIN_REGISTER_VP_SDNODE(VP_STORE, 1, vp_store, 4, 5) 593HELPER_MAP_VPID_TO_VPSD(vp_store, VP_STORE) 594VP_PROPERTY_FUNCTIONAL_OPC(Store) 595VP_PROPERTY_FUNCTIONAL_INTRINSIC(masked_store) 596VP_PROPERTY_MEMOP(1, 0) 597END_REGISTER_VP(vp_store, VP_STORE) 598 599// llvm.experimental.vp.strided.store(val,ptr,stride,mask,vlen) 600BEGIN_REGISTER_VP_INTRINSIC(experimental_vp_strided_store, 3, 4) 601// chain = EXPERIMENTAL_VP_STRIDED_STORE chain,val,base,offset,stride,mask,evl 602VP_PROPERTY_NO_FUNCTIONAL 603BEGIN_REGISTER_VP_SDNODE(EXPERIMENTAL_VP_STRIDED_STORE, 1, experimental_vp_strided_store, 5, 6) 604HELPER_MAP_VPID_TO_VPSD(experimental_vp_strided_store, EXPERIMENTAL_VP_STRIDED_STORE) 605VP_PROPERTY_MEMOP(1, 0) 606END_REGISTER_VP(experimental_vp_strided_store, EXPERIMENTAL_VP_STRIDED_STORE) 607 608// llvm.vp.scatter(ptr,val,mask,vlen) 609BEGIN_REGISTER_VP_INTRINSIC(vp_scatter, 2, 3) 610// chain = VP_SCATTER chain,val,base,indices,scale,mask,evl 611BEGIN_REGISTER_VP_SDNODE(VP_SCATTER, 1, vp_scatter, 5, 6) 612HELPER_MAP_VPID_TO_VPSD(vp_scatter, VP_SCATTER) 613VP_PROPERTY_FUNCTIONAL_INTRINSIC(masked_scatter) 614VP_PROPERTY_MEMOP(1, 0) 615END_REGISTER_VP(vp_scatter, VP_SCATTER) 616 617// llvm.vp.load(ptr,mask,vlen) 618BEGIN_REGISTER_VP_INTRINSIC(vp_load, 1, 2) 619// val,chain = VP_LOAD chain,base,offset,mask,evl 620BEGIN_REGISTER_VP_SDNODE(VP_LOAD, -1, vp_load, 3, 4) 621HELPER_MAP_VPID_TO_VPSD(vp_load, VP_LOAD) 622VP_PROPERTY_FUNCTIONAL_OPC(Load) 623VP_PROPERTY_FUNCTIONAL_INTRINSIC(masked_load) 624VP_PROPERTY_MEMOP(0, std::nullopt) 625END_REGISTER_VP(vp_load, VP_LOAD) 626 627// llvm.experimental.vp.strided.load(ptr,stride,mask,vlen) 628BEGIN_REGISTER_VP_INTRINSIC(experimental_vp_strided_load, 2, 3) 629// chain = EXPERIMENTAL_VP_STRIDED_LOAD chain,base,offset,stride,mask,evl 630VP_PROPERTY_NO_FUNCTIONAL 631BEGIN_REGISTER_VP_SDNODE(EXPERIMENTAL_VP_STRIDED_LOAD, -1, experimental_vp_strided_load, 4, 5) 632HELPER_MAP_VPID_TO_VPSD(experimental_vp_strided_load, EXPERIMENTAL_VP_STRIDED_LOAD) 633VP_PROPERTY_MEMOP(0, std::nullopt) 634END_REGISTER_VP(experimental_vp_strided_load, EXPERIMENTAL_VP_STRIDED_LOAD) 635 636// llvm.vp.gather(ptr,mask,vlen) 637BEGIN_REGISTER_VP_INTRINSIC(vp_gather, 1, 2) 638// val,chain = VP_GATHER chain,base,indices,scale,mask,evl 639BEGIN_REGISTER_VP_SDNODE(VP_GATHER, -1, vp_gather, 4, 5) 640HELPER_MAP_VPID_TO_VPSD(vp_gather, VP_GATHER) 641VP_PROPERTY_FUNCTIONAL_INTRINSIC(masked_gather) 642VP_PROPERTY_MEMOP(0, std::nullopt) 643END_REGISTER_VP(vp_gather, VP_GATHER) 644 645///// } Memory Operations 646 647///// Reductions { 648 649// Specialized helper macro for VP reductions (%start, %x, %mask, %evl). 650#ifdef HELPER_REGISTER_REDUCTION_VP 651#error \ 652 "The internal helper macro HELPER_REGISTER_REDUCTION_VP is already defined!" 653#endif 654#define HELPER_REGISTER_REDUCTION_VP(VPID, VPSD, INTRIN) \ 655 BEGIN_REGISTER_VP(VPID, 2, 3, VPSD, 1) \ 656 VP_PROPERTY_FUNCTIONAL_INTRINSIC(INTRIN) \ 657 VP_PROPERTY_REDUCTION(0, 1) \ 658 END_REGISTER_VP(VPID, VPSD) 659 660// llvm.vp.reduce.add(start,x,mask,vlen) 661HELPER_REGISTER_REDUCTION_VP(vp_reduce_add, VP_REDUCE_ADD, 662 vector_reduce_add) 663 664// llvm.vp.reduce.mul(start,x,mask,vlen) 665HELPER_REGISTER_REDUCTION_VP(vp_reduce_mul, VP_REDUCE_MUL, 666 vector_reduce_mul) 667 668// llvm.vp.reduce.and(start,x,mask,vlen) 669HELPER_REGISTER_REDUCTION_VP(vp_reduce_and, VP_REDUCE_AND, 670 vector_reduce_and) 671 672// llvm.vp.reduce.or(start,x,mask,vlen) 673HELPER_REGISTER_REDUCTION_VP(vp_reduce_or, VP_REDUCE_OR, 674 vector_reduce_or) 675 676// llvm.vp.reduce.xor(start,x,mask,vlen) 677HELPER_REGISTER_REDUCTION_VP(vp_reduce_xor, VP_REDUCE_XOR, 678 vector_reduce_xor) 679 680// llvm.vp.reduce.smax(start,x,mask,vlen) 681HELPER_REGISTER_REDUCTION_VP(vp_reduce_smax, VP_REDUCE_SMAX, 682 vector_reduce_smax) 683 684// llvm.vp.reduce.smin(start,x,mask,vlen) 685HELPER_REGISTER_REDUCTION_VP(vp_reduce_smin, VP_REDUCE_SMIN, 686 vector_reduce_smin) 687 688// llvm.vp.reduce.umax(start,x,mask,vlen) 689HELPER_REGISTER_REDUCTION_VP(vp_reduce_umax, VP_REDUCE_UMAX, 690 vector_reduce_umax) 691 692// llvm.vp.reduce.umin(start,x,mask,vlen) 693HELPER_REGISTER_REDUCTION_VP(vp_reduce_umin, VP_REDUCE_UMIN, 694 vector_reduce_umin) 695 696// llvm.vp.reduce.fmax(start,x,mask,vlen) 697HELPER_REGISTER_REDUCTION_VP(vp_reduce_fmax, VP_REDUCE_FMAX, 698 vector_reduce_fmax) 699 700// llvm.vp.reduce.fmin(start,x,mask,vlen) 701HELPER_REGISTER_REDUCTION_VP(vp_reduce_fmin, VP_REDUCE_FMIN, 702 vector_reduce_fmin) 703 704// llvm.vp.reduce.fmaximum(start,x,mask,vlen) 705HELPER_REGISTER_REDUCTION_VP(vp_reduce_fmaximum, VP_REDUCE_FMAXIMUM, 706 vector_reduce_fmaximum) 707 708// llvm.vp.reduce.fminimum(start,x,mask,vlen) 709HELPER_REGISTER_REDUCTION_VP(vp_reduce_fminimum, VP_REDUCE_FMINIMUM, 710 vector_reduce_fminimum) 711 712#undef HELPER_REGISTER_REDUCTION_VP 713 714// Specialized helper macro for VP reductions as above but with two forms: 715// sequential and reassociative. These manifest as the presence of 'reassoc' 716// fast-math flags in the IR and as two distinct ISD opcodes in the 717// SelectionDAG. 718// Note we by default map from the VP intrinsic to the SEQ ISD opcode, which 719// can then be relaxed to the non-SEQ ISD opcode if the 'reassoc' flag is set. 720#ifdef HELPER_REGISTER_REDUCTION_SEQ_VP 721#error \ 722 "The internal helper macro HELPER_REGISTER_REDUCTION_SEQ_VP is already defined!" 723#endif 724#define HELPER_REGISTER_REDUCTION_SEQ_VP(VPID, VPSD, SEQ_VPSD, INTRIN) \ 725 BEGIN_REGISTER_VP_INTRINSIC(VPID, 2, 3) \ 726 BEGIN_REGISTER_VP_SDNODE(VPSD, 1, VPID, 2, 3) \ 727 VP_PROPERTY_REDUCTION(0, 1) \ 728 END_REGISTER_VP_SDNODE(VPSD) \ 729 BEGIN_REGISTER_VP_SDNODE(SEQ_VPSD, 1, VPID, 2, 3) \ 730 HELPER_MAP_VPID_TO_VPSD(VPID, SEQ_VPSD) \ 731 VP_PROPERTY_REDUCTION(0, 1) \ 732 END_REGISTER_VP_SDNODE(SEQ_VPSD) \ 733 VP_PROPERTY_FUNCTIONAL_INTRINSIC(INTRIN) \ 734 END_REGISTER_VP_INTRINSIC(VPID) 735 736// llvm.vp.reduce.fadd(start,x,mask,vlen) 737HELPER_REGISTER_REDUCTION_SEQ_VP(vp_reduce_fadd, VP_REDUCE_FADD, 738 VP_REDUCE_SEQ_FADD, 739 vector_reduce_fadd) 740 741// llvm.vp.reduce.fmul(start,x,mask,vlen) 742HELPER_REGISTER_REDUCTION_SEQ_VP(vp_reduce_fmul, VP_REDUCE_FMUL, 743 VP_REDUCE_SEQ_FMUL, 744 vector_reduce_fmul) 745 746#undef HELPER_REGISTER_REDUCTION_SEQ_VP 747 748///// } Reduction 749 750///// Shuffles { 751 752// The mask 'cond' operand of llvm.vp.select and llvm.vp.merge are not reported 753// as masks with the BEGIN_REGISTER_VP_* macros. This is because, unlike other 754// VP intrinsics, these two have a defined result on lanes where the mask is 755// false. 756// 757// llvm.vp.select(cond,on_true,on_false,vlen) 758BEGIN_REGISTER_VP(vp_select, std::nullopt, 3, VP_SELECT, -1) 759VP_PROPERTY_FUNCTIONAL_OPC(Select) 760VP_PROPERTY_FUNCTIONAL_SDOPC(VSELECT) 761END_REGISTER_VP(vp_select, VP_SELECT) 762 763// llvm.vp.merge(cond,on_true,on_false,pivot) 764BEGIN_REGISTER_VP(vp_merge, std::nullopt, 3, VP_MERGE, -1) 765VP_PROPERTY_NO_FUNCTIONAL 766END_REGISTER_VP(vp_merge, VP_MERGE) 767 768BEGIN_REGISTER_VP(experimental_vp_splice, 3, 5, EXPERIMENTAL_VP_SPLICE, -1) 769VP_PROPERTY_NO_FUNCTIONAL 770END_REGISTER_VP(experimental_vp_splice, EXPERIMENTAL_VP_SPLICE) 771 772// llvm.experimental.vp.reverse(x,mask,vlen) 773BEGIN_REGISTER_VP(experimental_vp_reverse, 1, 2, 774 EXPERIMENTAL_VP_REVERSE, -1) 775VP_PROPERTY_NO_FUNCTIONAL 776END_REGISTER_VP(experimental_vp_reverse, EXPERIMENTAL_VP_REVERSE) 777 778///// } Shuffles 779 780// llvm.vp.splat(val,mask,vlen) 781BEGIN_REGISTER_VP_INTRINSIC(experimental_vp_splat, 1, 2) 782BEGIN_REGISTER_VP_SDNODE(EXPERIMENTAL_VP_SPLAT, -1, experimental_vp_splat, 1, 2) 783VP_PROPERTY_NO_FUNCTIONAL 784HELPER_MAP_VPID_TO_VPSD(experimental_vp_splat, EXPERIMENTAL_VP_SPLAT) 785END_REGISTER_VP(experimental_vp_splat, EXPERIMENTAL_VP_SPLAT) 786 787#undef BEGIN_REGISTER_VP 788#undef BEGIN_REGISTER_VP_INTRINSIC 789#undef BEGIN_REGISTER_VP_SDNODE 790#undef END_REGISTER_VP 791#undef END_REGISTER_VP_INTRINSIC 792#undef END_REGISTER_VP_SDNODE 793#undef HELPER_MAP_VPID_TO_VPSD 794#undef VP_PROPERTY_BINARYOP 795#undef VP_PROPERTY_CASTOP 796#undef VP_PROPERTY_CMP 797#undef VP_PROPERTY_CONSTRAINEDFP 798#undef VP_PROPERTY_FUNCTIONAL_INTRINSIC 799#undef VP_PROPERTY_FUNCTIONAL_OPC 800#undef VP_PROPERTY_FUNCTIONAL_SDOPC 801#undef VP_PROPERTY_NO_FUNCTIONAL 802#undef VP_PROPERTY_MEMOP 803#undef VP_PROPERTY_REDUCTION 804