1//===----------------------------------------------------------------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// Automatically generated file, do not edit! 9//===----------------------------------------------------------------------===// 10 11// tag : A2_abs 12class Hexagon_i32_i32_Intrinsic<string GCCIntSuffix, 13 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 14 : Hexagon_Intrinsic<GCCIntSuffix, 15 [llvm_i32_ty], [llvm_i32_ty], 16 intr_properties>; 17 18// tag : A2_absp 19class Hexagon_i64_i64_Intrinsic<string GCCIntSuffix, 20 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 21 : Hexagon_Intrinsic<GCCIntSuffix, 22 [llvm_i64_ty], [llvm_i64_ty], 23 intr_properties>; 24 25// tag : A2_add 26class Hexagon_i32_i32i32_Intrinsic<string GCCIntSuffix, 27 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 28 : Hexagon_Intrinsic<GCCIntSuffix, 29 [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty], 30 intr_properties>; 31 32// tag : A2_addp 33class Hexagon_i64_i64i64_Intrinsic<string GCCIntSuffix, 34 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 35 : Hexagon_Intrinsic<GCCIntSuffix, 36 [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty], 37 intr_properties>; 38 39// tag : A2_addsp 40class Hexagon_i64_i32i64_Intrinsic<string GCCIntSuffix, 41 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 42 : Hexagon_Intrinsic<GCCIntSuffix, 43 [llvm_i64_ty], [llvm_i32_ty,llvm_i64_ty], 44 intr_properties>; 45 46// tag : A2_combineii 47class Hexagon_i64_i32i32_Intrinsic<string GCCIntSuffix, 48 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 49 : Hexagon_Intrinsic<GCCIntSuffix, 50 [llvm_i64_ty], [llvm_i32_ty,llvm_i32_ty], 51 intr_properties>; 52 53// tag : A2_roundsat 54class Hexagon_i32_i64_Intrinsic<string GCCIntSuffix, 55 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 56 : Hexagon_Intrinsic<GCCIntSuffix, 57 [llvm_i32_ty], [llvm_i64_ty], 58 intr_properties>; 59 60// tag : A2_sxtw 61class Hexagon_i64_i32_Intrinsic<string GCCIntSuffix, 62 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 63 : Hexagon_Intrinsic<GCCIntSuffix, 64 [llvm_i64_ty], [llvm_i32_ty], 65 intr_properties>; 66 67// tag : A2_vcmpbeq 68class Hexagon_i32_i64i64_Intrinsic<string GCCIntSuffix, 69 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 70 : Hexagon_Intrinsic<GCCIntSuffix, 71 [llvm_i32_ty], [llvm_i64_ty,llvm_i64_ty], 72 intr_properties>; 73 74// tag : A2_vraddub_acc 75class Hexagon_i64_i64i64i64_Intrinsic<string GCCIntSuffix, 76 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 77 : Hexagon_Intrinsic<GCCIntSuffix, 78 [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i64_ty], 79 intr_properties>; 80 81// tag : A4_boundscheck 82class Hexagon_i32_i32i64_Intrinsic<string GCCIntSuffix, 83 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 84 : Hexagon_Intrinsic<GCCIntSuffix, 85 [llvm_i32_ty], [llvm_i32_ty,llvm_i64_ty], 86 intr_properties>; 87 88// tag : A4_tlbmatch 89class Hexagon_i32_i64i32_Intrinsic<string GCCIntSuffix, 90 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 91 : Hexagon_Intrinsic<GCCIntSuffix, 92 [llvm_i32_ty], [llvm_i64_ty,llvm_i32_ty], 93 intr_properties>; 94 95// tag : A4_vrmaxh 96class Hexagon_i64_i64i64i32_Intrinsic<string GCCIntSuffix, 97 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 98 : Hexagon_Intrinsic<GCCIntSuffix, 99 [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i32_ty], 100 intr_properties>; 101 102// tag : A7_croundd_ri 103class Hexagon_i64_i64i32_Intrinsic<string GCCIntSuffix, 104 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 105 : Hexagon_Intrinsic<GCCIntSuffix, 106 [llvm_i64_ty], [llvm_i64_ty,llvm_i32_ty], 107 intr_properties>; 108 109// tag : C2_mux 110class Hexagon_i32_i32i32i32_Intrinsic<string GCCIntSuffix, 111 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 112 : Hexagon_Intrinsic<GCCIntSuffix, 113 [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty,llvm_i32_ty], 114 intr_properties>; 115 116// tag : C2_vmux 117class Hexagon_i64_i32i64i64_Intrinsic<string GCCIntSuffix, 118 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 119 : Hexagon_Intrinsic<GCCIntSuffix, 120 [llvm_i64_ty], [llvm_i32_ty,llvm_i64_ty,llvm_i64_ty], 121 intr_properties>; 122 123// tag : F2_conv_d2df 124class Hexagon_double_i64_Intrinsic<string GCCIntSuffix, 125 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 126 : Hexagon_Intrinsic<GCCIntSuffix, 127 [llvm_double_ty], [llvm_i64_ty], 128 intr_properties>; 129 130// tag : F2_conv_d2sf 131class Hexagon_float_i64_Intrinsic<string GCCIntSuffix, 132 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 133 : Hexagon_Intrinsic<GCCIntSuffix, 134 [llvm_float_ty], [llvm_i64_ty], 135 intr_properties>; 136 137// tag : F2_conv_df2d 138class Hexagon_i64_double_Intrinsic<string GCCIntSuffix, 139 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 140 : Hexagon_Intrinsic<GCCIntSuffix, 141 [llvm_i64_ty], [llvm_double_ty], 142 intr_properties>; 143 144// tag : F2_conv_df2sf 145class Hexagon_float_double_Intrinsic<string GCCIntSuffix, 146 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 147 : Hexagon_Intrinsic<GCCIntSuffix, 148 [llvm_float_ty], [llvm_double_ty], 149 intr_properties>; 150 151// tag : F2_conv_df2uw 152class Hexagon_i32_double_Intrinsic<string GCCIntSuffix, 153 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 154 : Hexagon_Intrinsic<GCCIntSuffix, 155 [llvm_i32_ty], [llvm_double_ty], 156 intr_properties>; 157 158// tag : F2_conv_sf2d 159class Hexagon_i64_float_Intrinsic<string GCCIntSuffix, 160 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 161 : Hexagon_Intrinsic<GCCIntSuffix, 162 [llvm_i64_ty], [llvm_float_ty], 163 intr_properties>; 164 165// tag : F2_conv_sf2df 166class Hexagon_double_float_Intrinsic<string GCCIntSuffix, 167 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 168 : Hexagon_Intrinsic<GCCIntSuffix, 169 [llvm_double_ty], [llvm_float_ty], 170 intr_properties>; 171 172// tag : F2_conv_sf2uw 173class Hexagon_i32_float_Intrinsic<string GCCIntSuffix, 174 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 175 : Hexagon_Intrinsic<GCCIntSuffix, 176 [llvm_i32_ty], [llvm_float_ty], 177 intr_properties>; 178 179// tag : F2_conv_uw2df 180class Hexagon_double_i32_Intrinsic<string GCCIntSuffix, 181 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 182 : Hexagon_Intrinsic<GCCIntSuffix, 183 [llvm_double_ty], [llvm_i32_ty], 184 intr_properties>; 185 186// tag : F2_conv_uw2sf 187class Hexagon_float_i32_Intrinsic<string GCCIntSuffix, 188 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 189 : Hexagon_Intrinsic<GCCIntSuffix, 190 [llvm_float_ty], [llvm_i32_ty], 191 intr_properties>; 192 193// tag : F2_dfadd 194class Hexagon_double_doubledouble_Intrinsic<string GCCIntSuffix, 195 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 196 : Hexagon_Intrinsic<GCCIntSuffix, 197 [llvm_double_ty], [llvm_double_ty,llvm_double_ty], 198 intr_properties>; 199 200// tag : F2_dfclass 201class Hexagon_i32_doublei32_Intrinsic<string GCCIntSuffix, 202 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 203 : Hexagon_Intrinsic<GCCIntSuffix, 204 [llvm_i32_ty], [llvm_double_ty,llvm_i32_ty], 205 intr_properties>; 206 207// tag : F2_dfcmpeq 208class Hexagon_i32_doubledouble_Intrinsic<string GCCIntSuffix, 209 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 210 : Hexagon_Intrinsic<GCCIntSuffix, 211 [llvm_i32_ty], [llvm_double_ty,llvm_double_ty], 212 intr_properties>; 213 214// tag : F2_dfmpyhh 215class Hexagon_double_doubledoubledouble_Intrinsic<string GCCIntSuffix, 216 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 217 : Hexagon_Intrinsic<GCCIntSuffix, 218 [llvm_double_ty], [llvm_double_ty,llvm_double_ty,llvm_double_ty], 219 intr_properties>; 220 221// tag : F2_sfadd 222class Hexagon_float_floatfloat_Intrinsic<string GCCIntSuffix, 223 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 224 : Hexagon_Intrinsic<GCCIntSuffix, 225 [llvm_float_ty], [llvm_float_ty,llvm_float_ty], 226 intr_properties>; 227 228// tag : F2_sfclass 229class Hexagon_i32_floati32_Intrinsic<string GCCIntSuffix, 230 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 231 : Hexagon_Intrinsic<GCCIntSuffix, 232 [llvm_i32_ty], [llvm_float_ty,llvm_i32_ty], 233 intr_properties>; 234 235// tag : F2_sfcmpeq 236class Hexagon_i32_floatfloat_Intrinsic<string GCCIntSuffix, 237 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 238 : Hexagon_Intrinsic<GCCIntSuffix, 239 [llvm_i32_ty], [llvm_float_ty,llvm_float_ty], 240 intr_properties>; 241 242// tag : F2_sffixupr 243class Hexagon_float_float_Intrinsic<string GCCIntSuffix, 244 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 245 : Hexagon_Intrinsic<GCCIntSuffix, 246 [llvm_float_ty], [llvm_float_ty], 247 intr_properties>; 248 249// tag : F2_sffma 250class Hexagon_float_floatfloatfloat_Intrinsic<string GCCIntSuffix, 251 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 252 : Hexagon_Intrinsic<GCCIntSuffix, 253 [llvm_float_ty], [llvm_float_ty,llvm_float_ty,llvm_float_ty], 254 intr_properties>; 255 256// tag : F2_sffma_sc 257class Hexagon_float_floatfloatfloati32_Intrinsic<string GCCIntSuffix, 258 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 259 : Hexagon_Intrinsic<GCCIntSuffix, 260 [llvm_float_ty], [llvm_float_ty,llvm_float_ty,llvm_float_ty,llvm_i32_ty], 261 intr_properties>; 262 263// tag : M2_cmaci_s0 264class Hexagon_i64_i64i32i32_Intrinsic<string GCCIntSuffix, 265 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 266 : Hexagon_Intrinsic<GCCIntSuffix, 267 [llvm_i64_ty], [llvm_i64_ty,llvm_i32_ty,llvm_i32_ty], 268 intr_properties>; 269 270// tag : S2_insert 271class Hexagon_i32_i32i32i32i32_Intrinsic<string GCCIntSuffix, 272 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 273 : Hexagon_Intrinsic<GCCIntSuffix, 274 [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty,llvm_i32_ty,llvm_i32_ty], 275 intr_properties>; 276 277// tag : S2_insert_rp 278class Hexagon_i32_i32i32i64_Intrinsic<string GCCIntSuffix, 279 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 280 : Hexagon_Intrinsic<GCCIntSuffix, 281 [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty,llvm_i64_ty], 282 intr_properties>; 283 284// tag : S2_insertp 285class Hexagon_i64_i64i64i32i32_Intrinsic<string GCCIntSuffix, 286 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 287 : Hexagon_Intrinsic<GCCIntSuffix, 288 [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i32_ty,llvm_i32_ty], 289 intr_properties>; 290 291// tag : V6_extractw 292class Hexagon_i32_v16i32i32_Intrinsic<string GCCIntSuffix, 293 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 294 : Hexagon_Intrinsic<GCCIntSuffix, 295 [llvm_i32_ty], [llvm_v16i32_ty,llvm_i32_ty], 296 intr_properties>; 297 298// tag : V6_extractw 299class Hexagon_i32_v32i32i32_Intrinsic<string GCCIntSuffix, 300 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 301 : Hexagon_Intrinsic<GCCIntSuffix, 302 [llvm_i32_ty], [llvm_v32i32_ty,llvm_i32_ty], 303 intr_properties>; 304 305// tag : V6_hi 306class Hexagon_v16i32_v32i32_Intrinsic<string GCCIntSuffix, 307 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 308 : Hexagon_Intrinsic<GCCIntSuffix, 309 [llvm_v16i32_ty], [llvm_v32i32_ty], 310 intr_properties>; 311 312// tag : V6_hi 313class Hexagon_v32i32_v64i32_Intrinsic<string GCCIntSuffix, 314 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 315 : Hexagon_Intrinsic<GCCIntSuffix, 316 [llvm_v32i32_ty], [llvm_v64i32_ty], 317 intr_properties>; 318 319// tag : V6_lvsplatb 320class Hexagon_v16i32_i32_Intrinsic<string GCCIntSuffix, 321 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 322 : Hexagon_Intrinsic<GCCIntSuffix, 323 [llvm_v16i32_ty], [llvm_i32_ty], 324 intr_properties>; 325 326// tag : V6_lvsplatb 327class Hexagon_v32i32_i32_Intrinsic<string GCCIntSuffix, 328 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 329 : Hexagon_Intrinsic<GCCIntSuffix, 330 [llvm_v32i32_ty], [llvm_i32_ty], 331 intr_properties>; 332 333// tag : V6_pred_and 334class Hexagon_v64i1_v64i1v64i1_Intrinsic<string GCCIntSuffix, 335 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 336 : Hexagon_Intrinsic<GCCIntSuffix, 337 [llvm_v64i1_ty], [llvm_v64i1_ty,llvm_v64i1_ty], 338 intr_properties>; 339 340// tag : V6_pred_and 341class Hexagon_v128i1_v128i1v128i1_Intrinsic<string GCCIntSuffix, 342 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 343 : Hexagon_Intrinsic<GCCIntSuffix, 344 [llvm_v128i1_ty], [llvm_v128i1_ty,llvm_v128i1_ty], 345 intr_properties>; 346 347// tag : V6_pred_not 348class Hexagon_v64i1_v64i1_Intrinsic<string GCCIntSuffix, 349 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 350 : Hexagon_Intrinsic<GCCIntSuffix, 351 [llvm_v64i1_ty], [llvm_v64i1_ty], 352 intr_properties>; 353 354// tag : V6_pred_not 355class Hexagon_v128i1_v128i1_Intrinsic<string GCCIntSuffix, 356 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 357 : Hexagon_Intrinsic<GCCIntSuffix, 358 [llvm_v128i1_ty], [llvm_v128i1_ty], 359 intr_properties>; 360 361// tag : V6_pred_scalar2 362class Hexagon_v64i1_i32_Intrinsic<string GCCIntSuffix, 363 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 364 : Hexagon_Intrinsic<GCCIntSuffix, 365 [llvm_v64i1_ty], [llvm_i32_ty], 366 intr_properties>; 367 368// tag : V6_pred_scalar2 369class Hexagon_v128i1_i32_Intrinsic<string GCCIntSuffix, 370 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 371 : Hexagon_Intrinsic<GCCIntSuffix, 372 [llvm_v128i1_ty], [llvm_i32_ty], 373 intr_properties>; 374 375// tag : V6_v6mpyhubs10 376class Hexagon_v32i32_v32i32v32i32i32_Intrinsic<string GCCIntSuffix, 377 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 378 : Hexagon_Intrinsic<GCCIntSuffix, 379 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty], 380 intr_properties>; 381 382// tag : V6_v6mpyhubs10 383class Hexagon_v64i32_v64i32v64i32i32_Intrinsic<string GCCIntSuffix, 384 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 385 : Hexagon_Intrinsic<GCCIntSuffix, 386 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty,llvm_i32_ty], 387 intr_properties>; 388 389// tag : V6_v6mpyhubs10_vxx 390class Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<string GCCIntSuffix, 391 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 392 : Hexagon_Intrinsic<GCCIntSuffix, 393 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty], 394 intr_properties>; 395 396// tag : V6_v6mpyhubs10_vxx 397class Hexagon_v64i32_v64i32v64i32v64i32i32_Intrinsic<string GCCIntSuffix, 398 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 399 : Hexagon_Intrinsic<GCCIntSuffix, 400 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty,llvm_v64i32_ty,llvm_i32_ty], 401 intr_properties>; 402 403// tag : V6_vS32b_nqpred_ai 404class Hexagon__v64i1ptrv16i32_Intrinsic<string GCCIntSuffix, 405 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 406 : Hexagon_Intrinsic<GCCIntSuffix, 407 [], [llvm_v64i1_ty,llvm_ptr_ty,llvm_v16i32_ty], 408 intr_properties>; 409 410// tag : V6_vS32b_nqpred_ai 411class Hexagon__v128i1ptrv32i32_Intrinsic<string GCCIntSuffix, 412 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 413 : Hexagon_Intrinsic<GCCIntSuffix, 414 [], [llvm_v128i1_ty,llvm_ptr_ty,llvm_v32i32_ty], 415 intr_properties>; 416 417// tag : V6_vabs_hf 418class Hexagon_v16i32_v16i32_Intrinsic<string GCCIntSuffix, 419 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 420 : Hexagon_Intrinsic<GCCIntSuffix, 421 [llvm_v16i32_ty], [llvm_v16i32_ty], 422 intr_properties>; 423 424// tag : V6_vabs_hf 425class Hexagon_v32i32_v32i32_Intrinsic<string GCCIntSuffix, 426 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 427 : Hexagon_Intrinsic<GCCIntSuffix, 428 [llvm_v32i32_ty], [llvm_v32i32_ty], 429 intr_properties>; 430 431// tag : V6_vabsdiffh 432class Hexagon_v16i32_v16i32v16i32_Intrinsic<string GCCIntSuffix, 433 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 434 : Hexagon_Intrinsic<GCCIntSuffix, 435 [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty], 436 intr_properties>; 437 438// tag : V6_vabsdiffh 439class Hexagon_v32i32_v32i32v32i32_Intrinsic<string GCCIntSuffix, 440 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 441 : Hexagon_Intrinsic<GCCIntSuffix, 442 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty], 443 intr_properties>; 444 445// tag : V6_vadd_sf_bf 446class Hexagon_v32i32_v16i32v16i32_Intrinsic<string GCCIntSuffix, 447 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 448 : Hexagon_Intrinsic<GCCIntSuffix, 449 [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty], 450 intr_properties>; 451 452// tag : V6_vadd_sf_bf 453class Hexagon_v64i32_v32i32v32i32_Intrinsic<string GCCIntSuffix, 454 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 455 : Hexagon_Intrinsic<GCCIntSuffix, 456 [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty], 457 intr_properties>; 458 459// tag : V6_vaddb_dv 460class Hexagon_v64i32_v64i32v64i32_Intrinsic<string GCCIntSuffix, 461 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 462 : Hexagon_Intrinsic<GCCIntSuffix, 463 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty], 464 intr_properties>; 465 466// tag : V6_vaddbnq 467class Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<string GCCIntSuffix, 468 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 469 : Hexagon_Intrinsic<GCCIntSuffix, 470 [llvm_v16i32_ty], [llvm_v64i1_ty,llvm_v16i32_ty,llvm_v16i32_ty], 471 intr_properties>; 472 473// tag : V6_vaddbnq 474class Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<string GCCIntSuffix, 475 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 476 : Hexagon_Intrinsic<GCCIntSuffix, 477 [llvm_v32i32_ty], [llvm_v128i1_ty,llvm_v32i32_ty,llvm_v32i32_ty], 478 intr_properties>; 479 480// tag : V6_vaddcarry 481class Hexagon_custom_v16i32v64i1_v16i32v16i32v64i1_Intrinsic< 482 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 483 : Hexagon_NonGCC_Intrinsic< 484 [llvm_v16i32_ty,llvm_v64i1_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v64i1_ty], 485 intr_properties>; 486 487// tag : V6_vaddcarry 488class Hexagon_custom_v32i32v128i1_v32i32v32i32v128i1_Intrinsic_128B< 489 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 490 : Hexagon_NonGCC_Intrinsic< 491 [llvm_v32i32_ty,llvm_v128i1_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v128i1_ty], 492 intr_properties>; 493 494// tag : V6_vaddcarryo 495class Hexagon_custom_v16i32v64i1_v16i32v16i32_Intrinsic< 496 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 497 : Hexagon_NonGCC_Intrinsic< 498 [llvm_v16i32_ty,llvm_v64i1_ty], [llvm_v16i32_ty,llvm_v16i32_ty], 499 intr_properties>; 500 501// tag : V6_vaddcarryo 502class Hexagon_custom_v32i32v128i1_v32i32v32i32_Intrinsic_128B< 503 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 504 : Hexagon_NonGCC_Intrinsic< 505 [llvm_v32i32_ty,llvm_v128i1_ty], [llvm_v32i32_ty,llvm_v32i32_ty], 506 intr_properties>; 507 508// tag : V6_vaddcarrysat 509class Hexagon_v16i32_v16i32v16i32v64i1_Intrinsic<string GCCIntSuffix, 510 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 511 : Hexagon_Intrinsic<GCCIntSuffix, 512 [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v64i1_ty], 513 intr_properties>; 514 515// tag : V6_vaddcarrysat 516class Hexagon_v32i32_v32i32v32i32v128i1_Intrinsic<string GCCIntSuffix, 517 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 518 : Hexagon_Intrinsic<GCCIntSuffix, 519 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v128i1_ty], 520 intr_properties>; 521 522// tag : V6_vaddhw_acc 523class Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<string GCCIntSuffix, 524 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 525 : Hexagon_Intrinsic<GCCIntSuffix, 526 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_v16i32_ty], 527 intr_properties>; 528 529// tag : V6_vaddhw_acc 530class Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<string GCCIntSuffix, 531 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 532 : Hexagon_Intrinsic<GCCIntSuffix, 533 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_v32i32_ty], 534 intr_properties>; 535 536// tag : V6_valignb 537class Hexagon_v16i32_v16i32v16i32i32_Intrinsic<string GCCIntSuffix, 538 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 539 : Hexagon_Intrinsic<GCCIntSuffix, 540 [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty], 541 intr_properties>; 542 543// tag : V6_vandnqrt 544class Hexagon_v16i32_v64i1i32_Intrinsic<string GCCIntSuffix, 545 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 546 : Hexagon_Intrinsic<GCCIntSuffix, 547 [llvm_v16i32_ty], [llvm_v64i1_ty,llvm_i32_ty], 548 intr_properties>; 549 550// tag : V6_vandnqrt 551class Hexagon_v32i32_v128i1i32_Intrinsic<string GCCIntSuffix, 552 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 553 : Hexagon_Intrinsic<GCCIntSuffix, 554 [llvm_v32i32_ty], [llvm_v128i1_ty,llvm_i32_ty], 555 intr_properties>; 556 557// tag : V6_vandnqrt_acc 558class Hexagon_v16i32_v16i32v64i1i32_Intrinsic<string GCCIntSuffix, 559 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 560 : Hexagon_Intrinsic<GCCIntSuffix, 561 [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v64i1_ty,llvm_i32_ty], 562 intr_properties>; 563 564// tag : V6_vandnqrt_acc 565class Hexagon_v32i32_v32i32v128i1i32_Intrinsic<string GCCIntSuffix, 566 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 567 : Hexagon_Intrinsic<GCCIntSuffix, 568 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v128i1_ty,llvm_i32_ty], 569 intr_properties>; 570 571// tag : V6_vandvnqv 572class Hexagon_v16i32_v64i1v16i32_Intrinsic<string GCCIntSuffix, 573 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 574 : Hexagon_Intrinsic<GCCIntSuffix, 575 [llvm_v16i32_ty], [llvm_v64i1_ty,llvm_v16i32_ty], 576 intr_properties>; 577 578// tag : V6_vandvnqv 579class Hexagon_v32i32_v128i1v32i32_Intrinsic<string GCCIntSuffix, 580 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 581 : Hexagon_Intrinsic<GCCIntSuffix, 582 [llvm_v32i32_ty], [llvm_v128i1_ty,llvm_v32i32_ty], 583 intr_properties>; 584 585// tag : V6_vandvrt 586class Hexagon_v64i1_v16i32i32_Intrinsic<string GCCIntSuffix, 587 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 588 : Hexagon_Intrinsic<GCCIntSuffix, 589 [llvm_v64i1_ty], [llvm_v16i32_ty,llvm_i32_ty], 590 intr_properties>; 591 592// tag : V6_vandvrt 593class Hexagon_v128i1_v32i32i32_Intrinsic<string GCCIntSuffix, 594 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 595 : Hexagon_Intrinsic<GCCIntSuffix, 596 [llvm_v128i1_ty], [llvm_v32i32_ty,llvm_i32_ty], 597 intr_properties>; 598 599// tag : V6_vandvrt_acc 600class Hexagon_v64i1_v64i1v16i32i32_Intrinsic<string GCCIntSuffix, 601 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 602 : Hexagon_Intrinsic<GCCIntSuffix, 603 [llvm_v64i1_ty], [llvm_v64i1_ty,llvm_v16i32_ty,llvm_i32_ty], 604 intr_properties>; 605 606// tag : V6_vandvrt_acc 607class Hexagon_v128i1_v128i1v32i32i32_Intrinsic<string GCCIntSuffix, 608 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 609 : Hexagon_Intrinsic<GCCIntSuffix, 610 [llvm_v128i1_ty], [llvm_v128i1_ty,llvm_v32i32_ty,llvm_i32_ty], 611 intr_properties>; 612 613// tag : V6_vaslh 614class Hexagon_v16i32_v16i32i32_Intrinsic<string GCCIntSuffix, 615 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 616 : Hexagon_Intrinsic<GCCIntSuffix, 617 [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_i32_ty], 618 intr_properties>; 619 620// tag : V6_vaslh 621class Hexagon_v32i32_v32i32i32_Intrinsic<string GCCIntSuffix, 622 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 623 : Hexagon_Intrinsic<GCCIntSuffix, 624 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i32_ty], 625 intr_properties>; 626 627// tag : V6_vasrvuhubrndsat 628class Hexagon_v16i32_v32i32v16i32_Intrinsic<string GCCIntSuffix, 629 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 630 : Hexagon_Intrinsic<GCCIntSuffix, 631 [llvm_v16i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty], 632 intr_properties>; 633 634// tag : V6_vasrvuhubrndsat 635class Hexagon_v32i32_v64i32v32i32_Intrinsic<string GCCIntSuffix, 636 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 637 : Hexagon_Intrinsic<GCCIntSuffix, 638 [llvm_v32i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty], 639 intr_properties>; 640 641// tag : V6_vassignp 642class Hexagon_v64i32_v64i32_Intrinsic<string GCCIntSuffix, 643 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 644 : Hexagon_Intrinsic<GCCIntSuffix, 645 [llvm_v64i32_ty], [llvm_v64i32_ty], 646 intr_properties>; 647 648// tag : V6_vcvt_hf_b 649class Hexagon_v32i32_v16i32_Intrinsic<string GCCIntSuffix, 650 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 651 : Hexagon_Intrinsic<GCCIntSuffix, 652 [llvm_v32i32_ty], [llvm_v16i32_ty], 653 intr_properties>; 654 655// tag : V6_vcvt_hf_b 656class Hexagon_v64i32_v32i32_Intrinsic<string GCCIntSuffix, 657 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 658 : Hexagon_Intrinsic<GCCIntSuffix, 659 [llvm_v64i32_ty], [llvm_v32i32_ty], 660 intr_properties>; 661 662// tag : V6_vd0 663class Hexagon_v16i32__Intrinsic<string GCCIntSuffix, 664 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 665 : Hexagon_Intrinsic<GCCIntSuffix, 666 [llvm_v16i32_ty], [], 667 intr_properties>; 668 669// tag : V6_vd0 670class Hexagon_v32i32__Intrinsic<string GCCIntSuffix, 671 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 672 : Hexagon_Intrinsic<GCCIntSuffix, 673 [llvm_v32i32_ty], [], 674 intr_properties>; 675 676// tag : V6_vdd0 677class Hexagon_v64i32__Intrinsic<string GCCIntSuffix, 678 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 679 : Hexagon_Intrinsic<GCCIntSuffix, 680 [llvm_v64i32_ty], [], 681 intr_properties>; 682 683// tag : V6_vdealvdd 684class Hexagon_v32i32_v16i32v16i32i32_Intrinsic<string GCCIntSuffix, 685 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 686 : Hexagon_Intrinsic<GCCIntSuffix, 687 [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty], 688 intr_properties>; 689 690// tag : V6_vdealvdd 691class Hexagon_v64i32_v32i32v32i32i32_Intrinsic<string GCCIntSuffix, 692 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 693 : Hexagon_Intrinsic<GCCIntSuffix, 694 [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty], 695 intr_properties>; 696 697// tag : V6_vdmpy_sf_hf_acc 698class Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<string GCCIntSuffix, 699 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 700 : Hexagon_Intrinsic<GCCIntSuffix, 701 [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v16i32_ty], 702 intr_properties>; 703 704// tag : V6_vdmpy_sf_hf_acc 705class Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<string GCCIntSuffix, 706 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 707 : Hexagon_Intrinsic<GCCIntSuffix, 708 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v32i32_ty], 709 intr_properties>; 710 711// tag : V6_vdmpybus_dv 712class Hexagon_v64i32_v64i32i32_Intrinsic<string GCCIntSuffix, 713 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 714 : Hexagon_Intrinsic<GCCIntSuffix, 715 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_i32_ty], 716 intr_properties>; 717 718// tag : V6_vdmpyhisat 719class Hexagon_v16i32_v32i32i32_Intrinsic<string GCCIntSuffix, 720 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 721 : Hexagon_Intrinsic<GCCIntSuffix, 722 [llvm_v16i32_ty], [llvm_v32i32_ty,llvm_i32_ty], 723 intr_properties>; 724 725// tag : V6_vdmpyhisat 726class Hexagon_v32i32_v64i32i32_Intrinsic<string GCCIntSuffix, 727 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 728 : Hexagon_Intrinsic<GCCIntSuffix, 729 [llvm_v32i32_ty], [llvm_v64i32_ty,llvm_i32_ty], 730 intr_properties>; 731 732// tag : V6_vdmpyhisat_acc 733class Hexagon_v16i32_v16i32v32i32i32_Intrinsic<string GCCIntSuffix, 734 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 735 : Hexagon_Intrinsic<GCCIntSuffix, 736 [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v32i32_ty,llvm_i32_ty], 737 intr_properties>; 738 739// tag : V6_vdmpyhisat_acc 740class Hexagon_v32i32_v32i32v64i32i32_Intrinsic<string GCCIntSuffix, 741 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 742 : Hexagon_Intrinsic<GCCIntSuffix, 743 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v64i32_ty,llvm_i32_ty], 744 intr_properties>; 745 746// tag : V6_veqb 747class Hexagon_v64i1_v16i32v16i32_Intrinsic<string GCCIntSuffix, 748 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 749 : Hexagon_Intrinsic<GCCIntSuffix, 750 [llvm_v64i1_ty], [llvm_v16i32_ty,llvm_v16i32_ty], 751 intr_properties>; 752 753// tag : V6_veqb 754class Hexagon_v128i1_v32i32v32i32_Intrinsic<string GCCIntSuffix, 755 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 756 : Hexagon_Intrinsic<GCCIntSuffix, 757 [llvm_v128i1_ty], [llvm_v32i32_ty,llvm_v32i32_ty], 758 intr_properties>; 759 760// tag : V6_veqb_and 761class Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<string GCCIntSuffix, 762 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 763 : Hexagon_Intrinsic<GCCIntSuffix, 764 [llvm_v64i1_ty], [llvm_v64i1_ty,llvm_v16i32_ty,llvm_v16i32_ty], 765 intr_properties>; 766 767// tag : V6_veqb_and 768class Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<string GCCIntSuffix, 769 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 770 : Hexagon_Intrinsic<GCCIntSuffix, 771 [llvm_v128i1_ty], [llvm_v128i1_ty,llvm_v32i32_ty,llvm_v32i32_ty], 772 intr_properties>; 773 774// tag : V6_vgathermh 775class Hexagon__ptri32i32v16i32_Intrinsic<string GCCIntSuffix, 776 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 777 : Hexagon_Intrinsic<GCCIntSuffix, 778 [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty,llvm_v16i32_ty], 779 intr_properties>; 780 781// tag : V6_vgathermh 782class Hexagon__ptri32i32v32i32_Intrinsic<string GCCIntSuffix, 783 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 784 : Hexagon_Intrinsic<GCCIntSuffix, 785 [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty,llvm_v32i32_ty], 786 intr_properties>; 787 788// tag : V6_vgathermhq 789class Hexagon__ptrv64i1i32i32v16i32_Intrinsic<string GCCIntSuffix, 790 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 791 : Hexagon_Intrinsic<GCCIntSuffix, 792 [], [llvm_ptr_ty,llvm_v64i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v16i32_ty], 793 intr_properties>; 794 795// tag : V6_vgathermhq 796class Hexagon__ptrv128i1i32i32v32i32_Intrinsic<string GCCIntSuffix, 797 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 798 : Hexagon_Intrinsic<GCCIntSuffix, 799 [], [llvm_ptr_ty,llvm_v128i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v32i32_ty], 800 intr_properties>; 801 802// tag : V6_vgathermhw 803class Hexagon__ptri32i32v64i32_Intrinsic<string GCCIntSuffix, 804 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 805 : Hexagon_Intrinsic<GCCIntSuffix, 806 [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty,llvm_v64i32_ty], 807 intr_properties>; 808 809// tag : V6_vgathermhwq 810class Hexagon__ptrv64i1i32i32v32i32_Intrinsic<string GCCIntSuffix, 811 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 812 : Hexagon_Intrinsic<GCCIntSuffix, 813 [], [llvm_ptr_ty,llvm_v64i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v32i32_ty], 814 intr_properties>; 815 816// tag : V6_vgathermhwq 817class Hexagon__ptrv128i1i32i32v64i32_Intrinsic<string GCCIntSuffix, 818 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 819 : Hexagon_Intrinsic<GCCIntSuffix, 820 [], [llvm_ptr_ty,llvm_v128i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v64i32_ty], 821 intr_properties>; 822 823// tag : V6_vlut4 824class Hexagon_v16i32_v16i32i64_Intrinsic<string GCCIntSuffix, 825 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 826 : Hexagon_Intrinsic<GCCIntSuffix, 827 [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_i64_ty], 828 intr_properties>; 829 830// tag : V6_vlut4 831class Hexagon_v32i32_v32i32i64_Intrinsic<string GCCIntSuffix, 832 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 833 : Hexagon_Intrinsic<GCCIntSuffix, 834 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i64_ty], 835 intr_properties>; 836 837// tag : V6_vlutvvb_oracc 838class Hexagon_v16i32_v16i32v16i32v16i32i32_Intrinsic<string GCCIntSuffix, 839 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 840 : Hexagon_Intrinsic<GCCIntSuffix, 841 [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty], 842 intr_properties>; 843 844// tag : V6_vlutvwh_oracc 845class Hexagon_v32i32_v32i32v16i32v16i32i32_Intrinsic<string GCCIntSuffix, 846 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 847 : Hexagon_Intrinsic<GCCIntSuffix, 848 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty], 849 intr_properties>; 850 851// tag : V6_vlutvwh_oracc 852class Hexagon_v64i32_v64i32v32i32v32i32i32_Intrinsic<string GCCIntSuffix, 853 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 854 : Hexagon_Intrinsic<GCCIntSuffix, 855 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty], 856 intr_properties>; 857 858// tag : V6_vmpahhsat 859class Hexagon_v16i32_v16i32v16i32i64_Intrinsic<string GCCIntSuffix, 860 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 861 : Hexagon_Intrinsic<GCCIntSuffix, 862 [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i64_ty], 863 intr_properties>; 864 865// tag : V6_vmpahhsat 866class Hexagon_v32i32_v32i32v32i32i64_Intrinsic<string GCCIntSuffix, 867 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 868 : Hexagon_Intrinsic<GCCIntSuffix, 869 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i64_ty], 870 intr_properties>; 871 872// tag : V6_vmpybus 873class Hexagon_v32i32_v16i32i32_Intrinsic<string GCCIntSuffix, 874 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 875 : Hexagon_Intrinsic<GCCIntSuffix, 876 [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_i32_ty], 877 intr_properties>; 878 879// tag : V6_vmpybus 880class Hexagon_v64i32_v32i32i32_Intrinsic<string GCCIntSuffix, 881 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 882 : Hexagon_Intrinsic<GCCIntSuffix, 883 [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_i32_ty], 884 intr_properties>; 885 886// tag : V6_vmpybus_acc 887class Hexagon_v32i32_v32i32v16i32i32_Intrinsic<string GCCIntSuffix, 888 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 889 : Hexagon_Intrinsic<GCCIntSuffix, 890 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_i32_ty], 891 intr_properties>; 892 893// tag : V6_vmpybus_acc 894class Hexagon_v64i32_v64i32v32i32i32_Intrinsic<string GCCIntSuffix, 895 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 896 : Hexagon_Intrinsic<GCCIntSuffix, 897 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_i32_ty], 898 intr_properties>; 899 900// tag : V6_vprefixqb 901class Hexagon_v16i32_v64i1_Intrinsic<string GCCIntSuffix, 902 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 903 : Hexagon_Intrinsic<GCCIntSuffix, 904 [llvm_v16i32_ty], [llvm_v64i1_ty], 905 intr_properties>; 906 907// tag : V6_vprefixqb 908class Hexagon_v32i32_v128i1_Intrinsic<string GCCIntSuffix, 909 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 910 : Hexagon_Intrinsic<GCCIntSuffix, 911 [llvm_v32i32_ty], [llvm_v128i1_ty], 912 intr_properties>; 913 914// tag : V6_vrmpybusi 915class Hexagon_v32i32_v32i32i32i32_Intrinsic<string GCCIntSuffix, 916 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 917 : Hexagon_Intrinsic<GCCIntSuffix, 918 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i32_ty,llvm_i32_ty], 919 intr_properties>; 920 921// tag : V6_vrmpybusi 922class Hexagon_v64i32_v64i32i32i32_Intrinsic<string GCCIntSuffix, 923 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 924 : Hexagon_Intrinsic<GCCIntSuffix, 925 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_i32_ty,llvm_i32_ty], 926 intr_properties>; 927 928// tag : V6_vrmpybusi_acc 929class Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<string GCCIntSuffix, 930 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 931 : Hexagon_Intrinsic<GCCIntSuffix, 932 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty,llvm_i32_ty], 933 intr_properties>; 934 935// tag : V6_vrmpybusi_acc 936class Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<string GCCIntSuffix, 937 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 938 : Hexagon_Intrinsic<GCCIntSuffix, 939 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty,llvm_i32_ty,llvm_i32_ty], 940 intr_properties>; 941 942// tag : V6_vscattermh 943class Hexagon__i32i32v16i32v16i32_Intrinsic<string GCCIntSuffix, 944 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 945 : Hexagon_Intrinsic<GCCIntSuffix, 946 [], [llvm_i32_ty,llvm_i32_ty,llvm_v16i32_ty,llvm_v16i32_ty], 947 intr_properties>; 948 949// tag : V6_vscattermh 950class Hexagon__i32i32v32i32v32i32_Intrinsic<string GCCIntSuffix, 951 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 952 : Hexagon_Intrinsic<GCCIntSuffix, 953 [], [llvm_i32_ty,llvm_i32_ty,llvm_v32i32_ty,llvm_v32i32_ty], 954 intr_properties>; 955 956// tag : V6_vscattermhq 957class Hexagon__v64i1i32i32v16i32v16i32_Intrinsic<string GCCIntSuffix, 958 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 959 : Hexagon_Intrinsic<GCCIntSuffix, 960 [], [llvm_v64i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v16i32_ty,llvm_v16i32_ty], 961 intr_properties>; 962 963// tag : V6_vscattermhq 964class Hexagon__v128i1i32i32v32i32v32i32_Intrinsic<string GCCIntSuffix, 965 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 966 : Hexagon_Intrinsic<GCCIntSuffix, 967 [], [llvm_v128i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v32i32_ty,llvm_v32i32_ty], 968 intr_properties>; 969 970// tag : V6_vscattermhw 971class Hexagon__i32i32v32i32v16i32_Intrinsic<string GCCIntSuffix, 972 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 973 : Hexagon_Intrinsic<GCCIntSuffix, 974 [], [llvm_i32_ty,llvm_i32_ty,llvm_v32i32_ty,llvm_v16i32_ty], 975 intr_properties>; 976 977// tag : V6_vscattermhw 978class Hexagon__i32i32v64i32v32i32_Intrinsic<string GCCIntSuffix, 979 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 980 : Hexagon_Intrinsic<GCCIntSuffix, 981 [], [llvm_i32_ty,llvm_i32_ty,llvm_v64i32_ty,llvm_v32i32_ty], 982 intr_properties>; 983 984// tag : V6_vscattermhwq 985class Hexagon__v64i1i32i32v32i32v16i32_Intrinsic<string GCCIntSuffix, 986 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 987 : Hexagon_Intrinsic<GCCIntSuffix, 988 [], [llvm_v64i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v32i32_ty,llvm_v16i32_ty], 989 intr_properties>; 990 991// tag : V6_vscattermhwq 992class Hexagon__v128i1i32i32v64i32v32i32_Intrinsic<string GCCIntSuffix, 993 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 994 : Hexagon_Intrinsic<GCCIntSuffix, 995 [], [llvm_v128i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v64i32_ty,llvm_v32i32_ty], 996 intr_properties>; 997 998// tag : V6_vswap 999class Hexagon_v32i32_v64i1v16i32v16i32_Intrinsic<string GCCIntSuffix, 1000 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 1001 : Hexagon_Intrinsic<GCCIntSuffix, 1002 [llvm_v32i32_ty], [llvm_v64i1_ty,llvm_v16i32_ty,llvm_v16i32_ty], 1003 intr_properties>; 1004 1005// tag : V6_vswap 1006class Hexagon_v64i32_v128i1v32i32v32i32_Intrinsic<string GCCIntSuffix, 1007 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 1008 : Hexagon_Intrinsic<GCCIntSuffix, 1009 [llvm_v64i32_ty], [llvm_v128i1_ty,llvm_v32i32_ty,llvm_v32i32_ty], 1010 intr_properties>; 1011 1012// tag : V6_vunpackob 1013class Hexagon_v32i32_v32i32v16i32_Intrinsic<string GCCIntSuffix, 1014 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 1015 : Hexagon_Intrinsic<GCCIntSuffix, 1016 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty], 1017 intr_properties>; 1018 1019// tag : V6_vunpackob 1020class Hexagon_v64i32_v64i32v32i32_Intrinsic<string GCCIntSuffix, 1021 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 1022 : Hexagon_Intrinsic<GCCIntSuffix, 1023 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty], 1024 intr_properties>; 1025 1026// tag : Y2_dccleana 1027class Hexagon__ptr_Intrinsic<string GCCIntSuffix, 1028 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 1029 : Hexagon_Intrinsic<GCCIntSuffix, 1030 [], [llvm_ptr_ty], 1031 intr_properties>; 1032 1033// tag : Y4_l2fetch 1034class Hexagon__ptri32_Intrinsic<string GCCIntSuffix, 1035 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 1036 : Hexagon_Intrinsic<GCCIntSuffix, 1037 [], [llvm_ptr_ty,llvm_i32_ty], 1038 intr_properties>; 1039 1040// tag : Y5_l2fetch 1041class Hexagon__ptri64_Intrinsic<string GCCIntSuffix, 1042 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 1043 : Hexagon_Intrinsic<GCCIntSuffix, 1044 [], [llvm_ptr_ty,llvm_i64_ty], 1045 intr_properties>; 1046 1047// tag : Y6_dmlink 1048class Hexagon__ptrptr_Intrinsic<string GCCIntSuffix, 1049 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 1050 : Hexagon_Intrinsic<GCCIntSuffix, 1051 [], [llvm_ptr_ty,llvm_ptr_ty], 1052 intr_properties>; 1053 1054// tag : Y6_dmpause 1055class Hexagon_i32__Intrinsic<string GCCIntSuffix, 1056 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 1057 : Hexagon_Intrinsic<GCCIntSuffix, 1058 [llvm_i32_ty], [], 1059 intr_properties>; 1060 1061// V5 Scalar Instructions. 1062 1063def int_hexagon_A2_abs : 1064Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_abs">; 1065 1066def int_hexagon_A2_absp : 1067Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_absp">; 1068 1069def int_hexagon_A2_abssat : 1070Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_abssat">; 1071 1072def int_hexagon_A2_add : 1073Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_add">; 1074 1075def int_hexagon_A2_addh_h16_hh : 1076Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_hh">; 1077 1078def int_hexagon_A2_addh_h16_hl : 1079Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_hl">; 1080 1081def int_hexagon_A2_addh_h16_lh : 1082Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_lh">; 1083 1084def int_hexagon_A2_addh_h16_ll : 1085Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_ll">; 1086 1087def int_hexagon_A2_addh_h16_sat_hh : 1088Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_hh">; 1089 1090def int_hexagon_A2_addh_h16_sat_hl : 1091Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_hl">; 1092 1093def int_hexagon_A2_addh_h16_sat_lh : 1094Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_lh">; 1095 1096def int_hexagon_A2_addh_h16_sat_ll : 1097Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_ll">; 1098 1099def int_hexagon_A2_addh_l16_hl : 1100Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_hl">; 1101 1102def int_hexagon_A2_addh_l16_ll : 1103Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_ll">; 1104 1105def int_hexagon_A2_addh_l16_sat_hl : 1106Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_sat_hl">; 1107 1108def int_hexagon_A2_addh_l16_sat_ll : 1109Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_sat_ll">; 1110 1111def int_hexagon_A2_addi : 1112Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1113 1114def int_hexagon_A2_addp : 1115Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_addp">; 1116 1117def int_hexagon_A2_addpsat : 1118Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_addpsat">; 1119 1120def int_hexagon_A2_addsat : 1121Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addsat">; 1122 1123def int_hexagon_A2_addsp : 1124Hexagon_i64_i32i64_Intrinsic<"HEXAGON_A2_addsp">; 1125 1126def int_hexagon_A2_and : 1127Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_and">; 1128 1129def int_hexagon_A2_andir : 1130Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_andir", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1131 1132def int_hexagon_A2_andp : 1133Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_andp">; 1134 1135def int_hexagon_A2_aslh : 1136Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_aslh">; 1137 1138def int_hexagon_A2_asrh : 1139Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_asrh">; 1140 1141def int_hexagon_A2_combine_hh : 1142Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_hh">; 1143 1144def int_hexagon_A2_combine_hl : 1145Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_hl">; 1146 1147def int_hexagon_A2_combine_lh : 1148Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_lh">; 1149 1150def int_hexagon_A2_combine_ll : 1151Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_ll">; 1152 1153def int_hexagon_A2_combineii : 1154Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A2_combineii", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>; 1155 1156def int_hexagon_A2_combinew : 1157Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A2_combinew">; 1158 1159def int_hexagon_A2_max : 1160Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_max">; 1161 1162def int_hexagon_A2_maxp : 1163Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_maxp">; 1164 1165def int_hexagon_A2_maxu : 1166Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_maxu">; 1167 1168def int_hexagon_A2_maxup : 1169Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_maxup">; 1170 1171def int_hexagon_A2_min : 1172Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_min">; 1173 1174def int_hexagon_A2_minp : 1175Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_minp">; 1176 1177def int_hexagon_A2_minu : 1178Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_minu">; 1179 1180def int_hexagon_A2_minup : 1181Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_minup">; 1182 1183def int_hexagon_A2_neg : 1184Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_neg">; 1185 1186def int_hexagon_A2_negp : 1187Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_negp">; 1188 1189def int_hexagon_A2_negsat : 1190Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_negsat">; 1191 1192def int_hexagon_A2_not : 1193Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_not">; 1194 1195def int_hexagon_A2_notp : 1196Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_notp">; 1197 1198def int_hexagon_A2_or : 1199Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_or">; 1200 1201def int_hexagon_A2_orir : 1202Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_orir", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1203 1204def int_hexagon_A2_orp : 1205Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_orp">; 1206 1207def int_hexagon_A2_roundsat : 1208Hexagon_i32_i64_Intrinsic<"HEXAGON_A2_roundsat">; 1209 1210def int_hexagon_A2_sat : 1211Hexagon_i32_i64_Intrinsic<"HEXAGON_A2_sat">; 1212 1213def int_hexagon_A2_satb : 1214Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_satb">; 1215 1216def int_hexagon_A2_sath : 1217Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_sath">; 1218 1219def int_hexagon_A2_satub : 1220Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_satub">; 1221 1222def int_hexagon_A2_satuh : 1223Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_satuh">; 1224 1225def int_hexagon_A2_sub : 1226Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_sub">; 1227 1228def int_hexagon_A2_subh_h16_hh : 1229Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_hh">; 1230 1231def int_hexagon_A2_subh_h16_hl : 1232Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_hl">; 1233 1234def int_hexagon_A2_subh_h16_lh : 1235Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_lh">; 1236 1237def int_hexagon_A2_subh_h16_ll : 1238Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_ll">; 1239 1240def int_hexagon_A2_subh_h16_sat_hh : 1241Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_hh">; 1242 1243def int_hexagon_A2_subh_h16_sat_hl : 1244Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_hl">; 1245 1246def int_hexagon_A2_subh_h16_sat_lh : 1247Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_lh">; 1248 1249def int_hexagon_A2_subh_h16_sat_ll : 1250Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_ll">; 1251 1252def int_hexagon_A2_subh_l16_hl : 1253Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_hl">; 1254 1255def int_hexagon_A2_subh_l16_ll : 1256Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_ll">; 1257 1258def int_hexagon_A2_subh_l16_sat_hl : 1259Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_sat_hl">; 1260 1261def int_hexagon_A2_subh_l16_sat_ll : 1262Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_sat_ll">; 1263 1264def int_hexagon_A2_subp : 1265Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_subp">; 1266 1267def int_hexagon_A2_subri : 1268Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subri", [IntrNoMem, ImmArg<ArgIndex<0>>]>; 1269 1270def int_hexagon_A2_subsat : 1271Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subsat">; 1272 1273def int_hexagon_A2_svaddh : 1274Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svaddh">; 1275 1276def int_hexagon_A2_svaddhs : 1277Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svaddhs">; 1278 1279def int_hexagon_A2_svadduhs : 1280Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svadduhs">; 1281 1282def int_hexagon_A2_svavgh : 1283Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svavgh">; 1284 1285def int_hexagon_A2_svavghs : 1286Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svavghs">; 1287 1288def int_hexagon_A2_svnavgh : 1289Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svnavgh">; 1290 1291def int_hexagon_A2_svsubh : 1292Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svsubh">; 1293 1294def int_hexagon_A2_svsubhs : 1295Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svsubhs">; 1296 1297def int_hexagon_A2_svsubuhs : 1298Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svsubuhs">; 1299 1300def int_hexagon_A2_swiz : 1301Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_swiz">; 1302 1303def int_hexagon_A2_sxtb : 1304Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_sxtb">; 1305 1306def int_hexagon_A2_sxth : 1307Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_sxth">; 1308 1309def int_hexagon_A2_sxtw : 1310Hexagon_i64_i32_Intrinsic<"HEXAGON_A2_sxtw">; 1311 1312def int_hexagon_A2_tfr : 1313Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_tfr">; 1314 1315def int_hexagon_A2_tfrih : 1316Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_tfrih", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1317 1318def int_hexagon_A2_tfril : 1319Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_tfril", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1320 1321def int_hexagon_A2_tfrp : 1322Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_tfrp">; 1323 1324def int_hexagon_A2_tfrpi : 1325Hexagon_i64_i32_Intrinsic<"HEXAGON_A2_tfrpi", [IntrNoMem, ImmArg<ArgIndex<0>>]>; 1326 1327def int_hexagon_A2_tfrsi : 1328Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_tfrsi", [IntrNoMem, ImmArg<ArgIndex<0>>]>; 1329 1330def int_hexagon_A2_vabsh : 1331Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabsh">; 1332 1333def int_hexagon_A2_vabshsat : 1334Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabshsat">; 1335 1336def int_hexagon_A2_vabsw : 1337Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabsw">; 1338 1339def int_hexagon_A2_vabswsat : 1340Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabswsat">; 1341 1342def int_hexagon_A2_vaddb_map : 1343Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddb_map">; 1344 1345def int_hexagon_A2_vaddh : 1346Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddh">; 1347 1348def int_hexagon_A2_vaddhs : 1349Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddhs">; 1350 1351def int_hexagon_A2_vaddub : 1352Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddub">; 1353 1354def int_hexagon_A2_vaddubs : 1355Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddubs">; 1356 1357def int_hexagon_A2_vadduhs : 1358Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vadduhs">; 1359 1360def int_hexagon_A2_vaddw : 1361Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddw">; 1362 1363def int_hexagon_A2_vaddws : 1364Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddws">; 1365 1366def int_hexagon_A2_vavgh : 1367Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgh">; 1368 1369def int_hexagon_A2_vavghcr : 1370Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavghcr">; 1371 1372def int_hexagon_A2_vavghr : 1373Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavghr">; 1374 1375def int_hexagon_A2_vavgub : 1376Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgub">; 1377 1378def int_hexagon_A2_vavgubr : 1379Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgubr">; 1380 1381def int_hexagon_A2_vavguh : 1382Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguh">; 1383 1384def int_hexagon_A2_vavguhr : 1385Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguhr">; 1386 1387def int_hexagon_A2_vavguw : 1388Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguw">; 1389 1390def int_hexagon_A2_vavguwr : 1391Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguwr">; 1392 1393def int_hexagon_A2_vavgw : 1394Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgw">; 1395 1396def int_hexagon_A2_vavgwcr : 1397Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgwcr">; 1398 1399def int_hexagon_A2_vavgwr : 1400Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgwr">; 1401 1402def int_hexagon_A2_vcmpbeq : 1403Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpbeq">; 1404 1405def int_hexagon_A2_vcmpbgtu : 1406Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpbgtu">; 1407 1408def int_hexagon_A2_vcmpheq : 1409Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpheq">; 1410 1411def int_hexagon_A2_vcmphgt : 1412Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmphgt">; 1413 1414def int_hexagon_A2_vcmphgtu : 1415Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmphgtu">; 1416 1417def int_hexagon_A2_vcmpweq : 1418Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpweq">; 1419 1420def int_hexagon_A2_vcmpwgt : 1421Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpwgt">; 1422 1423def int_hexagon_A2_vcmpwgtu : 1424Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpwgtu">; 1425 1426def int_hexagon_A2_vconj : 1427Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vconj">; 1428 1429def int_hexagon_A2_vmaxb : 1430Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxb">; 1431 1432def int_hexagon_A2_vmaxh : 1433Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxh">; 1434 1435def int_hexagon_A2_vmaxub : 1436Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxub">; 1437 1438def int_hexagon_A2_vmaxuh : 1439Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxuh">; 1440 1441def int_hexagon_A2_vmaxuw : 1442Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxuw">; 1443 1444def int_hexagon_A2_vmaxw : 1445Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxw">; 1446 1447def int_hexagon_A2_vminb : 1448Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminb">; 1449 1450def int_hexagon_A2_vminh : 1451Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminh">; 1452 1453def int_hexagon_A2_vminub : 1454Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminub">; 1455 1456def int_hexagon_A2_vminuh : 1457Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminuh">; 1458 1459def int_hexagon_A2_vminuw : 1460Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminuw">; 1461 1462def int_hexagon_A2_vminw : 1463Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminw">; 1464 1465def int_hexagon_A2_vnavgh : 1466Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgh">; 1467 1468def int_hexagon_A2_vnavghcr : 1469Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavghcr">; 1470 1471def int_hexagon_A2_vnavghr : 1472Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavghr">; 1473 1474def int_hexagon_A2_vnavgw : 1475Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgw">; 1476 1477def int_hexagon_A2_vnavgwcr : 1478Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgwcr">; 1479 1480def int_hexagon_A2_vnavgwr : 1481Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgwr">; 1482 1483def int_hexagon_A2_vraddub : 1484Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vraddub">; 1485 1486def int_hexagon_A2_vraddub_acc : 1487Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_A2_vraddub_acc">; 1488 1489def int_hexagon_A2_vrsadub : 1490Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vrsadub">; 1491 1492def int_hexagon_A2_vrsadub_acc : 1493Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_A2_vrsadub_acc">; 1494 1495def int_hexagon_A2_vsubb_map : 1496Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubb_map">; 1497 1498def int_hexagon_A2_vsubh : 1499Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubh">; 1500 1501def int_hexagon_A2_vsubhs : 1502Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubhs">; 1503 1504def int_hexagon_A2_vsubub : 1505Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubub">; 1506 1507def int_hexagon_A2_vsububs : 1508Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsububs">; 1509 1510def int_hexagon_A2_vsubuhs : 1511Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubuhs">; 1512 1513def int_hexagon_A2_vsubw : 1514Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubw">; 1515 1516def int_hexagon_A2_vsubws : 1517Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubws">; 1518 1519def int_hexagon_A2_xor : 1520Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_xor">; 1521 1522def int_hexagon_A2_xorp : 1523Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_xorp">; 1524 1525def int_hexagon_A2_zxtb : 1526Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_zxtb">; 1527 1528def int_hexagon_A2_zxth : 1529Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_zxth">; 1530 1531def int_hexagon_A4_andn : 1532Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_andn">; 1533 1534def int_hexagon_A4_andnp : 1535Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A4_andnp">; 1536 1537def int_hexagon_A4_bitsplit : 1538Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_bitsplit">; 1539 1540def int_hexagon_A4_bitspliti : 1541Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_bitspliti", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1542 1543def int_hexagon_A4_boundscheck : 1544Hexagon_i32_i32i64_Intrinsic<"HEXAGON_A4_boundscheck">; 1545 1546def int_hexagon_A4_cmpbeq : 1547Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbeq">; 1548 1549def int_hexagon_A4_cmpbeqi : 1550Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbeqi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1551 1552def int_hexagon_A4_cmpbgt : 1553Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgt">; 1554 1555def int_hexagon_A4_cmpbgti : 1556Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgti", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1557 1558def int_hexagon_A4_cmpbgtu : 1559Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgtu">; 1560 1561def int_hexagon_A4_cmpbgtui : 1562Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgtui", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1563 1564def int_hexagon_A4_cmpheq : 1565Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpheq">; 1566 1567def int_hexagon_A4_cmpheqi : 1568Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpheqi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1569 1570def int_hexagon_A4_cmphgt : 1571Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgt">; 1572 1573def int_hexagon_A4_cmphgti : 1574Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgti", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1575 1576def int_hexagon_A4_cmphgtu : 1577Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgtu">; 1578 1579def int_hexagon_A4_cmphgtui : 1580Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgtui", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1581 1582def int_hexagon_A4_combineir : 1583Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_combineir", [IntrNoMem, ImmArg<ArgIndex<0>>]>; 1584 1585def int_hexagon_A4_combineri : 1586Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_combineri", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1587 1588def int_hexagon_A4_cround_ri : 1589Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cround_ri", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1590 1591def int_hexagon_A4_cround_rr : 1592Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cround_rr">; 1593 1594def int_hexagon_A4_modwrapu : 1595Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_modwrapu">; 1596 1597def int_hexagon_A4_orn : 1598Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_orn">; 1599 1600def int_hexagon_A4_ornp : 1601Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A4_ornp">; 1602 1603def int_hexagon_A4_rcmpeq : 1604Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpeq">; 1605 1606def int_hexagon_A4_rcmpeqi : 1607Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpeqi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1608 1609def int_hexagon_A4_rcmpneq : 1610Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpneq">; 1611 1612def int_hexagon_A4_rcmpneqi : 1613Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpneqi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1614 1615def int_hexagon_A4_round_ri : 1616Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_ri", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1617 1618def int_hexagon_A4_round_ri_sat : 1619Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_ri_sat", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1620 1621def int_hexagon_A4_round_rr : 1622Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_rr">; 1623 1624def int_hexagon_A4_round_rr_sat : 1625Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_rr_sat">; 1626 1627def int_hexagon_A4_tlbmatch : 1628Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_tlbmatch">; 1629 1630def int_hexagon_A4_vcmpbeq_any : 1631Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A4_vcmpbeq_any">; 1632 1633def int_hexagon_A4_vcmpbeqi : 1634Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpbeqi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1635 1636def int_hexagon_A4_vcmpbgt : 1637Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A4_vcmpbgt">; 1638 1639def int_hexagon_A4_vcmpbgti : 1640Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpbgti", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1641 1642def int_hexagon_A4_vcmpbgtui : 1643Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpbgtui", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1644 1645def int_hexagon_A4_vcmpheqi : 1646Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpheqi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1647 1648def int_hexagon_A4_vcmphgti : 1649Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmphgti", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1650 1651def int_hexagon_A4_vcmphgtui : 1652Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmphgtui", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1653 1654def int_hexagon_A4_vcmpweqi : 1655Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpweqi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1656 1657def int_hexagon_A4_vcmpwgti : 1658Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpwgti", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1659 1660def int_hexagon_A4_vcmpwgtui : 1661Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpwgtui", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1662 1663def int_hexagon_A4_vrmaxh : 1664Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxh">; 1665 1666def int_hexagon_A4_vrmaxuh : 1667Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxuh">; 1668 1669def int_hexagon_A4_vrmaxuw : 1670Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxuw">; 1671 1672def int_hexagon_A4_vrmaxw : 1673Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxw">; 1674 1675def int_hexagon_A4_vrminh : 1676Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminh">; 1677 1678def int_hexagon_A4_vrminuh : 1679Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminuh">; 1680 1681def int_hexagon_A4_vrminuw : 1682Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminuw">; 1683 1684def int_hexagon_A4_vrminw : 1685Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminw">; 1686 1687def int_hexagon_A5_vaddhubs : 1688Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A5_vaddhubs">; 1689 1690def int_hexagon_C2_all8 : 1691Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_all8">; 1692 1693def int_hexagon_C2_and : 1694Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_and">; 1695 1696def int_hexagon_C2_andn : 1697Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_andn">; 1698 1699def int_hexagon_C2_any8 : 1700Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_any8">; 1701 1702def int_hexagon_C2_bitsclr : 1703Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_bitsclr">; 1704 1705def int_hexagon_C2_bitsclri : 1706Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_bitsclri", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1707 1708def int_hexagon_C2_bitsset : 1709Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_bitsset">; 1710 1711def int_hexagon_C2_cmpeq : 1712Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpeq">; 1713 1714def int_hexagon_C2_cmpeqi : 1715Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpeqi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1716 1717def int_hexagon_C2_cmpeqp : 1718Hexagon_i32_i64i64_Intrinsic<"HEXAGON_C2_cmpeqp">; 1719 1720def int_hexagon_C2_cmpgei : 1721Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgei", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1722 1723def int_hexagon_C2_cmpgeui : 1724Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgeui", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1725 1726def int_hexagon_C2_cmpgt : 1727Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgt">; 1728 1729def int_hexagon_C2_cmpgti : 1730Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgti", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1731 1732def int_hexagon_C2_cmpgtp : 1733Hexagon_i32_i64i64_Intrinsic<"HEXAGON_C2_cmpgtp">; 1734 1735def int_hexagon_C2_cmpgtu : 1736Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgtu">; 1737 1738def int_hexagon_C2_cmpgtui : 1739Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgtui", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1740 1741def int_hexagon_C2_cmpgtup : 1742Hexagon_i32_i64i64_Intrinsic<"HEXAGON_C2_cmpgtup">; 1743 1744def int_hexagon_C2_cmplt : 1745Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmplt">; 1746 1747def int_hexagon_C2_cmpltu : 1748Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpltu">; 1749 1750def int_hexagon_C2_mask : 1751Hexagon_i64_i32_Intrinsic<"HEXAGON_C2_mask">; 1752 1753def int_hexagon_C2_mux : 1754Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_mux">; 1755 1756def int_hexagon_C2_muxii : 1757Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_muxii", [IntrNoMem, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>; 1758 1759def int_hexagon_C2_muxir : 1760Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_muxir", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 1761 1762def int_hexagon_C2_muxri : 1763Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_muxri", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1764 1765def int_hexagon_C2_not : 1766Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_not">; 1767 1768def int_hexagon_C2_or : 1769Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_or">; 1770 1771def int_hexagon_C2_orn : 1772Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_orn">; 1773 1774def int_hexagon_C2_pxfer_map : 1775Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_pxfer_map">; 1776 1777def int_hexagon_C2_tfrpr : 1778Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_tfrpr">; 1779 1780def int_hexagon_C2_tfrrp : 1781Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_tfrrp">; 1782 1783def int_hexagon_C2_vitpack : 1784Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_vitpack">; 1785 1786def int_hexagon_C2_vmux : 1787Hexagon_i64_i32i64i64_Intrinsic<"HEXAGON_C2_vmux">; 1788 1789def int_hexagon_C2_xor : 1790Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_xor">; 1791 1792def int_hexagon_C4_and_and : 1793Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_and">; 1794 1795def int_hexagon_C4_and_andn : 1796Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_andn">; 1797 1798def int_hexagon_C4_and_or : 1799Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_or">; 1800 1801def int_hexagon_C4_and_orn : 1802Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_orn">; 1803 1804def int_hexagon_C4_cmplte : 1805Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmplte">; 1806 1807def int_hexagon_C4_cmpltei : 1808Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmpltei", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1809 1810def int_hexagon_C4_cmplteu : 1811Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmplteu">; 1812 1813def int_hexagon_C4_cmplteui : 1814Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmplteui", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1815 1816def int_hexagon_C4_cmpneq : 1817Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmpneq">; 1818 1819def int_hexagon_C4_cmpneqi : 1820Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmpneqi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1821 1822def int_hexagon_C4_fastcorner9 : 1823Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_fastcorner9">; 1824 1825def int_hexagon_C4_fastcorner9_not : 1826Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_fastcorner9_not">; 1827 1828def int_hexagon_C4_nbitsclr : 1829Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_nbitsclr">; 1830 1831def int_hexagon_C4_nbitsclri : 1832Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_nbitsclri", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1833 1834def int_hexagon_C4_nbitsset : 1835Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_nbitsset">; 1836 1837def int_hexagon_C4_or_and : 1838Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_and">; 1839 1840def int_hexagon_C4_or_andn : 1841Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_andn">; 1842 1843def int_hexagon_C4_or_or : 1844Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_or">; 1845 1846def int_hexagon_C4_or_orn : 1847Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_orn">; 1848 1849def int_hexagon_F2_conv_d2df : 1850Hexagon_double_i64_Intrinsic<"HEXAGON_F2_conv_d2df">; 1851 1852def int_hexagon_F2_conv_d2sf : 1853Hexagon_float_i64_Intrinsic<"HEXAGON_F2_conv_d2sf">; 1854 1855def int_hexagon_F2_conv_df2d : 1856Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2d">; 1857 1858def int_hexagon_F2_conv_df2d_chop : 1859Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2d_chop">; 1860 1861def int_hexagon_F2_conv_df2sf : 1862Hexagon_float_double_Intrinsic<"HEXAGON_F2_conv_df2sf">; 1863 1864def int_hexagon_F2_conv_df2ud : 1865Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2ud">; 1866 1867def int_hexagon_F2_conv_df2ud_chop : 1868Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2ud_chop">; 1869 1870def int_hexagon_F2_conv_df2uw : 1871Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2uw">; 1872 1873def int_hexagon_F2_conv_df2uw_chop : 1874Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2uw_chop">; 1875 1876def int_hexagon_F2_conv_df2w : 1877Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2w">; 1878 1879def int_hexagon_F2_conv_df2w_chop : 1880Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2w_chop">; 1881 1882def int_hexagon_F2_conv_sf2d : 1883Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2d">; 1884 1885def int_hexagon_F2_conv_sf2d_chop : 1886Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2d_chop">; 1887 1888def int_hexagon_F2_conv_sf2df : 1889Hexagon_double_float_Intrinsic<"HEXAGON_F2_conv_sf2df">; 1890 1891def int_hexagon_F2_conv_sf2ud : 1892Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2ud">; 1893 1894def int_hexagon_F2_conv_sf2ud_chop : 1895Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2ud_chop">; 1896 1897def int_hexagon_F2_conv_sf2uw : 1898Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2uw">; 1899 1900def int_hexagon_F2_conv_sf2uw_chop : 1901Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2uw_chop">; 1902 1903def int_hexagon_F2_conv_sf2w : 1904Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2w">; 1905 1906def int_hexagon_F2_conv_sf2w_chop : 1907Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2w_chop">; 1908 1909def int_hexagon_F2_conv_ud2df : 1910Hexagon_double_i64_Intrinsic<"HEXAGON_F2_conv_ud2df">; 1911 1912def int_hexagon_F2_conv_ud2sf : 1913Hexagon_float_i64_Intrinsic<"HEXAGON_F2_conv_ud2sf">; 1914 1915def int_hexagon_F2_conv_uw2df : 1916Hexagon_double_i32_Intrinsic<"HEXAGON_F2_conv_uw2df">; 1917 1918def int_hexagon_F2_conv_uw2sf : 1919Hexagon_float_i32_Intrinsic<"HEXAGON_F2_conv_uw2sf">; 1920 1921def int_hexagon_F2_conv_w2df : 1922Hexagon_double_i32_Intrinsic<"HEXAGON_F2_conv_w2df">; 1923 1924def int_hexagon_F2_conv_w2sf : 1925Hexagon_float_i32_Intrinsic<"HEXAGON_F2_conv_w2sf">; 1926 1927def int_hexagon_F2_dfclass : 1928Hexagon_i32_doublei32_Intrinsic<"HEXAGON_F2_dfclass", [IntrNoMem, Throws, ImmArg<ArgIndex<1>>]>; 1929 1930def int_hexagon_F2_dfcmpeq : 1931Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpeq", [IntrNoMem, Throws]>; 1932 1933def int_hexagon_F2_dfcmpge : 1934Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpge", [IntrNoMem, Throws]>; 1935 1936def int_hexagon_F2_dfcmpgt : 1937Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpgt", [IntrNoMem, Throws]>; 1938 1939def int_hexagon_F2_dfcmpuo : 1940Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpuo", [IntrNoMem, Throws]>; 1941 1942def int_hexagon_F2_dfimm_n : 1943Hexagon_double_i32_Intrinsic<"HEXAGON_F2_dfimm_n", [IntrNoMem, Throws, ImmArg<ArgIndex<0>>]>; 1944 1945def int_hexagon_F2_dfimm_p : 1946Hexagon_double_i32_Intrinsic<"HEXAGON_F2_dfimm_p", [IntrNoMem, Throws, ImmArg<ArgIndex<0>>]>; 1947 1948def int_hexagon_F2_sfadd : 1949Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfadd", [IntrNoMem, Throws]>; 1950 1951def int_hexagon_F2_sfclass : 1952Hexagon_i32_floati32_Intrinsic<"HEXAGON_F2_sfclass", [IntrNoMem, Throws, ImmArg<ArgIndex<1>>]>; 1953 1954def int_hexagon_F2_sfcmpeq : 1955Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpeq", [IntrNoMem, Throws]>; 1956 1957def int_hexagon_F2_sfcmpge : 1958Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpge", [IntrNoMem, Throws]>; 1959 1960def int_hexagon_F2_sfcmpgt : 1961Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpgt", [IntrNoMem, Throws]>; 1962 1963def int_hexagon_F2_sfcmpuo : 1964Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpuo", [IntrNoMem, Throws]>; 1965 1966def int_hexagon_F2_sffixupd : 1967Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sffixupd", [IntrNoMem, Throws]>; 1968 1969def int_hexagon_F2_sffixupn : 1970Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sffixupn", [IntrNoMem, Throws]>; 1971 1972def int_hexagon_F2_sffixupr : 1973Hexagon_float_float_Intrinsic<"HEXAGON_F2_sffixupr", [IntrNoMem, Throws]>; 1974 1975def int_hexagon_F2_sffma : 1976Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffma", [IntrNoMem, Throws]>; 1977 1978def int_hexagon_F2_sffma_lib : 1979Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffma_lib", [IntrNoMem, Throws]>; 1980 1981def int_hexagon_F2_sffma_sc : 1982Hexagon_float_floatfloatfloati32_Intrinsic<"HEXAGON_F2_sffma_sc", [IntrNoMem, Throws]>; 1983 1984def int_hexagon_F2_sffms : 1985Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffms", [IntrNoMem, Throws]>; 1986 1987def int_hexagon_F2_sffms_lib : 1988Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffms_lib", [IntrNoMem, Throws]>; 1989 1990def int_hexagon_F2_sfimm_n : 1991Hexagon_float_i32_Intrinsic<"HEXAGON_F2_sfimm_n", [IntrNoMem, Throws, ImmArg<ArgIndex<0>>]>; 1992 1993def int_hexagon_F2_sfimm_p : 1994Hexagon_float_i32_Intrinsic<"HEXAGON_F2_sfimm_p", [IntrNoMem, Throws, ImmArg<ArgIndex<0>>]>; 1995 1996def int_hexagon_F2_sfmax : 1997Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfmax", [IntrNoMem, Throws]>; 1998 1999def int_hexagon_F2_sfmin : 2000Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfmin", [IntrNoMem, Throws]>; 2001 2002def int_hexagon_F2_sfmpy : 2003Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfmpy", [IntrNoMem, Throws]>; 2004 2005def int_hexagon_F2_sfsub : 2006Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfsub", [IntrNoMem, Throws]>; 2007 2008def int_hexagon_M2_acci : 2009Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_acci">; 2010 2011def int_hexagon_M2_accii : 2012Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_accii", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2013 2014def int_hexagon_M2_cmaci_s0 : 2015Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmaci_s0">; 2016 2017def int_hexagon_M2_cmacr_s0 : 2018Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacr_s0">; 2019 2020def int_hexagon_M2_cmacs_s0 : 2021Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacs_s0">; 2022 2023def int_hexagon_M2_cmacs_s1 : 2024Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacs_s1">; 2025 2026def int_hexagon_M2_cmacsc_s0 : 2027Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacsc_s0">; 2028 2029def int_hexagon_M2_cmacsc_s1 : 2030Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacsc_s1">; 2031 2032def int_hexagon_M2_cmpyi_s0 : 2033Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpyi_s0">; 2034 2035def int_hexagon_M2_cmpyr_s0 : 2036Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpyr_s0">; 2037 2038def int_hexagon_M2_cmpyrs_s0 : 2039Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrs_s0">; 2040 2041def int_hexagon_M2_cmpyrs_s1 : 2042Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrs_s1">; 2043 2044def int_hexagon_M2_cmpyrsc_s0 : 2045Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrsc_s0">; 2046 2047def int_hexagon_M2_cmpyrsc_s1 : 2048Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrsc_s1">; 2049 2050def int_hexagon_M2_cmpys_s0 : 2051Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpys_s0">; 2052 2053def int_hexagon_M2_cmpys_s1 : 2054Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpys_s1">; 2055 2056def int_hexagon_M2_cmpysc_s0 : 2057Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpysc_s0">; 2058 2059def int_hexagon_M2_cmpysc_s1 : 2060Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpysc_s1">; 2061 2062def int_hexagon_M2_cnacs_s0 : 2063Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacs_s0">; 2064 2065def int_hexagon_M2_cnacs_s1 : 2066Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacs_s1">; 2067 2068def int_hexagon_M2_cnacsc_s0 : 2069Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacsc_s0">; 2070 2071def int_hexagon_M2_cnacsc_s1 : 2072Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacsc_s1">; 2073 2074def int_hexagon_M2_dpmpyss_acc_s0 : 2075Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_acc_s0">; 2076 2077def int_hexagon_M2_dpmpyss_nac_s0 : 2078Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_nac_s0">; 2079 2080def int_hexagon_M2_dpmpyss_rnd_s0 : 2081Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_rnd_s0">; 2082 2083def int_hexagon_M2_dpmpyss_s0 : 2084Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_s0">; 2085 2086def int_hexagon_M2_dpmpyuu_acc_s0 : 2087Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyuu_acc_s0">; 2088 2089def int_hexagon_M2_dpmpyuu_nac_s0 : 2090Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyuu_nac_s0">; 2091 2092def int_hexagon_M2_dpmpyuu_s0 : 2093Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_dpmpyuu_s0">; 2094 2095def int_hexagon_M2_hmmpyh_rs1 : 2096Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyh_rs1">; 2097 2098def int_hexagon_M2_hmmpyh_s1 : 2099Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyh_s1">; 2100 2101def int_hexagon_M2_hmmpyl_rs1 : 2102Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyl_rs1">; 2103 2104def int_hexagon_M2_hmmpyl_s1 : 2105Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyl_s1">; 2106 2107def int_hexagon_M2_maci : 2108Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_maci">; 2109 2110def int_hexagon_M2_macsin : 2111Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_macsin", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2112 2113def int_hexagon_M2_macsip : 2114Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_macsip", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2115 2116def int_hexagon_M2_mmachs_rs0 : 2117Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_rs0">; 2118 2119def int_hexagon_M2_mmachs_rs1 : 2120Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_rs1">; 2121 2122def int_hexagon_M2_mmachs_s0 : 2123Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_s0">; 2124 2125def int_hexagon_M2_mmachs_s1 : 2126Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_s1">; 2127 2128def int_hexagon_M2_mmacls_rs0 : 2129Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_rs0">; 2130 2131def int_hexagon_M2_mmacls_rs1 : 2132Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_rs1">; 2133 2134def int_hexagon_M2_mmacls_s0 : 2135Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_s0">; 2136 2137def int_hexagon_M2_mmacls_s1 : 2138Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_s1">; 2139 2140def int_hexagon_M2_mmacuhs_rs0 : 2141Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_rs0">; 2142 2143def int_hexagon_M2_mmacuhs_rs1 : 2144Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_rs1">; 2145 2146def int_hexagon_M2_mmacuhs_s0 : 2147Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_s0">; 2148 2149def int_hexagon_M2_mmacuhs_s1 : 2150Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_s1">; 2151 2152def int_hexagon_M2_mmaculs_rs0 : 2153Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_rs0">; 2154 2155def int_hexagon_M2_mmaculs_rs1 : 2156Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_rs1">; 2157 2158def int_hexagon_M2_mmaculs_s0 : 2159Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_s0">; 2160 2161def int_hexagon_M2_mmaculs_s1 : 2162Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_s1">; 2163 2164def int_hexagon_M2_mmpyh_rs0 : 2165Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_rs0">; 2166 2167def int_hexagon_M2_mmpyh_rs1 : 2168Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_rs1">; 2169 2170def int_hexagon_M2_mmpyh_s0 : 2171Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_s0">; 2172 2173def int_hexagon_M2_mmpyh_s1 : 2174Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_s1">; 2175 2176def int_hexagon_M2_mmpyl_rs0 : 2177Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_rs0">; 2178 2179def int_hexagon_M2_mmpyl_rs1 : 2180Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_rs1">; 2181 2182def int_hexagon_M2_mmpyl_s0 : 2183Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_s0">; 2184 2185def int_hexagon_M2_mmpyl_s1 : 2186Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_s1">; 2187 2188def int_hexagon_M2_mmpyuh_rs0 : 2189Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_rs0">; 2190 2191def int_hexagon_M2_mmpyuh_rs1 : 2192Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_rs1">; 2193 2194def int_hexagon_M2_mmpyuh_s0 : 2195Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_s0">; 2196 2197def int_hexagon_M2_mmpyuh_s1 : 2198Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_s1">; 2199 2200def int_hexagon_M2_mmpyul_rs0 : 2201Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_rs0">; 2202 2203def int_hexagon_M2_mmpyul_rs1 : 2204Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_rs1">; 2205 2206def int_hexagon_M2_mmpyul_s0 : 2207Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_s0">; 2208 2209def int_hexagon_M2_mmpyul_s1 : 2210Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_s1">; 2211 2212def int_hexagon_M2_mpy_acc_hh_s0 : 2213Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hh_s0">; 2214 2215def int_hexagon_M2_mpy_acc_hh_s1 : 2216Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hh_s1">; 2217 2218def int_hexagon_M2_mpy_acc_hl_s0 : 2219Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hl_s0">; 2220 2221def int_hexagon_M2_mpy_acc_hl_s1 : 2222Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hl_s1">; 2223 2224def int_hexagon_M2_mpy_acc_lh_s0 : 2225Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_lh_s0">; 2226 2227def int_hexagon_M2_mpy_acc_lh_s1 : 2228Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_lh_s1">; 2229 2230def int_hexagon_M2_mpy_acc_ll_s0 : 2231Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_ll_s0">; 2232 2233def int_hexagon_M2_mpy_acc_ll_s1 : 2234Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_ll_s1">; 2235 2236def int_hexagon_M2_mpy_acc_sat_hh_s0 : 2237Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hh_s0">; 2238 2239def int_hexagon_M2_mpy_acc_sat_hh_s1 : 2240Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hh_s1">; 2241 2242def int_hexagon_M2_mpy_acc_sat_hl_s0 : 2243Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hl_s0">; 2244 2245def int_hexagon_M2_mpy_acc_sat_hl_s1 : 2246Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hl_s1">; 2247 2248def int_hexagon_M2_mpy_acc_sat_lh_s0 : 2249Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_lh_s0">; 2250 2251def int_hexagon_M2_mpy_acc_sat_lh_s1 : 2252Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_lh_s1">; 2253 2254def int_hexagon_M2_mpy_acc_sat_ll_s0 : 2255Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_ll_s0">; 2256 2257def int_hexagon_M2_mpy_acc_sat_ll_s1 : 2258Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_ll_s1">; 2259 2260def int_hexagon_M2_mpy_hh_s0 : 2261Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hh_s0">; 2262 2263def int_hexagon_M2_mpy_hh_s1 : 2264Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hh_s1">; 2265 2266def int_hexagon_M2_mpy_hl_s0 : 2267Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hl_s0">; 2268 2269def int_hexagon_M2_mpy_hl_s1 : 2270Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hl_s1">; 2271 2272def int_hexagon_M2_mpy_lh_s0 : 2273Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_lh_s0">; 2274 2275def int_hexagon_M2_mpy_lh_s1 : 2276Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_lh_s1">; 2277 2278def int_hexagon_M2_mpy_ll_s0 : 2279Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_ll_s0">; 2280 2281def int_hexagon_M2_mpy_ll_s1 : 2282Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_ll_s1">; 2283 2284def int_hexagon_M2_mpy_nac_hh_s0 : 2285Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hh_s0">; 2286 2287def int_hexagon_M2_mpy_nac_hh_s1 : 2288Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hh_s1">; 2289 2290def int_hexagon_M2_mpy_nac_hl_s0 : 2291Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hl_s0">; 2292 2293def int_hexagon_M2_mpy_nac_hl_s1 : 2294Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hl_s1">; 2295 2296def int_hexagon_M2_mpy_nac_lh_s0 : 2297Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_lh_s0">; 2298 2299def int_hexagon_M2_mpy_nac_lh_s1 : 2300Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_lh_s1">; 2301 2302def int_hexagon_M2_mpy_nac_ll_s0 : 2303Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_ll_s0">; 2304 2305def int_hexagon_M2_mpy_nac_ll_s1 : 2306Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_ll_s1">; 2307 2308def int_hexagon_M2_mpy_nac_sat_hh_s0 : 2309Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hh_s0">; 2310 2311def int_hexagon_M2_mpy_nac_sat_hh_s1 : 2312Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hh_s1">; 2313 2314def int_hexagon_M2_mpy_nac_sat_hl_s0 : 2315Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hl_s0">; 2316 2317def int_hexagon_M2_mpy_nac_sat_hl_s1 : 2318Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hl_s1">; 2319 2320def int_hexagon_M2_mpy_nac_sat_lh_s0 : 2321Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_lh_s0">; 2322 2323def int_hexagon_M2_mpy_nac_sat_lh_s1 : 2324Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_lh_s1">; 2325 2326def int_hexagon_M2_mpy_nac_sat_ll_s0 : 2327Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_ll_s0">; 2328 2329def int_hexagon_M2_mpy_nac_sat_ll_s1 : 2330Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_ll_s1">; 2331 2332def int_hexagon_M2_mpy_rnd_hh_s0 : 2333Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hh_s0">; 2334 2335def int_hexagon_M2_mpy_rnd_hh_s1 : 2336Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hh_s1">; 2337 2338def int_hexagon_M2_mpy_rnd_hl_s0 : 2339Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hl_s0">; 2340 2341def int_hexagon_M2_mpy_rnd_hl_s1 : 2342Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hl_s1">; 2343 2344def int_hexagon_M2_mpy_rnd_lh_s0 : 2345Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_lh_s0">; 2346 2347def int_hexagon_M2_mpy_rnd_lh_s1 : 2348Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_lh_s1">; 2349 2350def int_hexagon_M2_mpy_rnd_ll_s0 : 2351Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_ll_s0">; 2352 2353def int_hexagon_M2_mpy_rnd_ll_s1 : 2354Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_ll_s1">; 2355 2356def int_hexagon_M2_mpy_sat_hh_s0 : 2357Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hh_s0">; 2358 2359def int_hexagon_M2_mpy_sat_hh_s1 : 2360Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hh_s1">; 2361 2362def int_hexagon_M2_mpy_sat_hl_s0 : 2363Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hl_s0">; 2364 2365def int_hexagon_M2_mpy_sat_hl_s1 : 2366Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hl_s1">; 2367 2368def int_hexagon_M2_mpy_sat_lh_s0 : 2369Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_lh_s0">; 2370 2371def int_hexagon_M2_mpy_sat_lh_s1 : 2372Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_lh_s1">; 2373 2374def int_hexagon_M2_mpy_sat_ll_s0 : 2375Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_ll_s0">; 2376 2377def int_hexagon_M2_mpy_sat_ll_s1 : 2378Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_ll_s1">; 2379 2380def int_hexagon_M2_mpy_sat_rnd_hh_s0 : 2381Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hh_s0">; 2382 2383def int_hexagon_M2_mpy_sat_rnd_hh_s1 : 2384Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hh_s1">; 2385 2386def int_hexagon_M2_mpy_sat_rnd_hl_s0 : 2387Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hl_s0">; 2388 2389def int_hexagon_M2_mpy_sat_rnd_hl_s1 : 2390Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hl_s1">; 2391 2392def int_hexagon_M2_mpy_sat_rnd_lh_s0 : 2393Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_lh_s0">; 2394 2395def int_hexagon_M2_mpy_sat_rnd_lh_s1 : 2396Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_lh_s1">; 2397 2398def int_hexagon_M2_mpy_sat_rnd_ll_s0 : 2399Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_ll_s0">; 2400 2401def int_hexagon_M2_mpy_sat_rnd_ll_s1 : 2402Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_ll_s1">; 2403 2404def int_hexagon_M2_mpy_up : 2405Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_up">; 2406 2407def int_hexagon_M2_mpy_up_s1 : 2408Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_up_s1">; 2409 2410def int_hexagon_M2_mpy_up_s1_sat : 2411Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_up_s1_sat">; 2412 2413def int_hexagon_M2_mpyd_acc_hh_s0 : 2414Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hh_s0">; 2415 2416def int_hexagon_M2_mpyd_acc_hh_s1 : 2417Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hh_s1">; 2418 2419def int_hexagon_M2_mpyd_acc_hl_s0 : 2420Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hl_s0">; 2421 2422def int_hexagon_M2_mpyd_acc_hl_s1 : 2423Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hl_s1">; 2424 2425def int_hexagon_M2_mpyd_acc_lh_s0 : 2426Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_lh_s0">; 2427 2428def int_hexagon_M2_mpyd_acc_lh_s1 : 2429Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_lh_s1">; 2430 2431def int_hexagon_M2_mpyd_acc_ll_s0 : 2432Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_ll_s0">; 2433 2434def int_hexagon_M2_mpyd_acc_ll_s1 : 2435Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_ll_s1">; 2436 2437def int_hexagon_M2_mpyd_hh_s0 : 2438Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hh_s0">; 2439 2440def int_hexagon_M2_mpyd_hh_s1 : 2441Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hh_s1">; 2442 2443def int_hexagon_M2_mpyd_hl_s0 : 2444Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hl_s0">; 2445 2446def int_hexagon_M2_mpyd_hl_s1 : 2447Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hl_s1">; 2448 2449def int_hexagon_M2_mpyd_lh_s0 : 2450Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_lh_s0">; 2451 2452def int_hexagon_M2_mpyd_lh_s1 : 2453Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_lh_s1">; 2454 2455def int_hexagon_M2_mpyd_ll_s0 : 2456Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_ll_s0">; 2457 2458def int_hexagon_M2_mpyd_ll_s1 : 2459Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_ll_s1">; 2460 2461def int_hexagon_M2_mpyd_nac_hh_s0 : 2462Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hh_s0">; 2463 2464def int_hexagon_M2_mpyd_nac_hh_s1 : 2465Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hh_s1">; 2466 2467def int_hexagon_M2_mpyd_nac_hl_s0 : 2468Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hl_s0">; 2469 2470def int_hexagon_M2_mpyd_nac_hl_s1 : 2471Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hl_s1">; 2472 2473def int_hexagon_M2_mpyd_nac_lh_s0 : 2474Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_lh_s0">; 2475 2476def int_hexagon_M2_mpyd_nac_lh_s1 : 2477Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_lh_s1">; 2478 2479def int_hexagon_M2_mpyd_nac_ll_s0 : 2480Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_ll_s0">; 2481 2482def int_hexagon_M2_mpyd_nac_ll_s1 : 2483Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_ll_s1">; 2484 2485def int_hexagon_M2_mpyd_rnd_hh_s0 : 2486Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hh_s0">; 2487 2488def int_hexagon_M2_mpyd_rnd_hh_s1 : 2489Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hh_s1">; 2490 2491def int_hexagon_M2_mpyd_rnd_hl_s0 : 2492Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hl_s0">; 2493 2494def int_hexagon_M2_mpyd_rnd_hl_s1 : 2495Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hl_s1">; 2496 2497def int_hexagon_M2_mpyd_rnd_lh_s0 : 2498Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_lh_s0">; 2499 2500def int_hexagon_M2_mpyd_rnd_lh_s1 : 2501Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_lh_s1">; 2502 2503def int_hexagon_M2_mpyd_rnd_ll_s0 : 2504Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_ll_s0">; 2505 2506def int_hexagon_M2_mpyd_rnd_ll_s1 : 2507Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_ll_s1">; 2508 2509def int_hexagon_M2_mpyi : 2510Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyi">; 2511 2512def int_hexagon_M2_mpysmi : 2513Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpysmi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 2514 2515def int_hexagon_M2_mpysu_up : 2516Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpysu_up">; 2517 2518def int_hexagon_M2_mpyu_acc_hh_s0 : 2519Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hh_s0">; 2520 2521def int_hexagon_M2_mpyu_acc_hh_s1 : 2522Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hh_s1">; 2523 2524def int_hexagon_M2_mpyu_acc_hl_s0 : 2525Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hl_s0">; 2526 2527def int_hexagon_M2_mpyu_acc_hl_s1 : 2528Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hl_s1">; 2529 2530def int_hexagon_M2_mpyu_acc_lh_s0 : 2531Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_lh_s0">; 2532 2533def int_hexagon_M2_mpyu_acc_lh_s1 : 2534Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_lh_s1">; 2535 2536def int_hexagon_M2_mpyu_acc_ll_s0 : 2537Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_ll_s0">; 2538 2539def int_hexagon_M2_mpyu_acc_ll_s1 : 2540Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_ll_s1">; 2541 2542def int_hexagon_M2_mpyu_hh_s0 : 2543Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hh_s0">; 2544 2545def int_hexagon_M2_mpyu_hh_s1 : 2546Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hh_s1">; 2547 2548def int_hexagon_M2_mpyu_hl_s0 : 2549Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hl_s0">; 2550 2551def int_hexagon_M2_mpyu_hl_s1 : 2552Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hl_s1">; 2553 2554def int_hexagon_M2_mpyu_lh_s0 : 2555Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_lh_s0">; 2556 2557def int_hexagon_M2_mpyu_lh_s1 : 2558Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_lh_s1">; 2559 2560def int_hexagon_M2_mpyu_ll_s0 : 2561Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_ll_s0">; 2562 2563def int_hexagon_M2_mpyu_ll_s1 : 2564Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_ll_s1">; 2565 2566def int_hexagon_M2_mpyu_nac_hh_s0 : 2567Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hh_s0">; 2568 2569def int_hexagon_M2_mpyu_nac_hh_s1 : 2570Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hh_s1">; 2571 2572def int_hexagon_M2_mpyu_nac_hl_s0 : 2573Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hl_s0">; 2574 2575def int_hexagon_M2_mpyu_nac_hl_s1 : 2576Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hl_s1">; 2577 2578def int_hexagon_M2_mpyu_nac_lh_s0 : 2579Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_lh_s0">; 2580 2581def int_hexagon_M2_mpyu_nac_lh_s1 : 2582Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_lh_s1">; 2583 2584def int_hexagon_M2_mpyu_nac_ll_s0 : 2585Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_ll_s0">; 2586 2587def int_hexagon_M2_mpyu_nac_ll_s1 : 2588Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_ll_s1">; 2589 2590def int_hexagon_M2_mpyu_up : 2591Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_up">; 2592 2593def int_hexagon_M2_mpyud_acc_hh_s0 : 2594Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hh_s0">; 2595 2596def int_hexagon_M2_mpyud_acc_hh_s1 : 2597Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hh_s1">; 2598 2599def int_hexagon_M2_mpyud_acc_hl_s0 : 2600Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hl_s0">; 2601 2602def int_hexagon_M2_mpyud_acc_hl_s1 : 2603Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hl_s1">; 2604 2605def int_hexagon_M2_mpyud_acc_lh_s0 : 2606Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_lh_s0">; 2607 2608def int_hexagon_M2_mpyud_acc_lh_s1 : 2609Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_lh_s1">; 2610 2611def int_hexagon_M2_mpyud_acc_ll_s0 : 2612Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_ll_s0">; 2613 2614def int_hexagon_M2_mpyud_acc_ll_s1 : 2615Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_ll_s1">; 2616 2617def int_hexagon_M2_mpyud_hh_s0 : 2618Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hh_s0">; 2619 2620def int_hexagon_M2_mpyud_hh_s1 : 2621Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hh_s1">; 2622 2623def int_hexagon_M2_mpyud_hl_s0 : 2624Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hl_s0">; 2625 2626def int_hexagon_M2_mpyud_hl_s1 : 2627Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hl_s1">; 2628 2629def int_hexagon_M2_mpyud_lh_s0 : 2630Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_lh_s0">; 2631 2632def int_hexagon_M2_mpyud_lh_s1 : 2633Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_lh_s1">; 2634 2635def int_hexagon_M2_mpyud_ll_s0 : 2636Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_ll_s0">; 2637 2638def int_hexagon_M2_mpyud_ll_s1 : 2639Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_ll_s1">; 2640 2641def int_hexagon_M2_mpyud_nac_hh_s0 : 2642Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hh_s0">; 2643 2644def int_hexagon_M2_mpyud_nac_hh_s1 : 2645Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hh_s1">; 2646 2647def int_hexagon_M2_mpyud_nac_hl_s0 : 2648Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hl_s0">; 2649 2650def int_hexagon_M2_mpyud_nac_hl_s1 : 2651Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hl_s1">; 2652 2653def int_hexagon_M2_mpyud_nac_lh_s0 : 2654Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_lh_s0">; 2655 2656def int_hexagon_M2_mpyud_nac_lh_s1 : 2657Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_lh_s1">; 2658 2659def int_hexagon_M2_mpyud_nac_ll_s0 : 2660Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_ll_s0">; 2661 2662def int_hexagon_M2_mpyud_nac_ll_s1 : 2663Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_ll_s1">; 2664 2665def int_hexagon_M2_mpyui : 2666Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyui">; 2667 2668def int_hexagon_M2_nacci : 2669Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_nacci">; 2670 2671def int_hexagon_M2_naccii : 2672Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_naccii", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2673 2674def int_hexagon_M2_subacc : 2675Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_subacc">; 2676 2677def int_hexagon_M2_vabsdiffh : 2678Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vabsdiffh">; 2679 2680def int_hexagon_M2_vabsdiffw : 2681Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vabsdiffw">; 2682 2683def int_hexagon_M2_vcmac_s0_sat_i : 2684Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vcmac_s0_sat_i">; 2685 2686def int_hexagon_M2_vcmac_s0_sat_r : 2687Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vcmac_s0_sat_r">; 2688 2689def int_hexagon_M2_vcmpy_s0_sat_i : 2690Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vcmpy_s0_sat_i">; 2691 2692def int_hexagon_M2_vcmpy_s0_sat_r : 2693Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vcmpy_s0_sat_r">; 2694 2695def int_hexagon_M2_vcmpy_s1_sat_i : 2696Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vcmpy_s1_sat_i">; 2697 2698def int_hexagon_M2_vcmpy_s1_sat_r : 2699Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vcmpy_s1_sat_r">; 2700 2701def int_hexagon_M2_vdmacs_s0 : 2702Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vdmacs_s0">; 2703 2704def int_hexagon_M2_vdmacs_s1 : 2705Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vdmacs_s1">; 2706 2707def int_hexagon_M2_vdmpyrs_s0 : 2708Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vdmpyrs_s0">; 2709 2710def int_hexagon_M2_vdmpyrs_s1 : 2711Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vdmpyrs_s1">; 2712 2713def int_hexagon_M2_vdmpys_s0 : 2714Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vdmpys_s0">; 2715 2716def int_hexagon_M2_vdmpys_s1 : 2717Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vdmpys_s1">; 2718 2719def int_hexagon_M2_vmac2 : 2720Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2">; 2721 2722def int_hexagon_M2_vmac2es : 2723Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vmac2es">; 2724 2725def int_hexagon_M2_vmac2es_s0 : 2726Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vmac2es_s0">; 2727 2728def int_hexagon_M2_vmac2es_s1 : 2729Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vmac2es_s1">; 2730 2731def int_hexagon_M2_vmac2s_s0 : 2732Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2s_s0">; 2733 2734def int_hexagon_M2_vmac2s_s1 : 2735Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2s_s1">; 2736 2737def int_hexagon_M2_vmac2su_s0 : 2738Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2su_s0">; 2739 2740def int_hexagon_M2_vmac2su_s1 : 2741Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2su_s1">; 2742 2743def int_hexagon_M2_vmpy2es_s0 : 2744Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vmpy2es_s0">; 2745 2746def int_hexagon_M2_vmpy2es_s1 : 2747Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vmpy2es_s1">; 2748 2749def int_hexagon_M2_vmpy2s_s0 : 2750Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s0">; 2751 2752def int_hexagon_M2_vmpy2s_s0pack : 2753Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s0pack">; 2754 2755def int_hexagon_M2_vmpy2s_s1 : 2756Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s1">; 2757 2758def int_hexagon_M2_vmpy2s_s1pack : 2759Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s1pack">; 2760 2761def int_hexagon_M2_vmpy2su_s0 : 2762Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2su_s0">; 2763 2764def int_hexagon_M2_vmpy2su_s1 : 2765Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2su_s1">; 2766 2767def int_hexagon_M2_vraddh : 2768Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vraddh">; 2769 2770def int_hexagon_M2_vradduh : 2771Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vradduh">; 2772 2773def int_hexagon_M2_vrcmaci_s0 : 2774Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmaci_s0">; 2775 2776def int_hexagon_M2_vrcmaci_s0c : 2777Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmaci_s0c">; 2778 2779def int_hexagon_M2_vrcmacr_s0 : 2780Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmacr_s0">; 2781 2782def int_hexagon_M2_vrcmacr_s0c : 2783Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmacr_s0c">; 2784 2785def int_hexagon_M2_vrcmpyi_s0 : 2786Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyi_s0">; 2787 2788def int_hexagon_M2_vrcmpyi_s0c : 2789Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyi_s0c">; 2790 2791def int_hexagon_M2_vrcmpyr_s0 : 2792Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyr_s0">; 2793 2794def int_hexagon_M2_vrcmpyr_s0c : 2795Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyr_s0c">; 2796 2797def int_hexagon_M2_vrcmpys_acc_s1 : 2798Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_M2_vrcmpys_acc_s1">; 2799 2800def int_hexagon_M2_vrcmpys_s1 : 2801Hexagon_i64_i64i32_Intrinsic<"HEXAGON_M2_vrcmpys_s1">; 2802 2803def int_hexagon_M2_vrcmpys_s1rp : 2804Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M2_vrcmpys_s1rp">; 2805 2806def int_hexagon_M2_vrmac_s0 : 2807Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrmac_s0">; 2808 2809def int_hexagon_M2_vrmpy_s0 : 2810Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrmpy_s0">; 2811 2812def int_hexagon_M2_xor_xacc : 2813Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_xor_xacc">; 2814 2815def int_hexagon_M4_and_and : 2816Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_and">; 2817 2818def int_hexagon_M4_and_andn : 2819Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_andn">; 2820 2821def int_hexagon_M4_and_or : 2822Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_or">; 2823 2824def int_hexagon_M4_and_xor : 2825Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_xor">; 2826 2827def int_hexagon_M4_cmpyi_wh : 2828Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyi_wh">; 2829 2830def int_hexagon_M4_cmpyi_whc : 2831Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyi_whc">; 2832 2833def int_hexagon_M4_cmpyr_wh : 2834Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyr_wh">; 2835 2836def int_hexagon_M4_cmpyr_whc : 2837Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyr_whc">; 2838 2839def int_hexagon_M4_mac_up_s1_sat : 2840Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mac_up_s1_sat">; 2841 2842def int_hexagon_M4_mpyri_addi : 2843Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyri_addi", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>; 2844 2845def int_hexagon_M4_mpyri_addr : 2846Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyri_addr", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2847 2848def int_hexagon_M4_mpyri_addr_u2 : 2849Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyri_addr_u2", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 2850 2851def int_hexagon_M4_mpyrr_addi : 2852Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyrr_addi", [IntrNoMem, ImmArg<ArgIndex<0>>]>; 2853 2854def int_hexagon_M4_mpyrr_addr : 2855Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyrr_addr">; 2856 2857def int_hexagon_M4_nac_up_s1_sat : 2858Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_nac_up_s1_sat">; 2859 2860def int_hexagon_M4_or_and : 2861Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_and">; 2862 2863def int_hexagon_M4_or_andn : 2864Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_andn">; 2865 2866def int_hexagon_M4_or_or : 2867Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_or">; 2868 2869def int_hexagon_M4_or_xor : 2870Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_xor">; 2871 2872def int_hexagon_M4_pmpyw : 2873Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M4_pmpyw">; 2874 2875def int_hexagon_M4_pmpyw_acc : 2876Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M4_pmpyw_acc">; 2877 2878def int_hexagon_M4_vpmpyh : 2879Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M4_vpmpyh">; 2880 2881def int_hexagon_M4_vpmpyh_acc : 2882Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M4_vpmpyh_acc">; 2883 2884def int_hexagon_M4_vrmpyeh_acc_s0 : 2885Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_acc_s0">; 2886 2887def int_hexagon_M4_vrmpyeh_acc_s1 : 2888Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_acc_s1">; 2889 2890def int_hexagon_M4_vrmpyeh_s0 : 2891Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_s0">; 2892 2893def int_hexagon_M4_vrmpyeh_s1 : 2894Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_s1">; 2895 2896def int_hexagon_M4_vrmpyoh_acc_s0 : 2897Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_acc_s0">; 2898 2899def int_hexagon_M4_vrmpyoh_acc_s1 : 2900Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_acc_s1">; 2901 2902def int_hexagon_M4_vrmpyoh_s0 : 2903Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_s0">; 2904 2905def int_hexagon_M4_vrmpyoh_s1 : 2906Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_s1">; 2907 2908def int_hexagon_M4_xor_and : 2909Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_xor_and">; 2910 2911def int_hexagon_M4_xor_andn : 2912Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_xor_andn">; 2913 2914def int_hexagon_M4_xor_or : 2915Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_xor_or">; 2916 2917def int_hexagon_M4_xor_xacc : 2918Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_xor_xacc">; 2919 2920def int_hexagon_M5_vdmacbsu : 2921Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M5_vdmacbsu">; 2922 2923def int_hexagon_M5_vdmpybsu : 2924Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M5_vdmpybsu">; 2925 2926def int_hexagon_M5_vmacbsu : 2927Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M5_vmacbsu">; 2928 2929def int_hexagon_M5_vmacbuu : 2930Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M5_vmacbuu">; 2931 2932def int_hexagon_M5_vmpybsu : 2933Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M5_vmpybsu">; 2934 2935def int_hexagon_M5_vmpybuu : 2936Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M5_vmpybuu">; 2937 2938def int_hexagon_M5_vrmacbsu : 2939Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M5_vrmacbsu">; 2940 2941def int_hexagon_M5_vrmacbuu : 2942Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M5_vrmacbuu">; 2943 2944def int_hexagon_M5_vrmpybsu : 2945Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M5_vrmpybsu">; 2946 2947def int_hexagon_M5_vrmpybuu : 2948Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M5_vrmpybuu">; 2949 2950def int_hexagon_S2_addasl_rrri : 2951Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_addasl_rrri", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2952 2953def int_hexagon_S2_asl_i_p : 2954Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_i_p", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 2955 2956def int_hexagon_S2_asl_i_p_acc : 2957Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_acc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2958 2959def int_hexagon_S2_asl_i_p_and : 2960Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_and", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2961 2962def int_hexagon_S2_asl_i_p_nac : 2963Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_nac", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2964 2965def int_hexagon_S2_asl_i_p_or : 2966Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_or", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2967 2968def int_hexagon_S2_asl_i_p_xacc : 2969Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_xacc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2970 2971def int_hexagon_S2_asl_i_r : 2972Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_i_r", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 2973 2974def int_hexagon_S2_asl_i_r_acc : 2975Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_acc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2976 2977def int_hexagon_S2_asl_i_r_and : 2978Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_and", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2979 2980def int_hexagon_S2_asl_i_r_nac : 2981Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_nac", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2982 2983def int_hexagon_S2_asl_i_r_or : 2984Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_or", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2985 2986def int_hexagon_S2_asl_i_r_sat : 2987Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_sat", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 2988 2989def int_hexagon_S2_asl_i_r_xacc : 2990Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_xacc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2991 2992def int_hexagon_S2_asl_i_vh : 2993Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_i_vh", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 2994 2995def int_hexagon_S2_asl_i_vw : 2996Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_i_vw", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 2997 2998def int_hexagon_S2_asl_r_p : 2999Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_r_p">; 3000 3001def int_hexagon_S2_asl_r_p_acc : 3002Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_acc">; 3003 3004def int_hexagon_S2_asl_r_p_and : 3005Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_and">; 3006 3007def int_hexagon_S2_asl_r_p_nac : 3008Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_nac">; 3009 3010def int_hexagon_S2_asl_r_p_or : 3011Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_or">; 3012 3013def int_hexagon_S2_asl_r_p_xor : 3014Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_xor">; 3015 3016def int_hexagon_S2_asl_r_r : 3017Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_r_r">; 3018 3019def int_hexagon_S2_asl_r_r_acc : 3020Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_acc">; 3021 3022def int_hexagon_S2_asl_r_r_and : 3023Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_and">; 3024 3025def int_hexagon_S2_asl_r_r_nac : 3026Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_nac">; 3027 3028def int_hexagon_S2_asl_r_r_or : 3029Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_or">; 3030 3031def int_hexagon_S2_asl_r_r_sat : 3032Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_sat">; 3033 3034def int_hexagon_S2_asl_r_vh : 3035Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_r_vh">; 3036 3037def int_hexagon_S2_asl_r_vw : 3038Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_r_vw">; 3039 3040def int_hexagon_S2_asr_i_p : 3041Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_p", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3042 3043def int_hexagon_S2_asr_i_p_acc : 3044Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_acc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3045 3046def int_hexagon_S2_asr_i_p_and : 3047Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_and", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3048 3049def int_hexagon_S2_asr_i_p_nac : 3050Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_nac", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3051 3052def int_hexagon_S2_asr_i_p_or : 3053Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_or", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3054 3055def int_hexagon_S2_asr_i_p_rnd : 3056Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_rnd", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3057 3058def int_hexagon_S2_asr_i_p_rnd_goodsyntax : 3059Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_rnd_goodsyntax", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3060 3061def int_hexagon_S2_asr_i_r : 3062Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_i_r", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3063 3064def int_hexagon_S2_asr_i_r_acc : 3065Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_acc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3066 3067def int_hexagon_S2_asr_i_r_and : 3068Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_and", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3069 3070def int_hexagon_S2_asr_i_r_nac : 3071Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_nac", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3072 3073def int_hexagon_S2_asr_i_r_or : 3074Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_or", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3075 3076def int_hexagon_S2_asr_i_r_rnd : 3077Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_rnd", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3078 3079def int_hexagon_S2_asr_i_r_rnd_goodsyntax : 3080Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_rnd_goodsyntax", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3081 3082def int_hexagon_S2_asr_i_svw_trun : 3083Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S2_asr_i_svw_trun", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3084 3085def int_hexagon_S2_asr_i_vh : 3086Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_vh", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3087 3088def int_hexagon_S2_asr_i_vw : 3089Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_vw", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3090 3091def int_hexagon_S2_asr_r_p : 3092Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_r_p">; 3093 3094def int_hexagon_S2_asr_r_p_acc : 3095Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_acc">; 3096 3097def int_hexagon_S2_asr_r_p_and : 3098Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_and">; 3099 3100def int_hexagon_S2_asr_r_p_nac : 3101Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_nac">; 3102 3103def int_hexagon_S2_asr_r_p_or : 3104Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_or">; 3105 3106def int_hexagon_S2_asr_r_p_xor : 3107Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_xor">; 3108 3109def int_hexagon_S2_asr_r_r : 3110Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_r_r">; 3111 3112def int_hexagon_S2_asr_r_r_acc : 3113Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_acc">; 3114 3115def int_hexagon_S2_asr_r_r_and : 3116Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_and">; 3117 3118def int_hexagon_S2_asr_r_r_nac : 3119Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_nac">; 3120 3121def int_hexagon_S2_asr_r_r_or : 3122Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_or">; 3123 3124def int_hexagon_S2_asr_r_r_sat : 3125Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_sat">; 3126 3127def int_hexagon_S2_asr_r_svw_trun : 3128Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S2_asr_r_svw_trun">; 3129 3130def int_hexagon_S2_asr_r_vh : 3131Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_r_vh">; 3132 3133def int_hexagon_S2_asr_r_vw : 3134Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_r_vw">; 3135 3136def int_hexagon_S2_brev : 3137Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_brev">; 3138 3139def int_hexagon_S2_brevp : 3140Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_brevp">; 3141 3142def int_hexagon_S2_cl0 : 3143Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_cl0">; 3144 3145def int_hexagon_S2_cl0p : 3146Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_cl0p">; 3147 3148def int_hexagon_S2_cl1 : 3149Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_cl1">; 3150 3151def int_hexagon_S2_cl1p : 3152Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_cl1p">; 3153 3154def int_hexagon_S2_clb : 3155Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_clb">; 3156 3157def int_hexagon_S2_clbnorm : 3158Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_clbnorm">; 3159 3160def int_hexagon_S2_clbp : 3161Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_clbp">; 3162 3163def int_hexagon_S2_clrbit_i : 3164Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_clrbit_i", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3165 3166def int_hexagon_S2_clrbit_r : 3167Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_clrbit_r">; 3168 3169def int_hexagon_S2_ct0 : 3170Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_ct0">; 3171 3172def int_hexagon_S2_ct0p : 3173Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_ct0p">; 3174 3175def int_hexagon_S2_ct1 : 3176Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_ct1">; 3177 3178def int_hexagon_S2_ct1p : 3179Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_ct1p">; 3180 3181def int_hexagon_S2_deinterleave : 3182Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_deinterleave">; 3183 3184def int_hexagon_S2_extractu : 3185Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_extractu", [IntrNoMem, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>; 3186 3187def int_hexagon_S2_extractu_rp : 3188Hexagon_i32_i32i64_Intrinsic<"HEXAGON_S2_extractu_rp">; 3189 3190def int_hexagon_S2_extractup : 3191Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_S2_extractup", [IntrNoMem, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>; 3192 3193def int_hexagon_S2_extractup_rp : 3194Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_extractup_rp">; 3195 3196def int_hexagon_S2_insert : 3197Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_insert", [IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>; 3198 3199def int_hexagon_S2_insert_rp : 3200Hexagon_i32_i32i32i64_Intrinsic<"HEXAGON_S2_insert_rp">; 3201 3202def int_hexagon_S2_insertp : 3203Hexagon_i64_i64i64i32i32_Intrinsic<"HEXAGON_S2_insertp", [IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>; 3204 3205def int_hexagon_S2_insertp_rp : 3206Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_S2_insertp_rp">; 3207 3208def int_hexagon_S2_interleave : 3209Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_interleave">; 3210 3211def int_hexagon_S2_lfsp : 3212Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_lfsp">; 3213 3214def int_hexagon_S2_lsl_r_p : 3215Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p">; 3216 3217def int_hexagon_S2_lsl_r_p_acc : 3218Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_acc">; 3219 3220def int_hexagon_S2_lsl_r_p_and : 3221Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_and">; 3222 3223def int_hexagon_S2_lsl_r_p_nac : 3224Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_nac">; 3225 3226def int_hexagon_S2_lsl_r_p_or : 3227Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_or">; 3228 3229def int_hexagon_S2_lsl_r_p_xor : 3230Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_xor">; 3231 3232def int_hexagon_S2_lsl_r_r : 3233Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r">; 3234 3235def int_hexagon_S2_lsl_r_r_acc : 3236Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_acc">; 3237 3238def int_hexagon_S2_lsl_r_r_and : 3239Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_and">; 3240 3241def int_hexagon_S2_lsl_r_r_nac : 3242Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_nac">; 3243 3244def int_hexagon_S2_lsl_r_r_or : 3245Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_or">; 3246 3247def int_hexagon_S2_lsl_r_vh : 3248Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsl_r_vh">; 3249 3250def int_hexagon_S2_lsl_r_vw : 3251Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsl_r_vw">; 3252 3253def int_hexagon_S2_lsr_i_p : 3254Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3255 3256def int_hexagon_S2_lsr_i_p_acc : 3257Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_acc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3258 3259def int_hexagon_S2_lsr_i_p_and : 3260Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_and", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3261 3262def int_hexagon_S2_lsr_i_p_nac : 3263Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_nac", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3264 3265def int_hexagon_S2_lsr_i_p_or : 3266Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_or", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3267 3268def int_hexagon_S2_lsr_i_p_xacc : 3269Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_xacc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3270 3271def int_hexagon_S2_lsr_i_r : 3272Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3273 3274def int_hexagon_S2_lsr_i_r_acc : 3275Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_acc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3276 3277def int_hexagon_S2_lsr_i_r_and : 3278Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_and", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3279 3280def int_hexagon_S2_lsr_i_r_nac : 3281Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_nac", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3282 3283def int_hexagon_S2_lsr_i_r_or : 3284Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_or", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3285 3286def int_hexagon_S2_lsr_i_r_xacc : 3287Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_xacc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3288 3289def int_hexagon_S2_lsr_i_vh : 3290Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_i_vh", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3291 3292def int_hexagon_S2_lsr_i_vw : 3293Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_i_vw", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3294 3295def int_hexagon_S2_lsr_r_p : 3296Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p">; 3297 3298def int_hexagon_S2_lsr_r_p_acc : 3299Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_acc">; 3300 3301def int_hexagon_S2_lsr_r_p_and : 3302Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_and">; 3303 3304def int_hexagon_S2_lsr_r_p_nac : 3305Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_nac">; 3306 3307def int_hexagon_S2_lsr_r_p_or : 3308Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_or">; 3309 3310def int_hexagon_S2_lsr_r_p_xor : 3311Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_xor">; 3312 3313def int_hexagon_S2_lsr_r_r : 3314Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r">; 3315 3316def int_hexagon_S2_lsr_r_r_acc : 3317Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_acc">; 3318 3319def int_hexagon_S2_lsr_r_r_and : 3320Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_and">; 3321 3322def int_hexagon_S2_lsr_r_r_nac : 3323Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_nac">; 3324 3325def int_hexagon_S2_lsr_r_r_or : 3326Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_or">; 3327 3328def int_hexagon_S2_lsr_r_vh : 3329Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_r_vh">; 3330 3331def int_hexagon_S2_lsr_r_vw : 3332Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_r_vw">; 3333 3334def int_hexagon_S2_packhl : 3335Hexagon_i64_i32i32_Intrinsic<"HEXAGON_S2_packhl">; 3336 3337def int_hexagon_S2_parityp : 3338Hexagon_i32_i64i64_Intrinsic<"HEXAGON_S2_parityp">; 3339 3340def int_hexagon_S2_setbit_i : 3341Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_setbit_i", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3342 3343def int_hexagon_S2_setbit_r : 3344Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_setbit_r">; 3345 3346def int_hexagon_S2_shuffeb : 3347Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffeb">; 3348 3349def int_hexagon_S2_shuffeh : 3350Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffeh">; 3351 3352def int_hexagon_S2_shuffob : 3353Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffob">; 3354 3355def int_hexagon_S2_shuffoh : 3356Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffoh">; 3357 3358def int_hexagon_S2_svsathb : 3359Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_svsathb">; 3360 3361def int_hexagon_S2_svsathub : 3362Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_svsathub">; 3363 3364def int_hexagon_S2_tableidxb_goodsyntax : 3365Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxb_goodsyntax", [IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>; 3366 3367def int_hexagon_S2_tableidxd_goodsyntax : 3368Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxd_goodsyntax", [IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>; 3369 3370def int_hexagon_S2_tableidxh_goodsyntax : 3371Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxh_goodsyntax", [IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>; 3372 3373def int_hexagon_S2_tableidxw_goodsyntax : 3374Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxw_goodsyntax", [IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>; 3375 3376def int_hexagon_S2_togglebit_i : 3377Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_togglebit_i", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3378 3379def int_hexagon_S2_togglebit_r : 3380Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_togglebit_r">; 3381 3382def int_hexagon_S2_tstbit_i : 3383Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_tstbit_i", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3384 3385def int_hexagon_S2_tstbit_r : 3386Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_tstbit_r">; 3387 3388def int_hexagon_S2_valignib : 3389Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_valignib", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3390 3391def int_hexagon_S2_valignrb : 3392Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_valignrb">; 3393 3394def int_hexagon_S2_vcnegh : 3395Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_vcnegh">; 3396 3397def int_hexagon_S2_vcrotate : 3398Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_vcrotate">; 3399 3400def int_hexagon_S2_vrcnegh : 3401Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_vrcnegh">; 3402 3403def int_hexagon_S2_vrndpackwh : 3404Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vrndpackwh">; 3405 3406def int_hexagon_S2_vrndpackwhs : 3407Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vrndpackwhs">; 3408 3409def int_hexagon_S2_vsathb : 3410Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsathb">; 3411 3412def int_hexagon_S2_vsathb_nopack : 3413Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsathb_nopack">; 3414 3415def int_hexagon_S2_vsathub : 3416Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsathub">; 3417 3418def int_hexagon_S2_vsathub_nopack : 3419Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsathub_nopack">; 3420 3421def int_hexagon_S2_vsatwh : 3422Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsatwh">; 3423 3424def int_hexagon_S2_vsatwh_nopack : 3425Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsatwh_nopack">; 3426 3427def int_hexagon_S2_vsatwuh : 3428Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsatwuh">; 3429 3430def int_hexagon_S2_vsatwuh_nopack : 3431Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsatwuh_nopack">; 3432 3433def int_hexagon_S2_vsplatrb : 3434Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_vsplatrb">; 3435 3436def int_hexagon_S2_vsplatrh : 3437Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vsplatrh">; 3438 3439def int_hexagon_S2_vspliceib : 3440Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_vspliceib", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3441 3442def int_hexagon_S2_vsplicerb : 3443Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_vsplicerb">; 3444 3445def int_hexagon_S2_vsxtbh : 3446Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vsxtbh">; 3447 3448def int_hexagon_S2_vsxthw : 3449Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vsxthw">; 3450 3451def int_hexagon_S2_vtrunehb : 3452Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vtrunehb">; 3453 3454def int_hexagon_S2_vtrunewh : 3455Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_vtrunewh">; 3456 3457def int_hexagon_S2_vtrunohb : 3458Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vtrunohb">; 3459 3460def int_hexagon_S2_vtrunowh : 3461Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_vtrunowh">; 3462 3463def int_hexagon_S2_vzxtbh : 3464Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vzxtbh">; 3465 3466def int_hexagon_S2_vzxthw : 3467Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vzxthw">; 3468 3469def int_hexagon_S4_addaddi : 3470Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_addaddi", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3471 3472def int_hexagon_S4_addi_asl_ri : 3473Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_addi_asl_ri", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>; 3474 3475def int_hexagon_S4_addi_lsr_ri : 3476Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_addi_lsr_ri", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>; 3477 3478def int_hexagon_S4_andi_asl_ri : 3479Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_andi_asl_ri", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>; 3480 3481def int_hexagon_S4_andi_lsr_ri : 3482Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_andi_lsr_ri", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>; 3483 3484def int_hexagon_S4_clbaddi : 3485Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_clbaddi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3486 3487def int_hexagon_S4_clbpaddi : 3488Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S4_clbpaddi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3489 3490def int_hexagon_S4_clbpnorm : 3491Hexagon_i32_i64_Intrinsic<"HEXAGON_S4_clbpnorm">; 3492 3493def int_hexagon_S4_extract : 3494Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_extract", [IntrNoMem, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>; 3495 3496def int_hexagon_S4_extract_rp : 3497Hexagon_i32_i32i64_Intrinsic<"HEXAGON_S4_extract_rp">; 3498 3499def int_hexagon_S4_extractp : 3500Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_S4_extractp", [IntrNoMem, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>; 3501 3502def int_hexagon_S4_extractp_rp : 3503Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_extractp_rp">; 3504 3505def int_hexagon_S4_lsli : 3506Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_lsli", [IntrNoMem, ImmArg<ArgIndex<0>>]>; 3507 3508def int_hexagon_S4_ntstbit_i : 3509Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_ntstbit_i", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3510 3511def int_hexagon_S4_ntstbit_r : 3512Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_ntstbit_r">; 3513 3514def int_hexagon_S4_or_andi : 3515Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_or_andi", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3516 3517def int_hexagon_S4_or_andix : 3518Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_or_andix", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3519 3520def int_hexagon_S4_or_ori : 3521Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_or_ori", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3522 3523def int_hexagon_S4_ori_asl_ri : 3524Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_ori_asl_ri", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>; 3525 3526def int_hexagon_S4_ori_lsr_ri : 3527Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_ori_lsr_ri", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>; 3528 3529def int_hexagon_S4_parity : 3530Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_parity">; 3531 3532def int_hexagon_S4_subaddi : 3533Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_subaddi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3534 3535def int_hexagon_S4_subi_asl_ri : 3536Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_subi_asl_ri", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>; 3537 3538def int_hexagon_S4_subi_lsr_ri : 3539Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_subi_lsr_ri", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>; 3540 3541def int_hexagon_S4_vrcrotate : 3542Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_S4_vrcrotate", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3543 3544def int_hexagon_S4_vrcrotate_acc : 3545Hexagon_i64_i64i64i32i32_Intrinsic<"HEXAGON_S4_vrcrotate_acc", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 3546 3547def int_hexagon_S4_vxaddsubh : 3548Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxaddsubh">; 3549 3550def int_hexagon_S4_vxaddsubhr : 3551Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxaddsubhr">; 3552 3553def int_hexagon_S4_vxaddsubw : 3554Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxaddsubw">; 3555 3556def int_hexagon_S4_vxsubaddh : 3557Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxsubaddh">; 3558 3559def int_hexagon_S4_vxsubaddhr : 3560Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxsubaddhr">; 3561 3562def int_hexagon_S4_vxsubaddw : 3563Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxsubaddw">; 3564 3565def int_hexagon_S5_asrhub_rnd_sat_goodsyntax : 3566Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S5_asrhub_rnd_sat_goodsyntax", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3567 3568def int_hexagon_S5_asrhub_sat : 3569Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S5_asrhub_sat", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3570 3571def int_hexagon_S5_popcountp : 3572Hexagon_i32_i64_Intrinsic<"HEXAGON_S5_popcountp">; 3573 3574def int_hexagon_S5_vasrhrnd_goodsyntax : 3575Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S5_vasrhrnd_goodsyntax", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3576 3577def int_hexagon_Y2_dccleana : 3578Hexagon__ptr_Intrinsic<"HEXAGON_Y2_dccleana", []>; 3579 3580def int_hexagon_Y2_dccleaninva : 3581Hexagon__ptr_Intrinsic<"HEXAGON_Y2_dccleaninva", []>; 3582 3583def int_hexagon_Y2_dcfetch : 3584Hexagon__ptr_Intrinsic<"HEXAGON_Y2_dcfetch", []>; 3585 3586def int_hexagon_Y2_dcinva : 3587Hexagon__ptr_Intrinsic<"HEXAGON_Y2_dcinva", []>; 3588 3589def int_hexagon_Y2_dczeroa : 3590Hexagon__ptr_Intrinsic<"HEXAGON_Y2_dczeroa", []>; 3591 3592def int_hexagon_Y4_l2fetch : 3593Hexagon__ptri32_Intrinsic<"HEXAGON_Y4_l2fetch", []>; 3594 3595def int_hexagon_Y5_l2fetch : 3596Hexagon__ptri64_Intrinsic<"HEXAGON_Y5_l2fetch", []>; 3597 3598// V60 Scalar Instructions. 3599 3600def int_hexagon_S6_rol_i_p : 3601Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S6_rol_i_p", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3602 3603def int_hexagon_S6_rol_i_p_acc : 3604Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_acc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3605 3606def int_hexagon_S6_rol_i_p_and : 3607Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_and", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3608 3609def int_hexagon_S6_rol_i_p_nac : 3610Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_nac", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3611 3612def int_hexagon_S6_rol_i_p_or : 3613Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_or", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3614 3615def int_hexagon_S6_rol_i_p_xacc : 3616Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_xacc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3617 3618def int_hexagon_S6_rol_i_r : 3619Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S6_rol_i_r", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3620 3621def int_hexagon_S6_rol_i_r_acc : 3622Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_acc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3623 3624def int_hexagon_S6_rol_i_r_and : 3625Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_and", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3626 3627def int_hexagon_S6_rol_i_r_nac : 3628Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_nac", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3629 3630def int_hexagon_S6_rol_i_r_or : 3631Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_or", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3632 3633def int_hexagon_S6_rol_i_r_xacc : 3634Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_xacc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3635 3636// V62 Scalar Instructions. 3637 3638def int_hexagon_M6_vabsdiffb : 3639Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M6_vabsdiffb">; 3640 3641def int_hexagon_M6_vabsdiffub : 3642Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M6_vabsdiffub">; 3643 3644def int_hexagon_S6_vsplatrbp : 3645Hexagon_i64_i32_Intrinsic<"HEXAGON_S6_vsplatrbp">; 3646 3647def int_hexagon_S6_vtrunehb_ppp : 3648Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S6_vtrunehb_ppp">; 3649 3650def int_hexagon_S6_vtrunohb_ppp : 3651Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S6_vtrunohb_ppp">; 3652 3653// V65 Scalar Instructions. 3654 3655def int_hexagon_A6_vcmpbeq_notany : 3656Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A6_vcmpbeq_notany">; 3657 3658// V66 Scalar Instructions. 3659 3660def int_hexagon_F2_dfadd : 3661Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfadd", [IntrNoMem, Throws]>; 3662 3663def int_hexagon_F2_dfsub : 3664Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfsub", [IntrNoMem, Throws]>; 3665 3666def int_hexagon_M2_mnaci : 3667Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mnaci">; 3668 3669def int_hexagon_S2_mask : 3670Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_mask", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>; 3671 3672// V67 Scalar Instructions. 3673 3674def int_hexagon_A7_clip : 3675Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A7_clip", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3676 3677def int_hexagon_A7_croundd_ri : 3678Hexagon_i64_i64i32_Intrinsic<"HEXAGON_A7_croundd_ri", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3679 3680def int_hexagon_A7_croundd_rr : 3681Hexagon_i64_i64i32_Intrinsic<"HEXAGON_A7_croundd_rr">; 3682 3683def int_hexagon_A7_vclip : 3684Hexagon_i64_i64i32_Intrinsic<"HEXAGON_A7_vclip", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3685 3686def int_hexagon_F2_dfmax : 3687Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfmax", [IntrNoMem, Throws]>; 3688 3689def int_hexagon_F2_dfmin : 3690Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfmin", [IntrNoMem, Throws]>; 3691 3692def int_hexagon_F2_dfmpyfix : 3693Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfmpyfix", [IntrNoMem, Throws]>; 3694 3695def int_hexagon_F2_dfmpyhh : 3696Hexagon_double_doubledoubledouble_Intrinsic<"HEXAGON_F2_dfmpyhh", [IntrNoMem, Throws]>; 3697 3698def int_hexagon_F2_dfmpylh : 3699Hexagon_double_doubledoubledouble_Intrinsic<"HEXAGON_F2_dfmpylh", [IntrNoMem, Throws]>; 3700 3701def int_hexagon_F2_dfmpyll : 3702Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfmpyll", [IntrNoMem, Throws]>; 3703 3704def int_hexagon_M7_dcmpyiw : 3705Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M7_dcmpyiw">; 3706 3707def int_hexagon_M7_dcmpyiw_acc : 3708Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M7_dcmpyiw_acc">; 3709 3710def int_hexagon_M7_dcmpyiwc : 3711Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M7_dcmpyiwc">; 3712 3713def int_hexagon_M7_dcmpyiwc_acc : 3714Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M7_dcmpyiwc_acc">; 3715 3716def int_hexagon_M7_dcmpyrw : 3717Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M7_dcmpyrw">; 3718 3719def int_hexagon_M7_dcmpyrw_acc : 3720Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M7_dcmpyrw_acc">; 3721 3722def int_hexagon_M7_dcmpyrwc : 3723Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M7_dcmpyrwc">; 3724 3725def int_hexagon_M7_dcmpyrwc_acc : 3726Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M7_dcmpyrwc_acc">; 3727 3728def int_hexagon_M7_vdmpy : 3729Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M7_vdmpy">; 3730 3731def int_hexagon_M7_vdmpy_acc : 3732Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M7_vdmpy_acc">; 3733 3734def int_hexagon_M7_wcmpyiw : 3735Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyiw">; 3736 3737def int_hexagon_M7_wcmpyiw_rnd : 3738Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyiw_rnd">; 3739 3740def int_hexagon_M7_wcmpyiwc : 3741Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyiwc">; 3742 3743def int_hexagon_M7_wcmpyiwc_rnd : 3744Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyiwc_rnd">; 3745 3746def int_hexagon_M7_wcmpyrw : 3747Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyrw">; 3748 3749def int_hexagon_M7_wcmpyrw_rnd : 3750Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyrw_rnd">; 3751 3752def int_hexagon_M7_wcmpyrwc : 3753Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyrwc">; 3754 3755def int_hexagon_M7_wcmpyrwc_rnd : 3756Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyrwc_rnd">; 3757 3758// V68 Scalar Instructions. 3759 3760def int_hexagon_Y6_dmlink : 3761Hexagon__ptrptr_Intrinsic<"HEXAGON_Y6_dmlink", [IntrArgMemOnly, IntrHasSideEffects]>; 3762 3763def int_hexagon_Y6_dmpause : 3764Hexagon_i32__Intrinsic<"HEXAGON_Y6_dmpause", [IntrArgMemOnly, IntrHasSideEffects]>; 3765 3766def int_hexagon_Y6_dmpoll : 3767Hexagon_i32__Intrinsic<"HEXAGON_Y6_dmpoll", [IntrArgMemOnly, IntrHasSideEffects]>; 3768 3769def int_hexagon_Y6_dmresume : 3770Hexagon__ptr_Intrinsic<"HEXAGON_Y6_dmresume", [IntrArgMemOnly, IntrHasSideEffects]>; 3771 3772def int_hexagon_Y6_dmstart : 3773Hexagon__ptr_Intrinsic<"HEXAGON_Y6_dmstart", [IntrArgMemOnly, IntrHasSideEffects]>; 3774 3775def int_hexagon_Y6_dmwait : 3776Hexagon_i32__Intrinsic<"HEXAGON_Y6_dmwait", [IntrArgMemOnly, IntrHasSideEffects]>; 3777 3778// V60 HVX Instructions. 3779 3780def int_hexagon_V6_extractw : 3781Hexagon_i32_v16i32i32_Intrinsic<"HEXAGON_V6_extractw">; 3782 3783def int_hexagon_V6_extractw_128B : 3784Hexagon_i32_v32i32i32_Intrinsic<"HEXAGON_V6_extractw_128B">; 3785 3786def int_hexagon_V6_hi : 3787Hexagon_v16i32_v32i32_Intrinsic<"HEXAGON_V6_hi">; 3788 3789def int_hexagon_V6_hi_128B : 3790Hexagon_v32i32_v64i32_Intrinsic<"HEXAGON_V6_hi_128B">; 3791 3792def int_hexagon_V6_lo : 3793Hexagon_v16i32_v32i32_Intrinsic<"HEXAGON_V6_lo">; 3794 3795def int_hexagon_V6_lo_128B : 3796Hexagon_v32i32_v64i32_Intrinsic<"HEXAGON_V6_lo_128B">; 3797 3798def int_hexagon_V6_lvsplatw : 3799Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_lvsplatw">; 3800 3801def int_hexagon_V6_lvsplatw_128B : 3802Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_lvsplatw_128B">; 3803 3804def int_hexagon_V6_pred_and : 3805Hexagon_v64i1_v64i1v64i1_Intrinsic<"HEXAGON_V6_pred_and">; 3806 3807def int_hexagon_V6_pred_and_128B : 3808Hexagon_v128i1_v128i1v128i1_Intrinsic<"HEXAGON_V6_pred_and_128B">; 3809 3810def int_hexagon_V6_pred_and_n : 3811Hexagon_v64i1_v64i1v64i1_Intrinsic<"HEXAGON_V6_pred_and_n">; 3812 3813def int_hexagon_V6_pred_and_n_128B : 3814Hexagon_v128i1_v128i1v128i1_Intrinsic<"HEXAGON_V6_pred_and_n_128B">; 3815 3816def int_hexagon_V6_pred_not : 3817Hexagon_v64i1_v64i1_Intrinsic<"HEXAGON_V6_pred_not">; 3818 3819def int_hexagon_V6_pred_not_128B : 3820Hexagon_v128i1_v128i1_Intrinsic<"HEXAGON_V6_pred_not_128B">; 3821 3822def int_hexagon_V6_pred_or : 3823Hexagon_v64i1_v64i1v64i1_Intrinsic<"HEXAGON_V6_pred_or">; 3824 3825def int_hexagon_V6_pred_or_128B : 3826Hexagon_v128i1_v128i1v128i1_Intrinsic<"HEXAGON_V6_pred_or_128B">; 3827 3828def int_hexagon_V6_pred_or_n : 3829Hexagon_v64i1_v64i1v64i1_Intrinsic<"HEXAGON_V6_pred_or_n">; 3830 3831def int_hexagon_V6_pred_or_n_128B : 3832Hexagon_v128i1_v128i1v128i1_Intrinsic<"HEXAGON_V6_pred_or_n_128B">; 3833 3834def int_hexagon_V6_pred_scalar2 : 3835Hexagon_v64i1_i32_Intrinsic<"HEXAGON_V6_pred_scalar2">; 3836 3837def int_hexagon_V6_pred_scalar2_128B : 3838Hexagon_v128i1_i32_Intrinsic<"HEXAGON_V6_pred_scalar2_128B">; 3839 3840def int_hexagon_V6_pred_xor : 3841Hexagon_v64i1_v64i1v64i1_Intrinsic<"HEXAGON_V6_pred_xor">; 3842 3843def int_hexagon_V6_pred_xor_128B : 3844Hexagon_v128i1_v128i1v128i1_Intrinsic<"HEXAGON_V6_pred_xor_128B">; 3845 3846def int_hexagon_V6_vS32b_nqpred_ai : 3847Hexagon__v64i1ptrv16i32_Intrinsic<"HEXAGON_V6_vS32b_nqpred_ai", [IntrWriteMem]>; 3848 3849def int_hexagon_V6_vS32b_nqpred_ai_128B : 3850Hexagon__v128i1ptrv32i32_Intrinsic<"HEXAGON_V6_vS32b_nqpred_ai_128B", [IntrWriteMem]>; 3851 3852def int_hexagon_V6_vS32b_nt_nqpred_ai : 3853Hexagon__v64i1ptrv16i32_Intrinsic<"HEXAGON_V6_vS32b_nt_nqpred_ai", [IntrWriteMem]>; 3854 3855def int_hexagon_V6_vS32b_nt_nqpred_ai_128B : 3856Hexagon__v128i1ptrv32i32_Intrinsic<"HEXAGON_V6_vS32b_nt_nqpred_ai_128B", [IntrWriteMem]>; 3857 3858def int_hexagon_V6_vS32b_nt_qpred_ai : 3859Hexagon__v64i1ptrv16i32_Intrinsic<"HEXAGON_V6_vS32b_nt_qpred_ai", [IntrWriteMem]>; 3860 3861def int_hexagon_V6_vS32b_nt_qpred_ai_128B : 3862Hexagon__v128i1ptrv32i32_Intrinsic<"HEXAGON_V6_vS32b_nt_qpred_ai_128B", [IntrWriteMem]>; 3863 3864def int_hexagon_V6_vS32b_qpred_ai : 3865Hexagon__v64i1ptrv16i32_Intrinsic<"HEXAGON_V6_vS32b_qpred_ai", [IntrWriteMem]>; 3866 3867def int_hexagon_V6_vS32b_qpred_ai_128B : 3868Hexagon__v128i1ptrv32i32_Intrinsic<"HEXAGON_V6_vS32b_qpred_ai_128B", [IntrWriteMem]>; 3869 3870def int_hexagon_V6_vabsdiffh : 3871Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabsdiffh">; 3872 3873def int_hexagon_V6_vabsdiffh_128B : 3874Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabsdiffh_128B">; 3875 3876def int_hexagon_V6_vabsdiffub : 3877Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabsdiffub">; 3878 3879def int_hexagon_V6_vabsdiffub_128B : 3880Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabsdiffub_128B">; 3881 3882def int_hexagon_V6_vabsdiffuh : 3883Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabsdiffuh">; 3884 3885def int_hexagon_V6_vabsdiffuh_128B : 3886Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabsdiffuh_128B">; 3887 3888def int_hexagon_V6_vabsdiffw : 3889Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabsdiffw">; 3890 3891def int_hexagon_V6_vabsdiffw_128B : 3892Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabsdiffw_128B">; 3893 3894def int_hexagon_V6_vabsh : 3895Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsh">; 3896 3897def int_hexagon_V6_vabsh_128B : 3898Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsh_128B">; 3899 3900def int_hexagon_V6_vabsh_sat : 3901Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsh_sat">; 3902 3903def int_hexagon_V6_vabsh_sat_128B : 3904Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsh_sat_128B">; 3905 3906def int_hexagon_V6_vabsw : 3907Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsw">; 3908 3909def int_hexagon_V6_vabsw_128B : 3910Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsw_128B">; 3911 3912def int_hexagon_V6_vabsw_sat : 3913Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsw_sat">; 3914 3915def int_hexagon_V6_vabsw_sat_128B : 3916Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsw_sat_128B">; 3917 3918def int_hexagon_V6_vaddb : 3919Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddb">; 3920 3921def int_hexagon_V6_vaddb_128B : 3922Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddb_128B">; 3923 3924def int_hexagon_V6_vaddb_dv : 3925Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddb_dv">; 3926 3927def int_hexagon_V6_vaddb_dv_128B : 3928Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddb_dv_128B">; 3929 3930def int_hexagon_V6_vaddbnq : 3931Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddbnq">; 3932 3933def int_hexagon_V6_vaddbnq_128B : 3934Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddbnq_128B">; 3935 3936def int_hexagon_V6_vaddbq : 3937Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddbq">; 3938 3939def int_hexagon_V6_vaddbq_128B : 3940Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddbq_128B">; 3941 3942def int_hexagon_V6_vaddh : 3943Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddh">; 3944 3945def int_hexagon_V6_vaddh_128B : 3946Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddh_128B">; 3947 3948def int_hexagon_V6_vaddh_dv : 3949Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddh_dv">; 3950 3951def int_hexagon_V6_vaddh_dv_128B : 3952Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddh_dv_128B">; 3953 3954def int_hexagon_V6_vaddhnq : 3955Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhnq">; 3956 3957def int_hexagon_V6_vaddhnq_128B : 3958Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhnq_128B">; 3959 3960def int_hexagon_V6_vaddhq : 3961Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhq">; 3962 3963def int_hexagon_V6_vaddhq_128B : 3964Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhq_128B">; 3965 3966def int_hexagon_V6_vaddhsat : 3967Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhsat">; 3968 3969def int_hexagon_V6_vaddhsat_128B : 3970Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhsat_128B">; 3971 3972def int_hexagon_V6_vaddhsat_dv : 3973Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhsat_dv">; 3974 3975def int_hexagon_V6_vaddhsat_dv_128B : 3976Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddhsat_dv_128B">; 3977 3978def int_hexagon_V6_vaddhw : 3979Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhw">; 3980 3981def int_hexagon_V6_vaddhw_128B : 3982Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhw_128B">; 3983 3984def int_hexagon_V6_vaddubh : 3985Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddubh">; 3986 3987def int_hexagon_V6_vaddubh_128B : 3988Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddubh_128B">; 3989 3990def int_hexagon_V6_vaddubsat : 3991Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddubsat">; 3992 3993def int_hexagon_V6_vaddubsat_128B : 3994Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddubsat_128B">; 3995 3996def int_hexagon_V6_vaddubsat_dv : 3997Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddubsat_dv">; 3998 3999def int_hexagon_V6_vaddubsat_dv_128B : 4000Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddubsat_dv_128B">; 4001 4002def int_hexagon_V6_vadduhsat : 4003Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduhsat">; 4004 4005def int_hexagon_V6_vadduhsat_128B : 4006Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhsat_128B">; 4007 4008def int_hexagon_V6_vadduhsat_dv : 4009Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhsat_dv">; 4010 4011def int_hexagon_V6_vadduhsat_dv_128B : 4012Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vadduhsat_dv_128B">; 4013 4014def int_hexagon_V6_vadduhw : 4015Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduhw">; 4016 4017def int_hexagon_V6_vadduhw_128B : 4018Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhw_128B">; 4019 4020def int_hexagon_V6_vaddw : 4021Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddw">; 4022 4023def int_hexagon_V6_vaddw_128B : 4024Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddw_128B">; 4025 4026def int_hexagon_V6_vaddw_dv : 4027Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddw_dv">; 4028 4029def int_hexagon_V6_vaddw_dv_128B : 4030Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddw_dv_128B">; 4031 4032def int_hexagon_V6_vaddwnq : 4033Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddwnq">; 4034 4035def int_hexagon_V6_vaddwnq_128B : 4036Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddwnq_128B">; 4037 4038def int_hexagon_V6_vaddwq : 4039Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddwq">; 4040 4041def int_hexagon_V6_vaddwq_128B : 4042Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddwq_128B">; 4043 4044def int_hexagon_V6_vaddwsat : 4045Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddwsat">; 4046 4047def int_hexagon_V6_vaddwsat_128B : 4048Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddwsat_128B">; 4049 4050def int_hexagon_V6_vaddwsat_dv : 4051Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddwsat_dv">; 4052 4053def int_hexagon_V6_vaddwsat_dv_128B : 4054Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddwsat_dv_128B">; 4055 4056def int_hexagon_V6_valignb : 4057Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_valignb">; 4058 4059def int_hexagon_V6_valignb_128B : 4060Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_valignb_128B">; 4061 4062def int_hexagon_V6_valignbi : 4063Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_valignbi", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 4064 4065def int_hexagon_V6_valignbi_128B : 4066Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_valignbi_128B", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 4067 4068def int_hexagon_V6_vand : 4069Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vand">; 4070 4071def int_hexagon_V6_vand_128B : 4072Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vand_128B">; 4073 4074def int_hexagon_V6_vandqrt : 4075Hexagon_v16i32_v64i1i32_Intrinsic<"HEXAGON_V6_vandqrt">; 4076 4077def int_hexagon_V6_vandqrt_128B : 4078Hexagon_v32i32_v128i1i32_Intrinsic<"HEXAGON_V6_vandqrt_128B">; 4079 4080def int_hexagon_V6_vandqrt_acc : 4081Hexagon_v16i32_v16i32v64i1i32_Intrinsic<"HEXAGON_V6_vandqrt_acc">; 4082 4083def int_hexagon_V6_vandqrt_acc_128B : 4084Hexagon_v32i32_v32i32v128i1i32_Intrinsic<"HEXAGON_V6_vandqrt_acc_128B">; 4085 4086def int_hexagon_V6_vandvrt : 4087Hexagon_v64i1_v16i32i32_Intrinsic<"HEXAGON_V6_vandvrt">; 4088 4089def int_hexagon_V6_vandvrt_128B : 4090Hexagon_v128i1_v32i32i32_Intrinsic<"HEXAGON_V6_vandvrt_128B">; 4091 4092def int_hexagon_V6_vandvrt_acc : 4093Hexagon_v64i1_v64i1v16i32i32_Intrinsic<"HEXAGON_V6_vandvrt_acc">; 4094 4095def int_hexagon_V6_vandvrt_acc_128B : 4096Hexagon_v128i1_v128i1v32i32i32_Intrinsic<"HEXAGON_V6_vandvrt_acc_128B">; 4097 4098def int_hexagon_V6_vaslh : 4099Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vaslh">; 4100 4101def int_hexagon_V6_vaslh_128B : 4102Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vaslh_128B">; 4103 4104def int_hexagon_V6_vaslhv : 4105Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaslhv">; 4106 4107def int_hexagon_V6_vaslhv_128B : 4108Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaslhv_128B">; 4109 4110def int_hexagon_V6_vaslw : 4111Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vaslw">; 4112 4113def int_hexagon_V6_vaslw_128B : 4114Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vaslw_128B">; 4115 4116def int_hexagon_V6_vaslw_acc : 4117Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vaslw_acc">; 4118 4119def int_hexagon_V6_vaslw_acc_128B : 4120Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vaslw_acc_128B">; 4121 4122def int_hexagon_V6_vaslwv : 4123Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaslwv">; 4124 4125def int_hexagon_V6_vaslwv_128B : 4126Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaslwv_128B">; 4127 4128def int_hexagon_V6_vasrh : 4129Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vasrh">; 4130 4131def int_hexagon_V6_vasrh_128B : 4132Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vasrh_128B">; 4133 4134def int_hexagon_V6_vasrhbrndsat : 4135Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhbrndsat">; 4136 4137def int_hexagon_V6_vasrhbrndsat_128B : 4138Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhbrndsat_128B">; 4139 4140def int_hexagon_V6_vasrhubrndsat : 4141Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhubrndsat">; 4142 4143def int_hexagon_V6_vasrhubrndsat_128B : 4144Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhubrndsat_128B">; 4145 4146def int_hexagon_V6_vasrhubsat : 4147Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhubsat">; 4148 4149def int_hexagon_V6_vasrhubsat_128B : 4150Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhubsat_128B">; 4151 4152def int_hexagon_V6_vasrhv : 4153Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vasrhv">; 4154 4155def int_hexagon_V6_vasrhv_128B : 4156Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vasrhv_128B">; 4157 4158def int_hexagon_V6_vasrw : 4159Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vasrw">; 4160 4161def int_hexagon_V6_vasrw_128B : 4162Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vasrw_128B">; 4163 4164def int_hexagon_V6_vasrw_acc : 4165Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrw_acc">; 4166 4167def int_hexagon_V6_vasrw_acc_128B : 4168Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrw_acc_128B">; 4169 4170def int_hexagon_V6_vasrwh : 4171Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwh">; 4172 4173def int_hexagon_V6_vasrwh_128B : 4174Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwh_128B">; 4175 4176def int_hexagon_V6_vasrwhrndsat : 4177Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwhrndsat">; 4178 4179def int_hexagon_V6_vasrwhrndsat_128B : 4180Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwhrndsat_128B">; 4181 4182def int_hexagon_V6_vasrwhsat : 4183Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwhsat">; 4184 4185def int_hexagon_V6_vasrwhsat_128B : 4186Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwhsat_128B">; 4187 4188def int_hexagon_V6_vasrwuhsat : 4189Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwuhsat">; 4190 4191def int_hexagon_V6_vasrwuhsat_128B : 4192Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwuhsat_128B">; 4193 4194def int_hexagon_V6_vasrwv : 4195Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vasrwv">; 4196 4197def int_hexagon_V6_vasrwv_128B : 4198Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vasrwv_128B">; 4199 4200def int_hexagon_V6_vassign : 4201Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vassign">; 4202 4203def int_hexagon_V6_vassign_128B : 4204Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vassign_128B">; 4205 4206def int_hexagon_V6_vassignp : 4207Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vassignp">; 4208 4209def int_hexagon_V6_vassignp_128B : 4210Hexagon_v64i32_v64i32_Intrinsic<"HEXAGON_V6_vassignp_128B">; 4211 4212def int_hexagon_V6_vavgh : 4213Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgh">; 4214 4215def int_hexagon_V6_vavgh_128B : 4216Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgh_128B">; 4217 4218def int_hexagon_V6_vavghrnd : 4219Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavghrnd">; 4220 4221def int_hexagon_V6_vavghrnd_128B : 4222Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavghrnd_128B">; 4223 4224def int_hexagon_V6_vavgub : 4225Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgub">; 4226 4227def int_hexagon_V6_vavgub_128B : 4228Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgub_128B">; 4229 4230def int_hexagon_V6_vavgubrnd : 4231Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgubrnd">; 4232 4233def int_hexagon_V6_vavgubrnd_128B : 4234Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgubrnd_128B">; 4235 4236def int_hexagon_V6_vavguh : 4237Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguh">; 4238 4239def int_hexagon_V6_vavguh_128B : 4240Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguh_128B">; 4241 4242def int_hexagon_V6_vavguhrnd : 4243Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguhrnd">; 4244 4245def int_hexagon_V6_vavguhrnd_128B : 4246Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguhrnd_128B">; 4247 4248def int_hexagon_V6_vavgw : 4249Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgw">; 4250 4251def int_hexagon_V6_vavgw_128B : 4252Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgw_128B">; 4253 4254def int_hexagon_V6_vavgwrnd : 4255Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgwrnd">; 4256 4257def int_hexagon_V6_vavgwrnd_128B : 4258Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgwrnd_128B">; 4259 4260def int_hexagon_V6_vcl0h : 4261Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vcl0h">; 4262 4263def int_hexagon_V6_vcl0h_128B : 4264Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vcl0h_128B">; 4265 4266def int_hexagon_V6_vcl0w : 4267Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vcl0w">; 4268 4269def int_hexagon_V6_vcl0w_128B : 4270Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vcl0w_128B">; 4271 4272def int_hexagon_V6_vcombine : 4273Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vcombine">; 4274 4275def int_hexagon_V6_vcombine_128B : 4276Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vcombine_128B">; 4277 4278def int_hexagon_V6_vd0 : 4279Hexagon_v16i32__Intrinsic<"HEXAGON_V6_vd0">; 4280 4281def int_hexagon_V6_vd0_128B : 4282Hexagon_v32i32__Intrinsic<"HEXAGON_V6_vd0_128B">; 4283 4284def int_hexagon_V6_vdealb : 4285Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vdealb">; 4286 4287def int_hexagon_V6_vdealb_128B : 4288Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vdealb_128B">; 4289 4290def int_hexagon_V6_vdealb4w : 4291Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vdealb4w">; 4292 4293def int_hexagon_V6_vdealb4w_128B : 4294Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vdealb4w_128B">; 4295 4296def int_hexagon_V6_vdealh : 4297Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vdealh">; 4298 4299def int_hexagon_V6_vdealh_128B : 4300Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vdealh_128B">; 4301 4302def int_hexagon_V6_vdealvdd : 4303Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdealvdd">; 4304 4305def int_hexagon_V6_vdealvdd_128B : 4306Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdealvdd_128B">; 4307 4308def int_hexagon_V6_vdelta : 4309Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vdelta">; 4310 4311def int_hexagon_V6_vdelta_128B : 4312Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vdelta_128B">; 4313 4314def int_hexagon_V6_vdmpybus : 4315Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vdmpybus">; 4316 4317def int_hexagon_V6_vdmpybus_128B : 4318Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_128B">; 4319 4320def int_hexagon_V6_vdmpybus_acc : 4321Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_acc">; 4322 4323def int_hexagon_V6_vdmpybus_acc_128B : 4324Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_acc_128B">; 4325 4326def int_hexagon_V6_vdmpybus_dv : 4327Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_dv">; 4328 4329def int_hexagon_V6_vdmpybus_dv_128B : 4330Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_dv_128B">; 4331 4332def int_hexagon_V6_vdmpybus_dv_acc : 4333Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_dv_acc">; 4334 4335def int_hexagon_V6_vdmpybus_dv_acc_128B : 4336Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_dv_acc_128B">; 4337 4338def int_hexagon_V6_vdmpyhb : 4339Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb">; 4340 4341def int_hexagon_V6_vdmpyhb_128B : 4342Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_128B">; 4343 4344def int_hexagon_V6_vdmpyhb_acc : 4345Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_acc">; 4346 4347def int_hexagon_V6_vdmpyhb_acc_128B : 4348Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_acc_128B">; 4349 4350def int_hexagon_V6_vdmpyhb_dv : 4351Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_dv">; 4352 4353def int_hexagon_V6_vdmpyhb_dv_128B : 4354Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_dv_128B">; 4355 4356def int_hexagon_V6_vdmpyhb_dv_acc : 4357Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_dv_acc">; 4358 4359def int_hexagon_V6_vdmpyhb_dv_acc_128B : 4360Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_dv_acc_128B">; 4361 4362def int_hexagon_V6_vdmpyhisat : 4363Hexagon_v16i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat">; 4364 4365def int_hexagon_V6_vdmpyhisat_128B : 4366Hexagon_v32i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat_128B">; 4367 4368def int_hexagon_V6_vdmpyhisat_acc : 4369Hexagon_v16i32_v16i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat_acc">; 4370 4371def int_hexagon_V6_vdmpyhisat_acc_128B : 4372Hexagon_v32i32_v32i32v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat_acc_128B">; 4373 4374def int_hexagon_V6_vdmpyhsat : 4375Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsat">; 4376 4377def int_hexagon_V6_vdmpyhsat_128B : 4378Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsat_128B">; 4379 4380def int_hexagon_V6_vdmpyhsat_acc : 4381Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsat_acc">; 4382 4383def int_hexagon_V6_vdmpyhsat_acc_128B : 4384Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsat_acc_128B">; 4385 4386def int_hexagon_V6_vdmpyhsuisat : 4387Hexagon_v16i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat">; 4388 4389def int_hexagon_V6_vdmpyhsuisat_128B : 4390Hexagon_v32i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat_128B">; 4391 4392def int_hexagon_V6_vdmpyhsuisat_acc : 4393Hexagon_v16i32_v16i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat_acc">; 4394 4395def int_hexagon_V6_vdmpyhsuisat_acc_128B : 4396Hexagon_v32i32_v32i32v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat_acc_128B">; 4397 4398def int_hexagon_V6_vdmpyhsusat : 4399Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsusat">; 4400 4401def int_hexagon_V6_vdmpyhsusat_128B : 4402Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsusat_128B">; 4403 4404def int_hexagon_V6_vdmpyhsusat_acc : 4405Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsusat_acc">; 4406 4407def int_hexagon_V6_vdmpyhsusat_acc_128B : 4408Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsusat_acc_128B">; 4409 4410def int_hexagon_V6_vdmpyhvsat : 4411Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat">; 4412 4413def int_hexagon_V6_vdmpyhvsat_128B : 4414Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat_128B">; 4415 4416def int_hexagon_V6_vdmpyhvsat_acc : 4417Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat_acc">; 4418 4419def int_hexagon_V6_vdmpyhvsat_acc_128B : 4420Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat_acc_128B">; 4421 4422def int_hexagon_V6_vdsaduh : 4423Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdsaduh">; 4424 4425def int_hexagon_V6_vdsaduh_128B : 4426Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdsaduh_128B">; 4427 4428def int_hexagon_V6_vdsaduh_acc : 4429Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdsaduh_acc">; 4430 4431def int_hexagon_V6_vdsaduh_acc_128B : 4432Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vdsaduh_acc_128B">; 4433 4434def int_hexagon_V6_veqb : 4435Hexagon_v64i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_veqb">; 4436 4437def int_hexagon_V6_veqb_128B : 4438Hexagon_v128i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_veqb_128B">; 4439 4440def int_hexagon_V6_veqb_and : 4441Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqb_and">; 4442 4443def int_hexagon_V6_veqb_and_128B : 4444Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqb_and_128B">; 4445 4446def int_hexagon_V6_veqb_or : 4447Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqb_or">; 4448 4449def int_hexagon_V6_veqb_or_128B : 4450Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqb_or_128B">; 4451 4452def int_hexagon_V6_veqb_xor : 4453Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqb_xor">; 4454 4455def int_hexagon_V6_veqb_xor_128B : 4456Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqb_xor_128B">; 4457 4458def int_hexagon_V6_veqh : 4459Hexagon_v64i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_veqh">; 4460 4461def int_hexagon_V6_veqh_128B : 4462Hexagon_v128i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_veqh_128B">; 4463 4464def int_hexagon_V6_veqh_and : 4465Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqh_and">; 4466 4467def int_hexagon_V6_veqh_and_128B : 4468Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqh_and_128B">; 4469 4470def int_hexagon_V6_veqh_or : 4471Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqh_or">; 4472 4473def int_hexagon_V6_veqh_or_128B : 4474Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqh_or_128B">; 4475 4476def int_hexagon_V6_veqh_xor : 4477Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqh_xor">; 4478 4479def int_hexagon_V6_veqh_xor_128B : 4480Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqh_xor_128B">; 4481 4482def int_hexagon_V6_veqw : 4483Hexagon_v64i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_veqw">; 4484 4485def int_hexagon_V6_veqw_128B : 4486Hexagon_v128i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_veqw_128B">; 4487 4488def int_hexagon_V6_veqw_and : 4489Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqw_and">; 4490 4491def int_hexagon_V6_veqw_and_128B : 4492Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqw_and_128B">; 4493 4494def int_hexagon_V6_veqw_or : 4495Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqw_or">; 4496 4497def int_hexagon_V6_veqw_or_128B : 4498Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqw_or_128B">; 4499 4500def int_hexagon_V6_veqw_xor : 4501Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqw_xor">; 4502 4503def int_hexagon_V6_veqw_xor_128B : 4504Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqw_xor_128B">; 4505 4506def int_hexagon_V6_vgtb : 4507Hexagon_v64i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtb">; 4508 4509def int_hexagon_V6_vgtb_128B : 4510Hexagon_v128i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtb_128B">; 4511 4512def int_hexagon_V6_vgtb_and : 4513Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtb_and">; 4514 4515def int_hexagon_V6_vgtb_and_128B : 4516Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtb_and_128B">; 4517 4518def int_hexagon_V6_vgtb_or : 4519Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtb_or">; 4520 4521def int_hexagon_V6_vgtb_or_128B : 4522Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtb_or_128B">; 4523 4524def int_hexagon_V6_vgtb_xor : 4525Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtb_xor">; 4526 4527def int_hexagon_V6_vgtb_xor_128B : 4528Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtb_xor_128B">; 4529 4530def int_hexagon_V6_vgth : 4531Hexagon_v64i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgth">; 4532 4533def int_hexagon_V6_vgth_128B : 4534Hexagon_v128i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgth_128B">; 4535 4536def int_hexagon_V6_vgth_and : 4537Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgth_and">; 4538 4539def int_hexagon_V6_vgth_and_128B : 4540Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgth_and_128B">; 4541 4542def int_hexagon_V6_vgth_or : 4543Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgth_or">; 4544 4545def int_hexagon_V6_vgth_or_128B : 4546Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgth_or_128B">; 4547 4548def int_hexagon_V6_vgth_xor : 4549Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgth_xor">; 4550 4551def int_hexagon_V6_vgth_xor_128B : 4552Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgth_xor_128B">; 4553 4554def int_hexagon_V6_vgtub : 4555Hexagon_v64i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtub">; 4556 4557def int_hexagon_V6_vgtub_128B : 4558Hexagon_v128i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtub_128B">; 4559 4560def int_hexagon_V6_vgtub_and : 4561Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtub_and">; 4562 4563def int_hexagon_V6_vgtub_and_128B : 4564Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtub_and_128B">; 4565 4566def int_hexagon_V6_vgtub_or : 4567Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtub_or">; 4568 4569def int_hexagon_V6_vgtub_or_128B : 4570Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtub_or_128B">; 4571 4572def int_hexagon_V6_vgtub_xor : 4573Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtub_xor">; 4574 4575def int_hexagon_V6_vgtub_xor_128B : 4576Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtub_xor_128B">; 4577 4578def int_hexagon_V6_vgtuh : 4579Hexagon_v64i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuh">; 4580 4581def int_hexagon_V6_vgtuh_128B : 4582Hexagon_v128i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuh_128B">; 4583 4584def int_hexagon_V6_vgtuh_and : 4585Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuh_and">; 4586 4587def int_hexagon_V6_vgtuh_and_128B : 4588Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuh_and_128B">; 4589 4590def int_hexagon_V6_vgtuh_or : 4591Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuh_or">; 4592 4593def int_hexagon_V6_vgtuh_or_128B : 4594Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuh_or_128B">; 4595 4596def int_hexagon_V6_vgtuh_xor : 4597Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuh_xor">; 4598 4599def int_hexagon_V6_vgtuh_xor_128B : 4600Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuh_xor_128B">; 4601 4602def int_hexagon_V6_vgtuw : 4603Hexagon_v64i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuw">; 4604 4605def int_hexagon_V6_vgtuw_128B : 4606Hexagon_v128i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuw_128B">; 4607 4608def int_hexagon_V6_vgtuw_and : 4609Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuw_and">; 4610 4611def int_hexagon_V6_vgtuw_and_128B : 4612Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuw_and_128B">; 4613 4614def int_hexagon_V6_vgtuw_or : 4615Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuw_or">; 4616 4617def int_hexagon_V6_vgtuw_or_128B : 4618Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuw_or_128B">; 4619 4620def int_hexagon_V6_vgtuw_xor : 4621Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuw_xor">; 4622 4623def int_hexagon_V6_vgtuw_xor_128B : 4624Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuw_xor_128B">; 4625 4626def int_hexagon_V6_vgtw : 4627Hexagon_v64i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtw">; 4628 4629def int_hexagon_V6_vgtw_128B : 4630Hexagon_v128i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtw_128B">; 4631 4632def int_hexagon_V6_vgtw_and : 4633Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtw_and">; 4634 4635def int_hexagon_V6_vgtw_and_128B : 4636Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtw_and_128B">; 4637 4638def int_hexagon_V6_vgtw_or : 4639Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtw_or">; 4640 4641def int_hexagon_V6_vgtw_or_128B : 4642Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtw_or_128B">; 4643 4644def int_hexagon_V6_vgtw_xor : 4645Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtw_xor">; 4646 4647def int_hexagon_V6_vgtw_xor_128B : 4648Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtw_xor_128B">; 4649 4650def int_hexagon_V6_vinsertwr : 4651Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vinsertwr">; 4652 4653def int_hexagon_V6_vinsertwr_128B : 4654Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vinsertwr_128B">; 4655 4656def int_hexagon_V6_vlalignb : 4657Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlalignb">; 4658 4659def int_hexagon_V6_vlalignb_128B : 4660Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlalignb_128B">; 4661 4662def int_hexagon_V6_vlalignbi : 4663Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlalignbi", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 4664 4665def int_hexagon_V6_vlalignbi_128B : 4666Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlalignbi_128B", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 4667 4668def int_hexagon_V6_vlsrh : 4669Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vlsrh">; 4670 4671def int_hexagon_V6_vlsrh_128B : 4672Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vlsrh_128B">; 4673 4674def int_hexagon_V6_vlsrhv : 4675Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vlsrhv">; 4676 4677def int_hexagon_V6_vlsrhv_128B : 4678Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vlsrhv_128B">; 4679 4680def int_hexagon_V6_vlsrw : 4681Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vlsrw">; 4682 4683def int_hexagon_V6_vlsrw_128B : 4684Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vlsrw_128B">; 4685 4686def int_hexagon_V6_vlsrwv : 4687Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vlsrwv">; 4688 4689def int_hexagon_V6_vlsrwv_128B : 4690Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vlsrwv_128B">; 4691 4692def int_hexagon_V6_vlutvvb : 4693Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb">; 4694 4695def int_hexagon_V6_vlutvvb_128B : 4696Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_128B">; 4697 4698def int_hexagon_V6_vlutvvb_oracc : 4699Hexagon_v16i32_v16i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracc">; 4700 4701def int_hexagon_V6_vlutvvb_oracc_128B : 4702Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracc_128B">; 4703 4704def int_hexagon_V6_vlutvwh : 4705Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh">; 4706 4707def int_hexagon_V6_vlutvwh_128B : 4708Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_128B">; 4709 4710def int_hexagon_V6_vlutvwh_oracc : 4711Hexagon_v32i32_v32i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracc">; 4712 4713def int_hexagon_V6_vlutvwh_oracc_128B : 4714Hexagon_v64i32_v64i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracc_128B">; 4715 4716def int_hexagon_V6_vmaxh : 4717Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxh">; 4718 4719def int_hexagon_V6_vmaxh_128B : 4720Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxh_128B">; 4721 4722def int_hexagon_V6_vmaxub : 4723Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxub">; 4724 4725def int_hexagon_V6_vmaxub_128B : 4726Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxub_128B">; 4727 4728def int_hexagon_V6_vmaxuh : 4729Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxuh">; 4730 4731def int_hexagon_V6_vmaxuh_128B : 4732Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxuh_128B">; 4733 4734def int_hexagon_V6_vmaxw : 4735Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxw">; 4736 4737def int_hexagon_V6_vmaxw_128B : 4738Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxw_128B">; 4739 4740def int_hexagon_V6_vminh : 4741Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminh">; 4742 4743def int_hexagon_V6_vminh_128B : 4744Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminh_128B">; 4745 4746def int_hexagon_V6_vminub : 4747Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminub">; 4748 4749def int_hexagon_V6_vminub_128B : 4750Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminub_128B">; 4751 4752def int_hexagon_V6_vminuh : 4753Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminuh">; 4754 4755def int_hexagon_V6_vminuh_128B : 4756Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminuh_128B">; 4757 4758def int_hexagon_V6_vminw : 4759Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminw">; 4760 4761def int_hexagon_V6_vminw_128B : 4762Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminw_128B">; 4763 4764def int_hexagon_V6_vmpabus : 4765Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpabus">; 4766 4767def int_hexagon_V6_vmpabus_128B : 4768Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vmpabus_128B">; 4769 4770def int_hexagon_V6_vmpabus_acc : 4771Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpabus_acc">; 4772 4773def int_hexagon_V6_vmpabus_acc_128B : 4774Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vmpabus_acc_128B">; 4775 4776def int_hexagon_V6_vmpabusv : 4777Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpabusv">; 4778 4779def int_hexagon_V6_vmpabusv_128B : 4780Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vmpabusv_128B">; 4781 4782def int_hexagon_V6_vmpabuuv : 4783Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpabuuv">; 4784 4785def int_hexagon_V6_vmpabuuv_128B : 4786Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vmpabuuv_128B">; 4787 4788def int_hexagon_V6_vmpahb : 4789Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpahb">; 4790 4791def int_hexagon_V6_vmpahb_128B : 4792Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vmpahb_128B">; 4793 4794def int_hexagon_V6_vmpahb_acc : 4795Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpahb_acc">; 4796 4797def int_hexagon_V6_vmpahb_acc_128B : 4798Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vmpahb_acc_128B">; 4799 4800def int_hexagon_V6_vmpybus : 4801Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpybus">; 4802 4803def int_hexagon_V6_vmpybus_128B : 4804Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpybus_128B">; 4805 4806def int_hexagon_V6_vmpybus_acc : 4807Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpybus_acc">; 4808 4809def int_hexagon_V6_vmpybus_acc_128B : 4810Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpybus_acc_128B">; 4811 4812def int_hexagon_V6_vmpybusv : 4813Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybusv">; 4814 4815def int_hexagon_V6_vmpybusv_128B : 4816Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybusv_128B">; 4817 4818def int_hexagon_V6_vmpybusv_acc : 4819Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybusv_acc">; 4820 4821def int_hexagon_V6_vmpybusv_acc_128B : 4822Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybusv_acc_128B">; 4823 4824def int_hexagon_V6_vmpybv : 4825Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybv">; 4826 4827def int_hexagon_V6_vmpybv_128B : 4828Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybv_128B">; 4829 4830def int_hexagon_V6_vmpybv_acc : 4831Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybv_acc">; 4832 4833def int_hexagon_V6_vmpybv_acc_128B : 4834Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybv_acc_128B">; 4835 4836def int_hexagon_V6_vmpyewuh : 4837Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyewuh">; 4838 4839def int_hexagon_V6_vmpyewuh_128B : 4840Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyewuh_128B">; 4841 4842def int_hexagon_V6_vmpyh : 4843Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyh">; 4844 4845def int_hexagon_V6_vmpyh_128B : 4846Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyh_128B">; 4847 4848def int_hexagon_V6_vmpyhsat_acc : 4849Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyhsat_acc">; 4850 4851def int_hexagon_V6_vmpyhsat_acc_128B : 4852Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyhsat_acc_128B">; 4853 4854def int_hexagon_V6_vmpyhsrs : 4855Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyhsrs">; 4856 4857def int_hexagon_V6_vmpyhsrs_128B : 4858Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyhsrs_128B">; 4859 4860def int_hexagon_V6_vmpyhss : 4861Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyhss">; 4862 4863def int_hexagon_V6_vmpyhss_128B : 4864Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyhss_128B">; 4865 4866def int_hexagon_V6_vmpyhus : 4867Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhus">; 4868 4869def int_hexagon_V6_vmpyhus_128B : 4870Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhus_128B">; 4871 4872def int_hexagon_V6_vmpyhus_acc : 4873Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhus_acc">; 4874 4875def int_hexagon_V6_vmpyhus_acc_128B : 4876Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhus_acc_128B">; 4877 4878def int_hexagon_V6_vmpyhv : 4879Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhv">; 4880 4881def int_hexagon_V6_vmpyhv_128B : 4882Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhv_128B">; 4883 4884def int_hexagon_V6_vmpyhv_acc : 4885Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhv_acc">; 4886 4887def int_hexagon_V6_vmpyhv_acc_128B : 4888Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhv_acc_128B">; 4889 4890def int_hexagon_V6_vmpyhvsrs : 4891Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhvsrs">; 4892 4893def int_hexagon_V6_vmpyhvsrs_128B : 4894Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhvsrs_128B">; 4895 4896def int_hexagon_V6_vmpyieoh : 4897Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyieoh">; 4898 4899def int_hexagon_V6_vmpyieoh_128B : 4900Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyieoh_128B">; 4901 4902def int_hexagon_V6_vmpyiewh_acc : 4903Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiewh_acc">; 4904 4905def int_hexagon_V6_vmpyiewh_acc_128B : 4906Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiewh_acc_128B">; 4907 4908def int_hexagon_V6_vmpyiewuh : 4909Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiewuh">; 4910 4911def int_hexagon_V6_vmpyiewuh_128B : 4912Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiewuh_128B">; 4913 4914def int_hexagon_V6_vmpyiewuh_acc : 4915Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiewuh_acc">; 4916 4917def int_hexagon_V6_vmpyiewuh_acc_128B : 4918Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiewuh_acc_128B">; 4919 4920def int_hexagon_V6_vmpyih : 4921Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyih">; 4922 4923def int_hexagon_V6_vmpyih_128B : 4924Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyih_128B">; 4925 4926def int_hexagon_V6_vmpyih_acc : 4927Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyih_acc">; 4928 4929def int_hexagon_V6_vmpyih_acc_128B : 4930Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyih_acc_128B">; 4931 4932def int_hexagon_V6_vmpyihb : 4933Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyihb">; 4934 4935def int_hexagon_V6_vmpyihb_128B : 4936Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyihb_128B">; 4937 4938def int_hexagon_V6_vmpyihb_acc : 4939Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyihb_acc">; 4940 4941def int_hexagon_V6_vmpyihb_acc_128B : 4942Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyihb_acc_128B">; 4943 4944def int_hexagon_V6_vmpyiowh : 4945Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiowh">; 4946 4947def int_hexagon_V6_vmpyiowh_128B : 4948Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiowh_128B">; 4949 4950def int_hexagon_V6_vmpyiwb : 4951Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb">; 4952 4953def int_hexagon_V6_vmpyiwb_128B : 4954Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb_128B">; 4955 4956def int_hexagon_V6_vmpyiwb_acc : 4957Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb_acc">; 4958 4959def int_hexagon_V6_vmpyiwb_acc_128B : 4960Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb_acc_128B">; 4961 4962def int_hexagon_V6_vmpyiwh : 4963Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh">; 4964 4965def int_hexagon_V6_vmpyiwh_128B : 4966Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh_128B">; 4967 4968def int_hexagon_V6_vmpyiwh_acc : 4969Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh_acc">; 4970 4971def int_hexagon_V6_vmpyiwh_acc_128B : 4972Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh_acc_128B">; 4973 4974def int_hexagon_V6_vmpyowh : 4975Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh">; 4976 4977def int_hexagon_V6_vmpyowh_128B : 4978Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_128B">; 4979 4980def int_hexagon_V6_vmpyowh_rnd : 4981Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd">; 4982 4983def int_hexagon_V6_vmpyowh_rnd_128B : 4984Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd_128B">; 4985 4986def int_hexagon_V6_vmpyowh_rnd_sacc : 4987Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd_sacc">; 4988 4989def int_hexagon_V6_vmpyowh_rnd_sacc_128B : 4990Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd_sacc_128B">; 4991 4992def int_hexagon_V6_vmpyowh_sacc : 4993Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_sacc">; 4994 4995def int_hexagon_V6_vmpyowh_sacc_128B : 4996Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_sacc_128B">; 4997 4998def int_hexagon_V6_vmpyub : 4999Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyub">; 5000 5001def int_hexagon_V6_vmpyub_128B : 5002Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyub_128B">; 5003 5004def int_hexagon_V6_vmpyub_acc : 5005Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyub_acc">; 5006 5007def int_hexagon_V6_vmpyub_acc_128B : 5008Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyub_acc_128B">; 5009 5010def int_hexagon_V6_vmpyubv : 5011Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyubv">; 5012 5013def int_hexagon_V6_vmpyubv_128B : 5014Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyubv_128B">; 5015 5016def int_hexagon_V6_vmpyubv_acc : 5017Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyubv_acc">; 5018 5019def int_hexagon_V6_vmpyubv_acc_128B : 5020Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyubv_acc_128B">; 5021 5022def int_hexagon_V6_vmpyuh : 5023Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyuh">; 5024 5025def int_hexagon_V6_vmpyuh_128B : 5026Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyuh_128B">; 5027 5028def int_hexagon_V6_vmpyuh_acc : 5029Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyuh_acc">; 5030 5031def int_hexagon_V6_vmpyuh_acc_128B : 5032Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyuh_acc_128B">; 5033 5034def int_hexagon_V6_vmpyuhv : 5035Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyuhv">; 5036 5037def int_hexagon_V6_vmpyuhv_128B : 5038Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyuhv_128B">; 5039 5040def int_hexagon_V6_vmpyuhv_acc : 5041Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyuhv_acc">; 5042 5043def int_hexagon_V6_vmpyuhv_acc_128B : 5044Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyuhv_acc_128B">; 5045 5046def int_hexagon_V6_vmux : 5047Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vmux">; 5048 5049def int_hexagon_V6_vmux_128B : 5050Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vmux_128B">; 5051 5052def int_hexagon_V6_vnavgh : 5053Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgh">; 5054 5055def int_hexagon_V6_vnavgh_128B : 5056Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgh_128B">; 5057 5058def int_hexagon_V6_vnavgub : 5059Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgub">; 5060 5061def int_hexagon_V6_vnavgub_128B : 5062Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgub_128B">; 5063 5064def int_hexagon_V6_vnavgw : 5065Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgw">; 5066 5067def int_hexagon_V6_vnavgw_128B : 5068Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgw_128B">; 5069 5070def int_hexagon_V6_vnormamth : 5071Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vnormamth">; 5072 5073def int_hexagon_V6_vnormamth_128B : 5074Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vnormamth_128B">; 5075 5076def int_hexagon_V6_vnormamtw : 5077Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vnormamtw">; 5078 5079def int_hexagon_V6_vnormamtw_128B : 5080Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vnormamtw_128B">; 5081 5082def int_hexagon_V6_vnot : 5083Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vnot">; 5084 5085def int_hexagon_V6_vnot_128B : 5086Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vnot_128B">; 5087 5088def int_hexagon_V6_vor : 5089Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vor">; 5090 5091def int_hexagon_V6_vor_128B : 5092Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vor_128B">; 5093 5094def int_hexagon_V6_vpackeb : 5095Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackeb">; 5096 5097def int_hexagon_V6_vpackeb_128B : 5098Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackeb_128B">; 5099 5100def int_hexagon_V6_vpackeh : 5101Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackeh">; 5102 5103def int_hexagon_V6_vpackeh_128B : 5104Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackeh_128B">; 5105 5106def int_hexagon_V6_vpackhb_sat : 5107Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackhb_sat">; 5108 5109def int_hexagon_V6_vpackhb_sat_128B : 5110Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackhb_sat_128B">; 5111 5112def int_hexagon_V6_vpackhub_sat : 5113Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackhub_sat">; 5114 5115def int_hexagon_V6_vpackhub_sat_128B : 5116Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackhub_sat_128B">; 5117 5118def int_hexagon_V6_vpackob : 5119Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackob">; 5120 5121def int_hexagon_V6_vpackob_128B : 5122Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackob_128B">; 5123 5124def int_hexagon_V6_vpackoh : 5125Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackoh">; 5126 5127def int_hexagon_V6_vpackoh_128B : 5128Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackoh_128B">; 5129 5130def int_hexagon_V6_vpackwh_sat : 5131Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackwh_sat">; 5132 5133def int_hexagon_V6_vpackwh_sat_128B : 5134Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackwh_sat_128B">; 5135 5136def int_hexagon_V6_vpackwuh_sat : 5137Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackwuh_sat">; 5138 5139def int_hexagon_V6_vpackwuh_sat_128B : 5140Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackwuh_sat_128B">; 5141 5142def int_hexagon_V6_vpopcounth : 5143Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vpopcounth">; 5144 5145def int_hexagon_V6_vpopcounth_128B : 5146Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vpopcounth_128B">; 5147 5148def int_hexagon_V6_vrdelta : 5149Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrdelta">; 5150 5151def int_hexagon_V6_vrdelta_128B : 5152Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrdelta_128B">; 5153 5154def int_hexagon_V6_vrmpybus : 5155Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vrmpybus">; 5156 5157def int_hexagon_V6_vrmpybus_128B : 5158Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vrmpybus_128B">; 5159 5160def int_hexagon_V6_vrmpybus_acc : 5161Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vrmpybus_acc">; 5162 5163def int_hexagon_V6_vrmpybus_acc_128B : 5164Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vrmpybus_acc_128B">; 5165 5166def int_hexagon_V6_vrmpybusi : 5167Hexagon_v32i32_v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 5168 5169def int_hexagon_V6_vrmpybusi_128B : 5170Hexagon_v64i32_v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi_128B", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 5171 5172def int_hexagon_V6_vrmpybusi_acc : 5173Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi_acc", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 5174 5175def int_hexagon_V6_vrmpybusi_acc_128B : 5176Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi_acc_128B", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 5177 5178def int_hexagon_V6_vrmpybusv : 5179Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpybusv">; 5180 5181def int_hexagon_V6_vrmpybusv_128B : 5182Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpybusv_128B">; 5183 5184def int_hexagon_V6_vrmpybusv_acc : 5185Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpybusv_acc">; 5186 5187def int_hexagon_V6_vrmpybusv_acc_128B : 5188Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpybusv_acc_128B">; 5189 5190def int_hexagon_V6_vrmpybv : 5191Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpybv">; 5192 5193def int_hexagon_V6_vrmpybv_128B : 5194Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpybv_128B">; 5195 5196def int_hexagon_V6_vrmpybv_acc : 5197Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpybv_acc">; 5198 5199def int_hexagon_V6_vrmpybv_acc_128B : 5200Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpybv_acc_128B">; 5201 5202def int_hexagon_V6_vrmpyub : 5203Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vrmpyub">; 5204 5205def int_hexagon_V6_vrmpyub_128B : 5206Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vrmpyub_128B">; 5207 5208def int_hexagon_V6_vrmpyub_acc : 5209Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vrmpyub_acc">; 5210 5211def int_hexagon_V6_vrmpyub_acc_128B : 5212Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vrmpyub_acc_128B">; 5213 5214def int_hexagon_V6_vrmpyubi : 5215Hexagon_v32i32_v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 5216 5217def int_hexagon_V6_vrmpyubi_128B : 5218Hexagon_v64i32_v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi_128B", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 5219 5220def int_hexagon_V6_vrmpyubi_acc : 5221Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi_acc", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 5222 5223def int_hexagon_V6_vrmpyubi_acc_128B : 5224Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi_acc_128B", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 5225 5226def int_hexagon_V6_vrmpyubv : 5227Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpyubv">; 5228 5229def int_hexagon_V6_vrmpyubv_128B : 5230Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpyubv_128B">; 5231 5232def int_hexagon_V6_vrmpyubv_acc : 5233Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpyubv_acc">; 5234 5235def int_hexagon_V6_vrmpyubv_acc_128B : 5236Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpyubv_acc_128B">; 5237 5238def int_hexagon_V6_vror : 5239Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vror">; 5240 5241def int_hexagon_V6_vror_128B : 5242Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vror_128B">; 5243 5244def int_hexagon_V6_vroundhb : 5245Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vroundhb">; 5246 5247def int_hexagon_V6_vroundhb_128B : 5248Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vroundhb_128B">; 5249 5250def int_hexagon_V6_vroundhub : 5251Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vroundhub">; 5252 5253def int_hexagon_V6_vroundhub_128B : 5254Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vroundhub_128B">; 5255 5256def int_hexagon_V6_vroundwh : 5257Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vroundwh">; 5258 5259def int_hexagon_V6_vroundwh_128B : 5260Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vroundwh_128B">; 5261 5262def int_hexagon_V6_vroundwuh : 5263Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vroundwuh">; 5264 5265def int_hexagon_V6_vroundwuh_128B : 5266Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vroundwuh_128B">; 5267 5268def int_hexagon_V6_vrsadubi : 5269Hexagon_v32i32_v32i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 5270 5271def int_hexagon_V6_vrsadubi_128B : 5272Hexagon_v64i32_v64i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi_128B", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 5273 5274def int_hexagon_V6_vrsadubi_acc : 5275Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi_acc", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 5276 5277def int_hexagon_V6_vrsadubi_acc_128B : 5278Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi_acc_128B", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 5279 5280def int_hexagon_V6_vsathub : 5281Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsathub">; 5282 5283def int_hexagon_V6_vsathub_128B : 5284Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsathub_128B">; 5285 5286def int_hexagon_V6_vsatwh : 5287Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsatwh">; 5288 5289def int_hexagon_V6_vsatwh_128B : 5290Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsatwh_128B">; 5291 5292def int_hexagon_V6_vsb : 5293Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vsb">; 5294 5295def int_hexagon_V6_vsb_128B : 5296Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vsb_128B">; 5297 5298def int_hexagon_V6_vsh : 5299Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vsh">; 5300 5301def int_hexagon_V6_vsh_128B : 5302Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vsh_128B">; 5303 5304def int_hexagon_V6_vshufeh : 5305Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufeh">; 5306 5307def int_hexagon_V6_vshufeh_128B : 5308Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufeh_128B">; 5309 5310def int_hexagon_V6_vshuffb : 5311Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vshuffb">; 5312 5313def int_hexagon_V6_vshuffb_128B : 5314Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vshuffb_128B">; 5315 5316def int_hexagon_V6_vshuffeb : 5317Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshuffeb">; 5318 5319def int_hexagon_V6_vshuffeb_128B : 5320Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshuffeb_128B">; 5321 5322def int_hexagon_V6_vshuffh : 5323Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vshuffh">; 5324 5325def int_hexagon_V6_vshuffh_128B : 5326Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vshuffh_128B">; 5327 5328def int_hexagon_V6_vshuffob : 5329Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshuffob">; 5330 5331def int_hexagon_V6_vshuffob_128B : 5332Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshuffob_128B">; 5333 5334def int_hexagon_V6_vshuffvdd : 5335Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vshuffvdd">; 5336 5337def int_hexagon_V6_vshuffvdd_128B : 5338Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vshuffvdd_128B">; 5339 5340def int_hexagon_V6_vshufoeb : 5341Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufoeb">; 5342 5343def int_hexagon_V6_vshufoeb_128B : 5344Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufoeb_128B">; 5345 5346def int_hexagon_V6_vshufoeh : 5347Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufoeh">; 5348 5349def int_hexagon_V6_vshufoeh_128B : 5350Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufoeh_128B">; 5351 5352def int_hexagon_V6_vshufoh : 5353Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufoh">; 5354 5355def int_hexagon_V6_vshufoh_128B : 5356Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufoh_128B">; 5357 5358def int_hexagon_V6_vsubb : 5359Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubb">; 5360 5361def int_hexagon_V6_vsubb_128B : 5362Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubb_128B">; 5363 5364def int_hexagon_V6_vsubb_dv : 5365Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubb_dv">; 5366 5367def int_hexagon_V6_vsubb_dv_128B : 5368Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubb_dv_128B">; 5369 5370def int_hexagon_V6_vsubbnq : 5371Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubbnq">; 5372 5373def int_hexagon_V6_vsubbnq_128B : 5374Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubbnq_128B">; 5375 5376def int_hexagon_V6_vsubbq : 5377Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubbq">; 5378 5379def int_hexagon_V6_vsubbq_128B : 5380Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubbq_128B">; 5381 5382def int_hexagon_V6_vsubh : 5383Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubh">; 5384 5385def int_hexagon_V6_vsubh_128B : 5386Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubh_128B">; 5387 5388def int_hexagon_V6_vsubh_dv : 5389Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubh_dv">; 5390 5391def int_hexagon_V6_vsubh_dv_128B : 5392Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubh_dv_128B">; 5393 5394def int_hexagon_V6_vsubhnq : 5395Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubhnq">; 5396 5397def int_hexagon_V6_vsubhnq_128B : 5398Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhnq_128B">; 5399 5400def int_hexagon_V6_vsubhq : 5401Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubhq">; 5402 5403def int_hexagon_V6_vsubhq_128B : 5404Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhq_128B">; 5405 5406def int_hexagon_V6_vsubhsat : 5407Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubhsat">; 5408 5409def int_hexagon_V6_vsubhsat_128B : 5410Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhsat_128B">; 5411 5412def int_hexagon_V6_vsubhsat_dv : 5413Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhsat_dv">; 5414 5415def int_hexagon_V6_vsubhsat_dv_128B : 5416Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubhsat_dv_128B">; 5417 5418def int_hexagon_V6_vsubhw : 5419Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubhw">; 5420 5421def int_hexagon_V6_vsubhw_128B : 5422Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhw_128B">; 5423 5424def int_hexagon_V6_vsububh : 5425Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsububh">; 5426 5427def int_hexagon_V6_vsububh_128B : 5428Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsububh_128B">; 5429 5430def int_hexagon_V6_vsububsat : 5431Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsububsat">; 5432 5433def int_hexagon_V6_vsububsat_128B : 5434Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsububsat_128B">; 5435 5436def int_hexagon_V6_vsububsat_dv : 5437Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsububsat_dv">; 5438 5439def int_hexagon_V6_vsububsat_dv_128B : 5440Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsububsat_dv_128B">; 5441 5442def int_hexagon_V6_vsubuhsat : 5443Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubuhsat">; 5444 5445def int_hexagon_V6_vsubuhsat_128B : 5446Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuhsat_128B">; 5447 5448def int_hexagon_V6_vsubuhsat_dv : 5449Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuhsat_dv">; 5450 5451def int_hexagon_V6_vsubuhsat_dv_128B : 5452Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubuhsat_dv_128B">; 5453 5454def int_hexagon_V6_vsubuhw : 5455Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubuhw">; 5456 5457def int_hexagon_V6_vsubuhw_128B : 5458Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuhw_128B">; 5459 5460def int_hexagon_V6_vsubw : 5461Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubw">; 5462 5463def int_hexagon_V6_vsubw_128B : 5464Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubw_128B">; 5465 5466def int_hexagon_V6_vsubw_dv : 5467Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubw_dv">; 5468 5469def int_hexagon_V6_vsubw_dv_128B : 5470Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubw_dv_128B">; 5471 5472def int_hexagon_V6_vsubwnq : 5473Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubwnq">; 5474 5475def int_hexagon_V6_vsubwnq_128B : 5476Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubwnq_128B">; 5477 5478def int_hexagon_V6_vsubwq : 5479Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubwq">; 5480 5481def int_hexagon_V6_vsubwq_128B : 5482Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubwq_128B">; 5483 5484def int_hexagon_V6_vsubwsat : 5485Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubwsat">; 5486 5487def int_hexagon_V6_vsubwsat_128B : 5488Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubwsat_128B">; 5489 5490def int_hexagon_V6_vsubwsat_dv : 5491Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubwsat_dv">; 5492 5493def int_hexagon_V6_vsubwsat_dv_128B : 5494Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubwsat_dv_128B">; 5495 5496def int_hexagon_V6_vswap : 5497Hexagon_v32i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vswap">; 5498 5499def int_hexagon_V6_vswap_128B : 5500Hexagon_v64i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vswap_128B">; 5501 5502def int_hexagon_V6_vtmpyb : 5503Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyb">; 5504 5505def int_hexagon_V6_vtmpyb_128B : 5506Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyb_128B">; 5507 5508def int_hexagon_V6_vtmpyb_acc : 5509Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyb_acc">; 5510 5511def int_hexagon_V6_vtmpyb_acc_128B : 5512Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyb_acc_128B">; 5513 5514def int_hexagon_V6_vtmpybus : 5515Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vtmpybus">; 5516 5517def int_hexagon_V6_vtmpybus_128B : 5518Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vtmpybus_128B">; 5519 5520def int_hexagon_V6_vtmpybus_acc : 5521Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vtmpybus_acc">; 5522 5523def int_hexagon_V6_vtmpybus_acc_128B : 5524Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vtmpybus_acc_128B">; 5525 5526def int_hexagon_V6_vtmpyhb : 5527Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb">; 5528 5529def int_hexagon_V6_vtmpyhb_128B : 5530Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb_128B">; 5531 5532def int_hexagon_V6_vtmpyhb_acc : 5533Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb_acc">; 5534 5535def int_hexagon_V6_vtmpyhb_acc_128B : 5536Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb_acc_128B">; 5537 5538def int_hexagon_V6_vunpackb : 5539Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackb">; 5540 5541def int_hexagon_V6_vunpackb_128B : 5542Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackb_128B">; 5543 5544def int_hexagon_V6_vunpackh : 5545Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackh">; 5546 5547def int_hexagon_V6_vunpackh_128B : 5548Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackh_128B">; 5549 5550def int_hexagon_V6_vunpackob : 5551Hexagon_v32i32_v32i32v16i32_Intrinsic<"HEXAGON_V6_vunpackob">; 5552 5553def int_hexagon_V6_vunpackob_128B : 5554Hexagon_v64i32_v64i32v32i32_Intrinsic<"HEXAGON_V6_vunpackob_128B">; 5555 5556def int_hexagon_V6_vunpackoh : 5557Hexagon_v32i32_v32i32v16i32_Intrinsic<"HEXAGON_V6_vunpackoh">; 5558 5559def int_hexagon_V6_vunpackoh_128B : 5560Hexagon_v64i32_v64i32v32i32_Intrinsic<"HEXAGON_V6_vunpackoh_128B">; 5561 5562def int_hexagon_V6_vunpackub : 5563Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackub">; 5564 5565def int_hexagon_V6_vunpackub_128B : 5566Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackub_128B">; 5567 5568def int_hexagon_V6_vunpackuh : 5569Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackuh">; 5570 5571def int_hexagon_V6_vunpackuh_128B : 5572Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackuh_128B">; 5573 5574def int_hexagon_V6_vxor : 5575Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vxor">; 5576 5577def int_hexagon_V6_vxor_128B : 5578Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vxor_128B">; 5579 5580def int_hexagon_V6_vzb : 5581Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vzb">; 5582 5583def int_hexagon_V6_vzb_128B : 5584Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vzb_128B">; 5585 5586def int_hexagon_V6_vzh : 5587Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vzh">; 5588 5589def int_hexagon_V6_vzh_128B : 5590Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vzh_128B">; 5591 5592// V62 HVX Instructions. 5593 5594def int_hexagon_V6_lvsplatb : 5595Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_lvsplatb">; 5596 5597def int_hexagon_V6_lvsplatb_128B : 5598Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_lvsplatb_128B">; 5599 5600def int_hexagon_V6_lvsplath : 5601Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_lvsplath">; 5602 5603def int_hexagon_V6_lvsplath_128B : 5604Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_lvsplath_128B">; 5605 5606def int_hexagon_V6_pred_scalar2v2 : 5607Hexagon_v64i1_i32_Intrinsic<"HEXAGON_V6_pred_scalar2v2">; 5608 5609def int_hexagon_V6_pred_scalar2v2_128B : 5610Hexagon_v128i1_i32_Intrinsic<"HEXAGON_V6_pred_scalar2v2_128B">; 5611 5612def int_hexagon_V6_shuffeqh : 5613Hexagon_v64i1_v64i1v64i1_Intrinsic<"HEXAGON_V6_shuffeqh">; 5614 5615def int_hexagon_V6_shuffeqh_128B : 5616Hexagon_v128i1_v128i1v128i1_Intrinsic<"HEXAGON_V6_shuffeqh_128B">; 5617 5618def int_hexagon_V6_shuffeqw : 5619Hexagon_v64i1_v64i1v64i1_Intrinsic<"HEXAGON_V6_shuffeqw">; 5620 5621def int_hexagon_V6_shuffeqw_128B : 5622Hexagon_v128i1_v128i1v128i1_Intrinsic<"HEXAGON_V6_shuffeqw_128B">; 5623 5624def int_hexagon_V6_vaddbsat : 5625Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddbsat">; 5626 5627def int_hexagon_V6_vaddbsat_128B : 5628Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddbsat_128B">; 5629 5630def int_hexagon_V6_vaddbsat_dv : 5631Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddbsat_dv">; 5632 5633def int_hexagon_V6_vaddbsat_dv_128B : 5634Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddbsat_dv_128B">; 5635 5636def int_hexagon_V6_vaddcarry : 5637Hexagon_custom_v16i32v64i1_v16i32v16i32v64i1_Intrinsic; 5638 5639def int_hexagon_V6_vaddcarry_128B : 5640Hexagon_custom_v32i32v128i1_v32i32v32i32v128i1_Intrinsic_128B; 5641 5642def int_hexagon_V6_vaddclbh : 5643Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddclbh">; 5644 5645def int_hexagon_V6_vaddclbh_128B : 5646Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddclbh_128B">; 5647 5648def int_hexagon_V6_vaddclbw : 5649Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddclbw">; 5650 5651def int_hexagon_V6_vaddclbw_128B : 5652Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddclbw_128B">; 5653 5654def int_hexagon_V6_vaddhw_acc : 5655Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhw_acc">; 5656 5657def int_hexagon_V6_vaddhw_acc_128B : 5658Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhw_acc_128B">; 5659 5660def int_hexagon_V6_vaddubh_acc : 5661Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddubh_acc">; 5662 5663def int_hexagon_V6_vaddubh_acc_128B : 5664Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddubh_acc_128B">; 5665 5666def int_hexagon_V6_vaddububb_sat : 5667Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddububb_sat">; 5668 5669def int_hexagon_V6_vaddububb_sat_128B : 5670Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddububb_sat_128B">; 5671 5672def int_hexagon_V6_vadduhw_acc : 5673Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduhw_acc">; 5674 5675def int_hexagon_V6_vadduhw_acc_128B : 5676Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhw_acc_128B">; 5677 5678def int_hexagon_V6_vadduwsat : 5679Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduwsat">; 5680 5681def int_hexagon_V6_vadduwsat_128B : 5682Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduwsat_128B">; 5683 5684def int_hexagon_V6_vadduwsat_dv : 5685Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduwsat_dv">; 5686 5687def int_hexagon_V6_vadduwsat_dv_128B : 5688Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vadduwsat_dv_128B">; 5689 5690def int_hexagon_V6_vandnqrt : 5691Hexagon_v16i32_v64i1i32_Intrinsic<"HEXAGON_V6_vandnqrt">; 5692 5693def int_hexagon_V6_vandnqrt_128B : 5694Hexagon_v32i32_v128i1i32_Intrinsic<"HEXAGON_V6_vandnqrt_128B">; 5695 5696def int_hexagon_V6_vandnqrt_acc : 5697Hexagon_v16i32_v16i32v64i1i32_Intrinsic<"HEXAGON_V6_vandnqrt_acc">; 5698 5699def int_hexagon_V6_vandnqrt_acc_128B : 5700Hexagon_v32i32_v32i32v128i1i32_Intrinsic<"HEXAGON_V6_vandnqrt_acc_128B">; 5701 5702def int_hexagon_V6_vandvnqv : 5703Hexagon_v16i32_v64i1v16i32_Intrinsic<"HEXAGON_V6_vandvnqv">; 5704 5705def int_hexagon_V6_vandvnqv_128B : 5706Hexagon_v32i32_v128i1v32i32_Intrinsic<"HEXAGON_V6_vandvnqv_128B">; 5707 5708def int_hexagon_V6_vandvqv : 5709Hexagon_v16i32_v64i1v16i32_Intrinsic<"HEXAGON_V6_vandvqv">; 5710 5711def int_hexagon_V6_vandvqv_128B : 5712Hexagon_v32i32_v128i1v32i32_Intrinsic<"HEXAGON_V6_vandvqv_128B">; 5713 5714def int_hexagon_V6_vasrhbsat : 5715Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhbsat">; 5716 5717def int_hexagon_V6_vasrhbsat_128B : 5718Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhbsat_128B">; 5719 5720def int_hexagon_V6_vasruwuhrndsat : 5721Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruwuhrndsat">; 5722 5723def int_hexagon_V6_vasruwuhrndsat_128B : 5724Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruwuhrndsat_128B">; 5725 5726def int_hexagon_V6_vasrwuhrndsat : 5727Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwuhrndsat">; 5728 5729def int_hexagon_V6_vasrwuhrndsat_128B : 5730Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwuhrndsat_128B">; 5731 5732def int_hexagon_V6_vlsrb : 5733Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vlsrb">; 5734 5735def int_hexagon_V6_vlsrb_128B : 5736Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vlsrb_128B">; 5737 5738def int_hexagon_V6_vlutvvb_nm : 5739Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_nm">; 5740 5741def int_hexagon_V6_vlutvvb_nm_128B : 5742Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_nm_128B">; 5743 5744def int_hexagon_V6_vlutvvb_oracci : 5745Hexagon_v16i32_v16i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracci", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 5746 5747def int_hexagon_V6_vlutvvb_oracci_128B : 5748Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracci_128B", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 5749 5750def int_hexagon_V6_vlutvvbi : 5751Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvbi", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 5752 5753def int_hexagon_V6_vlutvvbi_128B : 5754Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvbi_128B", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 5755 5756def int_hexagon_V6_vlutvwh_nm : 5757Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_nm">; 5758 5759def int_hexagon_V6_vlutvwh_nm_128B : 5760Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_nm_128B">; 5761 5762def int_hexagon_V6_vlutvwh_oracci : 5763Hexagon_v32i32_v32i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracci", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 5764 5765def int_hexagon_V6_vlutvwh_oracci_128B : 5766Hexagon_v64i32_v64i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracci_128B", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 5767 5768def int_hexagon_V6_vlutvwhi : 5769Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwhi", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 5770 5771def int_hexagon_V6_vlutvwhi_128B : 5772Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwhi_128B", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 5773 5774def int_hexagon_V6_vmaxb : 5775Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxb">; 5776 5777def int_hexagon_V6_vmaxb_128B : 5778Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxb_128B">; 5779 5780def int_hexagon_V6_vminb : 5781Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminb">; 5782 5783def int_hexagon_V6_vminb_128B : 5784Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminb_128B">; 5785 5786def int_hexagon_V6_vmpauhb : 5787Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpauhb">; 5788 5789def int_hexagon_V6_vmpauhb_128B : 5790Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vmpauhb_128B">; 5791 5792def int_hexagon_V6_vmpauhb_acc : 5793Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpauhb_acc">; 5794 5795def int_hexagon_V6_vmpauhb_acc_128B : 5796Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vmpauhb_acc_128B">; 5797 5798def int_hexagon_V6_vmpyewuh_64 : 5799Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyewuh_64">; 5800 5801def int_hexagon_V6_vmpyewuh_64_128B : 5802Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyewuh_64_128B">; 5803 5804def int_hexagon_V6_vmpyiwub : 5805Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub">; 5806 5807def int_hexagon_V6_vmpyiwub_128B : 5808Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub_128B">; 5809 5810def int_hexagon_V6_vmpyiwub_acc : 5811Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub_acc">; 5812 5813def int_hexagon_V6_vmpyiwub_acc_128B : 5814Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub_acc_128B">; 5815 5816def int_hexagon_V6_vmpyowh_64_acc : 5817Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_64_acc">; 5818 5819def int_hexagon_V6_vmpyowh_64_acc_128B : 5820Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_64_acc_128B">; 5821 5822def int_hexagon_V6_vrounduhub : 5823Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrounduhub">; 5824 5825def int_hexagon_V6_vrounduhub_128B : 5826Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrounduhub_128B">; 5827 5828def int_hexagon_V6_vrounduwuh : 5829Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrounduwuh">; 5830 5831def int_hexagon_V6_vrounduwuh_128B : 5832Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrounduwuh_128B">; 5833 5834def int_hexagon_V6_vsatuwuh : 5835Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsatuwuh">; 5836 5837def int_hexagon_V6_vsatuwuh_128B : 5838Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsatuwuh_128B">; 5839 5840def int_hexagon_V6_vsubbsat : 5841Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubbsat">; 5842 5843def int_hexagon_V6_vsubbsat_128B : 5844Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubbsat_128B">; 5845 5846def int_hexagon_V6_vsubbsat_dv : 5847Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubbsat_dv">; 5848 5849def int_hexagon_V6_vsubbsat_dv_128B : 5850Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubbsat_dv_128B">; 5851 5852def int_hexagon_V6_vsubcarry : 5853Hexagon_custom_v16i32v64i1_v16i32v16i32v64i1_Intrinsic; 5854 5855def int_hexagon_V6_vsubcarry_128B : 5856Hexagon_custom_v32i32v128i1_v32i32v32i32v128i1_Intrinsic_128B; 5857 5858def int_hexagon_V6_vsubububb_sat : 5859Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubububb_sat">; 5860 5861def int_hexagon_V6_vsubububb_sat_128B : 5862Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubububb_sat_128B">; 5863 5864def int_hexagon_V6_vsubuwsat : 5865Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubuwsat">; 5866 5867def int_hexagon_V6_vsubuwsat_128B : 5868Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuwsat_128B">; 5869 5870def int_hexagon_V6_vsubuwsat_dv : 5871Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuwsat_dv">; 5872 5873def int_hexagon_V6_vsubuwsat_dv_128B : 5874Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubuwsat_dv_128B">; 5875 5876// V65 HVX Instructions. 5877 5878def int_hexagon_V6_vabsb : 5879Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsb">; 5880 5881def int_hexagon_V6_vabsb_128B : 5882Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsb_128B">; 5883 5884def int_hexagon_V6_vabsb_sat : 5885Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsb_sat">; 5886 5887def int_hexagon_V6_vabsb_sat_128B : 5888Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsb_sat_128B">; 5889 5890def int_hexagon_V6_vaslh_acc : 5891Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vaslh_acc">; 5892 5893def int_hexagon_V6_vaslh_acc_128B : 5894Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vaslh_acc_128B">; 5895 5896def int_hexagon_V6_vasrh_acc : 5897Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrh_acc">; 5898 5899def int_hexagon_V6_vasrh_acc_128B : 5900Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrh_acc_128B">; 5901 5902def int_hexagon_V6_vasruhubrndsat : 5903Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruhubrndsat">; 5904 5905def int_hexagon_V6_vasruhubrndsat_128B : 5906Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruhubrndsat_128B">; 5907 5908def int_hexagon_V6_vasruhubsat : 5909Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruhubsat">; 5910 5911def int_hexagon_V6_vasruhubsat_128B : 5912Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruhubsat_128B">; 5913 5914def int_hexagon_V6_vasruwuhsat : 5915Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruwuhsat">; 5916 5917def int_hexagon_V6_vasruwuhsat_128B : 5918Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruwuhsat_128B">; 5919 5920def int_hexagon_V6_vavgb : 5921Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgb">; 5922 5923def int_hexagon_V6_vavgb_128B : 5924Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgb_128B">; 5925 5926def int_hexagon_V6_vavgbrnd : 5927Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgbrnd">; 5928 5929def int_hexagon_V6_vavgbrnd_128B : 5930Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgbrnd_128B">; 5931 5932def int_hexagon_V6_vavguw : 5933Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguw">; 5934 5935def int_hexagon_V6_vavguw_128B : 5936Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguw_128B">; 5937 5938def int_hexagon_V6_vavguwrnd : 5939Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguwrnd">; 5940 5941def int_hexagon_V6_vavguwrnd_128B : 5942Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguwrnd_128B">; 5943 5944def int_hexagon_V6_vdd0 : 5945Hexagon_v32i32__Intrinsic<"HEXAGON_V6_vdd0">; 5946 5947def int_hexagon_V6_vdd0_128B : 5948Hexagon_v64i32__Intrinsic<"HEXAGON_V6_vdd0_128B">; 5949 5950def int_hexagon_V6_vgathermh : 5951Hexagon__ptri32i32v16i32_Intrinsic<"HEXAGON_V6_vgathermh", [IntrArgMemOnly]>; 5952 5953def int_hexagon_V6_vgathermh_128B : 5954Hexagon__ptri32i32v32i32_Intrinsic<"HEXAGON_V6_vgathermh_128B", [IntrArgMemOnly]>; 5955 5956def int_hexagon_V6_vgathermhq : 5957Hexagon__ptrv64i1i32i32v16i32_Intrinsic<"HEXAGON_V6_vgathermhq", [IntrArgMemOnly]>; 5958 5959def int_hexagon_V6_vgathermhq_128B : 5960Hexagon__ptrv128i1i32i32v32i32_Intrinsic<"HEXAGON_V6_vgathermhq_128B", [IntrArgMemOnly]>; 5961 5962def int_hexagon_V6_vgathermhw : 5963Hexagon__ptri32i32v32i32_Intrinsic<"HEXAGON_V6_vgathermhw", [IntrArgMemOnly]>; 5964 5965def int_hexagon_V6_vgathermhw_128B : 5966Hexagon__ptri32i32v64i32_Intrinsic<"HEXAGON_V6_vgathermhw_128B", [IntrArgMemOnly]>; 5967 5968def int_hexagon_V6_vgathermhwq : 5969Hexagon__ptrv64i1i32i32v32i32_Intrinsic<"HEXAGON_V6_vgathermhwq", [IntrArgMemOnly]>; 5970 5971def int_hexagon_V6_vgathermhwq_128B : 5972Hexagon__ptrv128i1i32i32v64i32_Intrinsic<"HEXAGON_V6_vgathermhwq_128B", [IntrArgMemOnly]>; 5973 5974def int_hexagon_V6_vgathermw : 5975Hexagon__ptri32i32v16i32_Intrinsic<"HEXAGON_V6_vgathermw", [IntrArgMemOnly]>; 5976 5977def int_hexagon_V6_vgathermw_128B : 5978Hexagon__ptri32i32v32i32_Intrinsic<"HEXAGON_V6_vgathermw_128B", [IntrArgMemOnly]>; 5979 5980def int_hexagon_V6_vgathermwq : 5981Hexagon__ptrv64i1i32i32v16i32_Intrinsic<"HEXAGON_V6_vgathermwq", [IntrArgMemOnly]>; 5982 5983def int_hexagon_V6_vgathermwq_128B : 5984Hexagon__ptrv128i1i32i32v32i32_Intrinsic<"HEXAGON_V6_vgathermwq_128B", [IntrArgMemOnly]>; 5985 5986def int_hexagon_V6_vlut4 : 5987Hexagon_v16i32_v16i32i64_Intrinsic<"HEXAGON_V6_vlut4">; 5988 5989def int_hexagon_V6_vlut4_128B : 5990Hexagon_v32i32_v32i32i64_Intrinsic<"HEXAGON_V6_vlut4_128B">; 5991 5992def int_hexagon_V6_vmpabuu : 5993Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpabuu">; 5994 5995def int_hexagon_V6_vmpabuu_128B : 5996Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vmpabuu_128B">; 5997 5998def int_hexagon_V6_vmpabuu_acc : 5999Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpabuu_acc">; 6000 6001def int_hexagon_V6_vmpabuu_acc_128B : 6002Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vmpabuu_acc_128B">; 6003 6004def int_hexagon_V6_vmpahhsat : 6005Hexagon_v16i32_v16i32v16i32i64_Intrinsic<"HEXAGON_V6_vmpahhsat">; 6006 6007def int_hexagon_V6_vmpahhsat_128B : 6008Hexagon_v32i32_v32i32v32i32i64_Intrinsic<"HEXAGON_V6_vmpahhsat_128B">; 6009 6010def int_hexagon_V6_vmpauhuhsat : 6011Hexagon_v16i32_v16i32v16i32i64_Intrinsic<"HEXAGON_V6_vmpauhuhsat">; 6012 6013def int_hexagon_V6_vmpauhuhsat_128B : 6014Hexagon_v32i32_v32i32v32i32i64_Intrinsic<"HEXAGON_V6_vmpauhuhsat_128B">; 6015 6016def int_hexagon_V6_vmpsuhuhsat : 6017Hexagon_v16i32_v16i32v16i32i64_Intrinsic<"HEXAGON_V6_vmpsuhuhsat">; 6018 6019def int_hexagon_V6_vmpsuhuhsat_128B : 6020Hexagon_v32i32_v32i32v32i32i64_Intrinsic<"HEXAGON_V6_vmpsuhuhsat_128B">; 6021 6022def int_hexagon_V6_vmpyh_acc : 6023Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyh_acc">; 6024 6025def int_hexagon_V6_vmpyh_acc_128B : 6026Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyh_acc_128B">; 6027 6028def int_hexagon_V6_vmpyuhe : 6029Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyuhe">; 6030 6031def int_hexagon_V6_vmpyuhe_128B : 6032Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyuhe_128B">; 6033 6034def int_hexagon_V6_vmpyuhe_acc : 6035Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyuhe_acc">; 6036 6037def int_hexagon_V6_vmpyuhe_acc_128B : 6038Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyuhe_acc_128B">; 6039 6040def int_hexagon_V6_vnavgb : 6041Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgb">; 6042 6043def int_hexagon_V6_vnavgb_128B : 6044Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgb_128B">; 6045 6046def int_hexagon_V6_vprefixqb : 6047Hexagon_v16i32_v64i1_Intrinsic<"HEXAGON_V6_vprefixqb">; 6048 6049def int_hexagon_V6_vprefixqb_128B : 6050Hexagon_v32i32_v128i1_Intrinsic<"HEXAGON_V6_vprefixqb_128B">; 6051 6052def int_hexagon_V6_vprefixqh : 6053Hexagon_v16i32_v64i1_Intrinsic<"HEXAGON_V6_vprefixqh">; 6054 6055def int_hexagon_V6_vprefixqh_128B : 6056Hexagon_v32i32_v128i1_Intrinsic<"HEXAGON_V6_vprefixqh_128B">; 6057 6058def int_hexagon_V6_vprefixqw : 6059Hexagon_v16i32_v64i1_Intrinsic<"HEXAGON_V6_vprefixqw">; 6060 6061def int_hexagon_V6_vprefixqw_128B : 6062Hexagon_v32i32_v128i1_Intrinsic<"HEXAGON_V6_vprefixqw_128B">; 6063 6064def int_hexagon_V6_vscattermh : 6065Hexagon__i32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vscattermh", [IntrWriteMem]>; 6066 6067def int_hexagon_V6_vscattermh_128B : 6068Hexagon__i32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vscattermh_128B", [IntrWriteMem]>; 6069 6070def int_hexagon_V6_vscattermh_add : 6071Hexagon__i32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vscattermh_add", [IntrWriteMem]>; 6072 6073def int_hexagon_V6_vscattermh_add_128B : 6074Hexagon__i32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vscattermh_add_128B", [IntrWriteMem]>; 6075 6076def int_hexagon_V6_vscattermhq : 6077Hexagon__v64i1i32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vscattermhq", [IntrWriteMem]>; 6078 6079def int_hexagon_V6_vscattermhq_128B : 6080Hexagon__v128i1i32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vscattermhq_128B", [IntrWriteMem]>; 6081 6082def int_hexagon_V6_vscattermhw : 6083Hexagon__i32i32v32i32v16i32_Intrinsic<"HEXAGON_V6_vscattermhw", [IntrWriteMem]>; 6084 6085def int_hexagon_V6_vscattermhw_128B : 6086Hexagon__i32i32v64i32v32i32_Intrinsic<"HEXAGON_V6_vscattermhw_128B", [IntrWriteMem]>; 6087 6088def int_hexagon_V6_vscattermhw_add : 6089Hexagon__i32i32v32i32v16i32_Intrinsic<"HEXAGON_V6_vscattermhw_add", [IntrWriteMem]>; 6090 6091def int_hexagon_V6_vscattermhw_add_128B : 6092Hexagon__i32i32v64i32v32i32_Intrinsic<"HEXAGON_V6_vscattermhw_add_128B", [IntrWriteMem]>; 6093 6094def int_hexagon_V6_vscattermhwq : 6095Hexagon__v64i1i32i32v32i32v16i32_Intrinsic<"HEXAGON_V6_vscattermhwq", [IntrWriteMem]>; 6096 6097def int_hexagon_V6_vscattermhwq_128B : 6098Hexagon__v128i1i32i32v64i32v32i32_Intrinsic<"HEXAGON_V6_vscattermhwq_128B", [IntrWriteMem]>; 6099 6100def int_hexagon_V6_vscattermw : 6101Hexagon__i32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vscattermw", [IntrWriteMem]>; 6102 6103def int_hexagon_V6_vscattermw_128B : 6104Hexagon__i32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vscattermw_128B", [IntrWriteMem]>; 6105 6106def int_hexagon_V6_vscattermw_add : 6107Hexagon__i32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vscattermw_add", [IntrWriteMem]>; 6108 6109def int_hexagon_V6_vscattermw_add_128B : 6110Hexagon__i32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vscattermw_add_128B", [IntrWriteMem]>; 6111 6112def int_hexagon_V6_vscattermwq : 6113Hexagon__v64i1i32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vscattermwq", [IntrWriteMem]>; 6114 6115def int_hexagon_V6_vscattermwq_128B : 6116Hexagon__v128i1i32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vscattermwq_128B", [IntrWriteMem]>; 6117 6118// V66 HVX Instructions. 6119 6120def int_hexagon_V6_vaddcarryo : 6121Hexagon_custom_v16i32v64i1_v16i32v16i32_Intrinsic; 6122 6123def int_hexagon_V6_vaddcarryo_128B : 6124Hexagon_custom_v32i32v128i1_v32i32v32i32_Intrinsic_128B; 6125 6126def int_hexagon_V6_vaddcarrysat : 6127Hexagon_v16i32_v16i32v16i32v64i1_Intrinsic<"HEXAGON_V6_vaddcarrysat">; 6128 6129def int_hexagon_V6_vaddcarrysat_128B : 6130Hexagon_v32i32_v32i32v32i32v128i1_Intrinsic<"HEXAGON_V6_vaddcarrysat_128B">; 6131 6132def int_hexagon_V6_vasr_into : 6133Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vasr_into">; 6134 6135def int_hexagon_V6_vasr_into_128B : 6136Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vasr_into_128B">; 6137 6138def int_hexagon_V6_vrotr : 6139Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrotr">; 6140 6141def int_hexagon_V6_vrotr_128B : 6142Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrotr_128B">; 6143 6144def int_hexagon_V6_vsatdw : 6145Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsatdw">; 6146 6147def int_hexagon_V6_vsatdw_128B : 6148Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsatdw_128B">; 6149 6150def int_hexagon_V6_vsubcarryo : 6151Hexagon_custom_v16i32v64i1_v16i32v16i32_Intrinsic; 6152 6153def int_hexagon_V6_vsubcarryo_128B : 6154Hexagon_custom_v32i32v128i1_v32i32v32i32_Intrinsic_128B; 6155 6156// V68 HVX Instructions. 6157 6158def int_hexagon_V6_v6mpyhubs10 : 6159Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_v6mpyhubs10", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 6160 6161def int_hexagon_V6_v6mpyhubs10_128B : 6162Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_v6mpyhubs10_128B", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 6163 6164def int_hexagon_V6_v6mpyhubs10_vxx : 6165Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_v6mpyhubs10_vxx", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 6166 6167def int_hexagon_V6_v6mpyhubs10_vxx_128B : 6168Hexagon_v64i32_v64i32v64i32v64i32i32_Intrinsic<"HEXAGON_V6_v6mpyhubs10_vxx_128B", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 6169 6170def int_hexagon_V6_v6mpyvubs10 : 6171Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_v6mpyvubs10", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 6172 6173def int_hexagon_V6_v6mpyvubs10_128B : 6174Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_v6mpyvubs10_128B", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 6175 6176def int_hexagon_V6_v6mpyvubs10_vxx : 6177Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_v6mpyvubs10_vxx", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 6178 6179def int_hexagon_V6_v6mpyvubs10_vxx_128B : 6180Hexagon_v64i32_v64i32v64i32v64i32i32_Intrinsic<"HEXAGON_V6_v6mpyvubs10_vxx_128B", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 6181 6182def int_hexagon_V6_vabs_hf : 6183Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabs_hf">; 6184 6185def int_hexagon_V6_vabs_hf_128B : 6186Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabs_hf_128B">; 6187 6188def int_hexagon_V6_vabs_sf : 6189Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabs_sf">; 6190 6191def int_hexagon_V6_vabs_sf_128B : 6192Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabs_sf_128B">; 6193 6194def int_hexagon_V6_vadd_hf : 6195Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadd_hf">; 6196 6197def int_hexagon_V6_vadd_hf_128B : 6198Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadd_hf_128B">; 6199 6200def int_hexagon_V6_vadd_hf_hf : 6201Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadd_hf_hf">; 6202 6203def int_hexagon_V6_vadd_hf_hf_128B : 6204Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadd_hf_hf_128B">; 6205 6206def int_hexagon_V6_vadd_qf16 : 6207Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadd_qf16">; 6208 6209def int_hexagon_V6_vadd_qf16_128B : 6210Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadd_qf16_128B">; 6211 6212def int_hexagon_V6_vadd_qf16_mix : 6213Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadd_qf16_mix">; 6214 6215def int_hexagon_V6_vadd_qf16_mix_128B : 6216Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadd_qf16_mix_128B">; 6217 6218def int_hexagon_V6_vadd_qf32 : 6219Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadd_qf32">; 6220 6221def int_hexagon_V6_vadd_qf32_128B : 6222Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadd_qf32_128B">; 6223 6224def int_hexagon_V6_vadd_qf32_mix : 6225Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadd_qf32_mix">; 6226 6227def int_hexagon_V6_vadd_qf32_mix_128B : 6228Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadd_qf32_mix_128B">; 6229 6230def int_hexagon_V6_vadd_sf : 6231Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadd_sf">; 6232 6233def int_hexagon_V6_vadd_sf_128B : 6234Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadd_sf_128B">; 6235 6236def int_hexagon_V6_vadd_sf_hf : 6237Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadd_sf_hf">; 6238 6239def int_hexagon_V6_vadd_sf_hf_128B : 6240Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadd_sf_hf_128B">; 6241 6242def int_hexagon_V6_vadd_sf_sf : 6243Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadd_sf_sf">; 6244 6245def int_hexagon_V6_vadd_sf_sf_128B : 6246Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadd_sf_sf_128B">; 6247 6248def int_hexagon_V6_vassign_fp : 6249Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vassign_fp">; 6250 6251def int_hexagon_V6_vassign_fp_128B : 6252Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vassign_fp_128B">; 6253 6254def int_hexagon_V6_vconv_hf_qf16 : 6255Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vconv_hf_qf16">; 6256 6257def int_hexagon_V6_vconv_hf_qf16_128B : 6258Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vconv_hf_qf16_128B">; 6259 6260def int_hexagon_V6_vconv_hf_qf32 : 6261Hexagon_v16i32_v32i32_Intrinsic<"HEXAGON_V6_vconv_hf_qf32">; 6262 6263def int_hexagon_V6_vconv_hf_qf32_128B : 6264Hexagon_v32i32_v64i32_Intrinsic<"HEXAGON_V6_vconv_hf_qf32_128B">; 6265 6266def int_hexagon_V6_vconv_sf_qf32 : 6267Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vconv_sf_qf32">; 6268 6269def int_hexagon_V6_vconv_sf_qf32_128B : 6270Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vconv_sf_qf32_128B">; 6271 6272def int_hexagon_V6_vcvt_b_hf : 6273Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vcvt_b_hf">; 6274 6275def int_hexagon_V6_vcvt_b_hf_128B : 6276Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vcvt_b_hf_128B">; 6277 6278def int_hexagon_V6_vcvt_h_hf : 6279Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vcvt_h_hf">; 6280 6281def int_hexagon_V6_vcvt_h_hf_128B : 6282Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vcvt_h_hf_128B">; 6283 6284def int_hexagon_V6_vcvt_hf_b : 6285Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vcvt_hf_b">; 6286 6287def int_hexagon_V6_vcvt_hf_b_128B : 6288Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vcvt_hf_b_128B">; 6289 6290def int_hexagon_V6_vcvt_hf_h : 6291Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vcvt_hf_h">; 6292 6293def int_hexagon_V6_vcvt_hf_h_128B : 6294Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vcvt_hf_h_128B">; 6295 6296def int_hexagon_V6_vcvt_hf_sf : 6297Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vcvt_hf_sf">; 6298 6299def int_hexagon_V6_vcvt_hf_sf_128B : 6300Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vcvt_hf_sf_128B">; 6301 6302def int_hexagon_V6_vcvt_hf_ub : 6303Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vcvt_hf_ub">; 6304 6305def int_hexagon_V6_vcvt_hf_ub_128B : 6306Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vcvt_hf_ub_128B">; 6307 6308def int_hexagon_V6_vcvt_hf_uh : 6309Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vcvt_hf_uh">; 6310 6311def int_hexagon_V6_vcvt_hf_uh_128B : 6312Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vcvt_hf_uh_128B">; 6313 6314def int_hexagon_V6_vcvt_sf_hf : 6315Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vcvt_sf_hf">; 6316 6317def int_hexagon_V6_vcvt_sf_hf_128B : 6318Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vcvt_sf_hf_128B">; 6319 6320def int_hexagon_V6_vcvt_ub_hf : 6321Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vcvt_ub_hf">; 6322 6323def int_hexagon_V6_vcvt_ub_hf_128B : 6324Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vcvt_ub_hf_128B">; 6325 6326def int_hexagon_V6_vcvt_uh_hf : 6327Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vcvt_uh_hf">; 6328 6329def int_hexagon_V6_vcvt_uh_hf_128B : 6330Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vcvt_uh_hf_128B">; 6331 6332def int_hexagon_V6_vdmpy_sf_hf : 6333Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vdmpy_sf_hf">; 6334 6335def int_hexagon_V6_vdmpy_sf_hf_128B : 6336Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vdmpy_sf_hf_128B">; 6337 6338def int_hexagon_V6_vdmpy_sf_hf_acc : 6339Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vdmpy_sf_hf_acc">; 6340 6341def int_hexagon_V6_vdmpy_sf_hf_acc_128B : 6342Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vdmpy_sf_hf_acc_128B">; 6343 6344def int_hexagon_V6_vfmax_hf : 6345Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vfmax_hf">; 6346 6347def int_hexagon_V6_vfmax_hf_128B : 6348Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vfmax_hf_128B">; 6349 6350def int_hexagon_V6_vfmax_sf : 6351Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vfmax_sf">; 6352 6353def int_hexagon_V6_vfmax_sf_128B : 6354Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vfmax_sf_128B">; 6355 6356def int_hexagon_V6_vfmin_hf : 6357Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vfmin_hf">; 6358 6359def int_hexagon_V6_vfmin_hf_128B : 6360Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vfmin_hf_128B">; 6361 6362def int_hexagon_V6_vfmin_sf : 6363Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vfmin_sf">; 6364 6365def int_hexagon_V6_vfmin_sf_128B : 6366Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vfmin_sf_128B">; 6367 6368def int_hexagon_V6_vfneg_hf : 6369Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vfneg_hf">; 6370 6371def int_hexagon_V6_vfneg_hf_128B : 6372Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vfneg_hf_128B">; 6373 6374def int_hexagon_V6_vfneg_sf : 6375Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vfneg_sf">; 6376 6377def int_hexagon_V6_vfneg_sf_128B : 6378Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vfneg_sf_128B">; 6379 6380def int_hexagon_V6_vgthf : 6381Hexagon_v64i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgthf">; 6382 6383def int_hexagon_V6_vgthf_128B : 6384Hexagon_v128i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgthf_128B">; 6385 6386def int_hexagon_V6_vgthf_and : 6387Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgthf_and">; 6388 6389def int_hexagon_V6_vgthf_and_128B : 6390Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgthf_and_128B">; 6391 6392def int_hexagon_V6_vgthf_or : 6393Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgthf_or">; 6394 6395def int_hexagon_V6_vgthf_or_128B : 6396Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgthf_or_128B">; 6397 6398def int_hexagon_V6_vgthf_xor : 6399Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgthf_xor">; 6400 6401def int_hexagon_V6_vgthf_xor_128B : 6402Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgthf_xor_128B">; 6403 6404def int_hexagon_V6_vgtsf : 6405Hexagon_v64i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtsf">; 6406 6407def int_hexagon_V6_vgtsf_128B : 6408Hexagon_v128i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtsf_128B">; 6409 6410def int_hexagon_V6_vgtsf_and : 6411Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtsf_and">; 6412 6413def int_hexagon_V6_vgtsf_and_128B : 6414Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtsf_and_128B">; 6415 6416def int_hexagon_V6_vgtsf_or : 6417Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtsf_or">; 6418 6419def int_hexagon_V6_vgtsf_or_128B : 6420Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtsf_or_128B">; 6421 6422def int_hexagon_V6_vgtsf_xor : 6423Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtsf_xor">; 6424 6425def int_hexagon_V6_vgtsf_xor_128B : 6426Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtsf_xor_128B">; 6427 6428def int_hexagon_V6_vmax_hf : 6429Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmax_hf">; 6430 6431def int_hexagon_V6_vmax_hf_128B : 6432Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmax_hf_128B">; 6433 6434def int_hexagon_V6_vmax_sf : 6435Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmax_sf">; 6436 6437def int_hexagon_V6_vmax_sf_128B : 6438Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmax_sf_128B">; 6439 6440def int_hexagon_V6_vmin_hf : 6441Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmin_hf">; 6442 6443def int_hexagon_V6_vmin_hf_128B : 6444Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmin_hf_128B">; 6445 6446def int_hexagon_V6_vmin_sf : 6447Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmin_sf">; 6448 6449def int_hexagon_V6_vmin_sf_128B : 6450Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmin_sf_128B">; 6451 6452def int_hexagon_V6_vmpy_hf_hf : 6453Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpy_hf_hf">; 6454 6455def int_hexagon_V6_vmpy_hf_hf_128B : 6456Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpy_hf_hf_128B">; 6457 6458def int_hexagon_V6_vmpy_hf_hf_acc : 6459Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpy_hf_hf_acc">; 6460 6461def int_hexagon_V6_vmpy_hf_hf_acc_128B : 6462Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpy_hf_hf_acc_128B">; 6463 6464def int_hexagon_V6_vmpy_qf16 : 6465Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpy_qf16">; 6466 6467def int_hexagon_V6_vmpy_qf16_128B : 6468Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpy_qf16_128B">; 6469 6470def int_hexagon_V6_vmpy_qf16_hf : 6471Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpy_qf16_hf">; 6472 6473def int_hexagon_V6_vmpy_qf16_hf_128B : 6474Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpy_qf16_hf_128B">; 6475 6476def int_hexagon_V6_vmpy_qf16_mix_hf : 6477Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpy_qf16_mix_hf">; 6478 6479def int_hexagon_V6_vmpy_qf16_mix_hf_128B : 6480Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpy_qf16_mix_hf_128B">; 6481 6482def int_hexagon_V6_vmpy_qf32 : 6483Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpy_qf32">; 6484 6485def int_hexagon_V6_vmpy_qf32_128B : 6486Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpy_qf32_128B">; 6487 6488def int_hexagon_V6_vmpy_qf32_hf : 6489Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpy_qf32_hf">; 6490 6491def int_hexagon_V6_vmpy_qf32_hf_128B : 6492Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpy_qf32_hf_128B">; 6493 6494def int_hexagon_V6_vmpy_qf32_mix_hf : 6495Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpy_qf32_mix_hf">; 6496 6497def int_hexagon_V6_vmpy_qf32_mix_hf_128B : 6498Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpy_qf32_mix_hf_128B">; 6499 6500def int_hexagon_V6_vmpy_qf32_qf16 : 6501Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpy_qf32_qf16">; 6502 6503def int_hexagon_V6_vmpy_qf32_qf16_128B : 6504Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpy_qf32_qf16_128B">; 6505 6506def int_hexagon_V6_vmpy_qf32_sf : 6507Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpy_qf32_sf">; 6508 6509def int_hexagon_V6_vmpy_qf32_sf_128B : 6510Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpy_qf32_sf_128B">; 6511 6512def int_hexagon_V6_vmpy_sf_hf : 6513Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpy_sf_hf">; 6514 6515def int_hexagon_V6_vmpy_sf_hf_128B : 6516Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpy_sf_hf_128B">; 6517 6518def int_hexagon_V6_vmpy_sf_hf_acc : 6519Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpy_sf_hf_acc">; 6520 6521def int_hexagon_V6_vmpy_sf_hf_acc_128B : 6522Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpy_sf_hf_acc_128B">; 6523 6524def int_hexagon_V6_vmpy_sf_sf : 6525Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpy_sf_sf">; 6526 6527def int_hexagon_V6_vmpy_sf_sf_128B : 6528Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpy_sf_sf_128B">; 6529 6530def int_hexagon_V6_vsub_hf : 6531Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsub_hf">; 6532 6533def int_hexagon_V6_vsub_hf_128B : 6534Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsub_hf_128B">; 6535 6536def int_hexagon_V6_vsub_hf_hf : 6537Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsub_hf_hf">; 6538 6539def int_hexagon_V6_vsub_hf_hf_128B : 6540Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsub_hf_hf_128B">; 6541 6542def int_hexagon_V6_vsub_qf16 : 6543Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsub_qf16">; 6544 6545def int_hexagon_V6_vsub_qf16_128B : 6546Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsub_qf16_128B">; 6547 6548def int_hexagon_V6_vsub_qf16_mix : 6549Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsub_qf16_mix">; 6550 6551def int_hexagon_V6_vsub_qf16_mix_128B : 6552Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsub_qf16_mix_128B">; 6553 6554def int_hexagon_V6_vsub_qf32 : 6555Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsub_qf32">; 6556 6557def int_hexagon_V6_vsub_qf32_128B : 6558Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsub_qf32_128B">; 6559 6560def int_hexagon_V6_vsub_qf32_mix : 6561Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsub_qf32_mix">; 6562 6563def int_hexagon_V6_vsub_qf32_mix_128B : 6564Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsub_qf32_mix_128B">; 6565 6566def int_hexagon_V6_vsub_sf : 6567Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsub_sf">; 6568 6569def int_hexagon_V6_vsub_sf_128B : 6570Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsub_sf_128B">; 6571 6572def int_hexagon_V6_vsub_sf_hf : 6573Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsub_sf_hf">; 6574 6575def int_hexagon_V6_vsub_sf_hf_128B : 6576Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsub_sf_hf_128B">; 6577 6578def int_hexagon_V6_vsub_sf_sf : 6579Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsub_sf_sf">; 6580 6581def int_hexagon_V6_vsub_sf_sf_128B : 6582Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsub_sf_sf_128B">; 6583 6584// V69 HVX Instructions. 6585 6586def int_hexagon_V6_vasrvuhubrndsat : 6587Hexagon_v16i32_v32i32v16i32_Intrinsic<"HEXAGON_V6_vasrvuhubrndsat">; 6588 6589def int_hexagon_V6_vasrvuhubrndsat_128B : 6590Hexagon_v32i32_v64i32v32i32_Intrinsic<"HEXAGON_V6_vasrvuhubrndsat_128B">; 6591 6592def int_hexagon_V6_vasrvuhubsat : 6593Hexagon_v16i32_v32i32v16i32_Intrinsic<"HEXAGON_V6_vasrvuhubsat">; 6594 6595def int_hexagon_V6_vasrvuhubsat_128B : 6596Hexagon_v32i32_v64i32v32i32_Intrinsic<"HEXAGON_V6_vasrvuhubsat_128B">; 6597 6598def int_hexagon_V6_vasrvwuhrndsat : 6599Hexagon_v16i32_v32i32v16i32_Intrinsic<"HEXAGON_V6_vasrvwuhrndsat">; 6600 6601def int_hexagon_V6_vasrvwuhrndsat_128B : 6602Hexagon_v32i32_v64i32v32i32_Intrinsic<"HEXAGON_V6_vasrvwuhrndsat_128B">; 6603 6604def int_hexagon_V6_vasrvwuhsat : 6605Hexagon_v16i32_v32i32v16i32_Intrinsic<"HEXAGON_V6_vasrvwuhsat">; 6606 6607def int_hexagon_V6_vasrvwuhsat_128B : 6608Hexagon_v32i32_v64i32v32i32_Intrinsic<"HEXAGON_V6_vasrvwuhsat_128B">; 6609 6610def int_hexagon_V6_vmpyuhvs : 6611Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyuhvs">; 6612 6613def int_hexagon_V6_vmpyuhvs_128B : 6614Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyuhvs_128B">; 6615 6616// V73 HVX Instructions. 6617 6618def int_hexagon_V6_vadd_sf_bf : 6619Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadd_sf_bf">; 6620 6621def int_hexagon_V6_vadd_sf_bf_128B : 6622Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadd_sf_bf_128B">; 6623 6624def int_hexagon_V6_vconv_h_hf : 6625Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vconv_h_hf">; 6626 6627def int_hexagon_V6_vconv_h_hf_128B : 6628Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vconv_h_hf_128B">; 6629 6630def int_hexagon_V6_vconv_hf_h : 6631Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vconv_hf_h">; 6632 6633def int_hexagon_V6_vconv_hf_h_128B : 6634Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vconv_hf_h_128B">; 6635 6636def int_hexagon_V6_vconv_sf_w : 6637Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vconv_sf_w">; 6638 6639def int_hexagon_V6_vconv_sf_w_128B : 6640Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vconv_sf_w_128B">; 6641 6642def int_hexagon_V6_vconv_w_sf : 6643Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vconv_w_sf">; 6644 6645def int_hexagon_V6_vconv_w_sf_128B : 6646Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vconv_w_sf_128B">; 6647 6648def int_hexagon_V6_vcvt_bf_sf : 6649Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vcvt_bf_sf">; 6650 6651def int_hexagon_V6_vcvt_bf_sf_128B : 6652Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vcvt_bf_sf_128B">; 6653 6654def int_hexagon_V6_vgtbf : 6655Hexagon_v64i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtbf">; 6656 6657def int_hexagon_V6_vgtbf_128B : 6658Hexagon_v128i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtbf_128B">; 6659 6660def int_hexagon_V6_vgtbf_and : 6661Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtbf_and">; 6662 6663def int_hexagon_V6_vgtbf_and_128B : 6664Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtbf_and_128B">; 6665 6666def int_hexagon_V6_vgtbf_or : 6667Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtbf_or">; 6668 6669def int_hexagon_V6_vgtbf_or_128B : 6670Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtbf_or_128B">; 6671 6672def int_hexagon_V6_vgtbf_xor : 6673Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtbf_xor">; 6674 6675def int_hexagon_V6_vgtbf_xor_128B : 6676Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtbf_xor_128B">; 6677 6678def int_hexagon_V6_vmax_bf : 6679Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmax_bf">; 6680 6681def int_hexagon_V6_vmax_bf_128B : 6682Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmax_bf_128B">; 6683 6684def int_hexagon_V6_vmin_bf : 6685Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmin_bf">; 6686 6687def int_hexagon_V6_vmin_bf_128B : 6688Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmin_bf_128B">; 6689 6690def int_hexagon_V6_vmpy_sf_bf : 6691Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpy_sf_bf">; 6692 6693def int_hexagon_V6_vmpy_sf_bf_128B : 6694Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpy_sf_bf_128B">; 6695 6696def int_hexagon_V6_vmpy_sf_bf_acc : 6697Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpy_sf_bf_acc">; 6698 6699def int_hexagon_V6_vmpy_sf_bf_acc_128B : 6700Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpy_sf_bf_acc_128B">; 6701 6702def int_hexagon_V6_vsub_sf_bf : 6703Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsub_sf_bf">; 6704 6705def int_hexagon_V6_vsub_sf_bf_128B : 6706Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsub_sf_bf_128B">; 6707 6708