1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2006 Intel Corp. 4 * Tom Long Nguyen (tom.l.nguyen@intel.com) 5 * Zhang Yanmin (yanmin.zhang@intel.com) 6 */ 7 8 #ifndef _AER_H_ 9 #define _AER_H_ 10 11 #include <linux/errno.h> 12 #include <linux/types.h> 13 14 #define AER_NONFATAL 0 15 #define AER_FATAL 1 16 #define AER_CORRECTABLE 2 17 #define DPC_FATAL 3 18 19 struct pci_dev; 20 21 struct pcie_tlp_log { 22 u32 dw[4]; 23 }; 24 25 struct aer_capability_regs { 26 u32 header; 27 u32 uncor_status; 28 u32 uncor_mask; 29 u32 uncor_severity; 30 u32 cor_status; 31 u32 cor_mask; 32 u32 cap_control; 33 struct pcie_tlp_log header_log; 34 u32 root_command; 35 u32 root_status; 36 u16 cor_err_source; 37 u16 uncor_err_source; 38 }; 39 40 int pcie_read_tlp_log(struct pci_dev *dev, int where, struct pcie_tlp_log *log); 41 42 #if defined(CONFIG_PCIEAER) 43 int pci_aer_clear_nonfatal_status(struct pci_dev *dev); 44 int pcie_aer_is_native(struct pci_dev *dev); 45 #else pci_aer_clear_nonfatal_status(struct pci_dev * dev)46static inline int pci_aer_clear_nonfatal_status(struct pci_dev *dev) 47 { 48 return -EINVAL; 49 } pcie_aer_is_native(struct pci_dev * dev)50static inline int pcie_aer_is_native(struct pci_dev *dev) { return 0; } 51 #endif 52 53 void pci_print_aer(struct pci_dev *dev, int aer_severity, 54 struct aer_capability_regs *aer); 55 int cper_severity_to_aer(int cper_severity); 56 void aer_recover_queue(int domain, unsigned int bus, unsigned int devfn, 57 int severity, struct aer_capability_regs *aer_regs); 58 #endif //_AER_H_ 59 60