1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree Source for J722S SoC Family 4 * 5 * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/soc/ti,sci_pm_domain.h> 12 13#include "k3-pinctrl.h" 14 15/ { 16 model = "Texas Instruments K3 J722S SoC"; 17 compatible = "ti,j722s"; 18 interrupt-parent = <&gic500>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 cpus { 23 #address-cells = <1>; 24 #size-cells = <0>; 25 26 cpu-map { 27 cluster0: cluster0 { 28 core0 { 29 cpu = <&cpu0>; 30 }; 31 32 core1 { 33 cpu = <&cpu1>; 34 }; 35 36 core2 { 37 cpu = <&cpu2>; 38 }; 39 40 core3 { 41 cpu = <&cpu3>; 42 }; 43 }; 44 }; 45 46 cpu0: cpu@0 { 47 compatible = "arm,cortex-a53"; 48 reg = <0x000>; 49 device_type = "cpu"; 50 enable-method = "psci"; 51 i-cache-size = <0x8000>; 52 i-cache-line-size = <64>; 53 i-cache-sets = <256>; 54 d-cache-size = <0x8000>; 55 d-cache-line-size = <64>; 56 d-cache-sets = <128>; 57 next-level-cache = <&l2_0>; 58 clocks = <&k3_clks 135 0>; 59 #cooling-cells = <2>; 60 }; 61 62 cpu1: cpu@1 { 63 compatible = "arm,cortex-a53"; 64 reg = <0x001>; 65 device_type = "cpu"; 66 enable-method = "psci"; 67 i-cache-size = <0x8000>; 68 i-cache-line-size = <64>; 69 i-cache-sets = <256>; 70 d-cache-size = <0x8000>; 71 d-cache-line-size = <64>; 72 d-cache-sets = <128>; 73 next-level-cache = <&l2_0>; 74 clocks = <&k3_clks 136 0>; 75 #cooling-cells = <2>; 76 }; 77 78 cpu2: cpu@2 { 79 compatible = "arm,cortex-a53"; 80 reg = <0x002>; 81 device_type = "cpu"; 82 enable-method = "psci"; 83 i-cache-size = <0x8000>; 84 i-cache-line-size = <64>; 85 i-cache-sets = <256>; 86 d-cache-size = <0x8000>; 87 d-cache-line-size = <64>; 88 d-cache-sets = <128>; 89 next-level-cache = <&l2_0>; 90 clocks = <&k3_clks 137 0>; 91 #cooling-cells = <2>; 92 }; 93 94 cpu3: cpu@3 { 95 compatible = "arm,cortex-a53"; 96 reg = <0x003>; 97 device_type = "cpu"; 98 enable-method = "psci"; 99 i-cache-size = <0x8000>; 100 i-cache-line-size = <64>; 101 i-cache-sets = <256>; 102 d-cache-size = <0x8000>; 103 d-cache-line-size = <64>; 104 d-cache-sets = <128>; 105 next-level-cache = <&l2_0>; 106 clocks = <&k3_clks 138 0>; 107 #cooling-cells = <2>; 108 }; 109 }; 110 111 l2_0: l2-cache0 { 112 compatible = "cache"; 113 cache-unified; 114 cache-level = <2>; 115 cache-size = <0x80000>; 116 cache-line-size = <64>; 117 cache-sets = <512>; 118 }; 119 120 firmware { 121 optee { 122 compatible = "linaro,optee-tz"; 123 method = "smc"; 124 }; 125 126 psci: psci { 127 compatible = "arm,psci-1.0"; 128 method = "smc"; 129 }; 130 }; 131 132 a53_timer0: timer-cl0-cpu0 { 133 compatible = "arm,armv8-timer"; 134 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ 135 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ 136 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ 137 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ 138 }; 139 140 pmu: pmu { 141 compatible = "arm,cortex-a53-pmu"; 142 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 143 }; 144 145 cbass_main: bus@f0000 { 146 compatible = "simple-bus"; 147 #address-cells = <2>; 148 #size-cells = <2>; 149 150 ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */ 151 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */ 152 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ 153 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */ 154 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */ 155 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */ 156 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */ 157 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */ 158 <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_0 */ 159 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */ 160 <0x00 0x0fd80000 0x00 0x0fd80000 0x00 0x00080000>, /* GPU */ 161 <0x00 0x0fd20000 0x00 0x0fd20000 0x00 0x00000100>, /* JPEGENC0_CORE */ 162 <0x00 0x0fd20200 0x00 0x0fd20200 0x00 0x00000200>, /* JPEGENC0_CORE_MMU */ 163 <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */ 164 <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */ 165 <0x00 0x301C0000 0x00 0x301C0000 0x00 0x00001000>, /* DPHY-TX */ 166 <0x00 0x30101000 0x00 0x30101000 0x00 0x00080100>, /* CSI window */ 167 <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */ 168 <0x00 0x30210000 0x00 0x30210000 0x00 0x00010000>, /* VPU */ 169 <0x00 0x30220000 0x00 0x30220000 0x00 0x00010000>, /* DSS1 */ 170 <0x00 0x30270000 0x00 0x30270000 0x00 0x00010000>, /* DSI-base1 */ 171 <0x00 0x30500000 0x00 0x30500000 0x00 0x00100000>, /* DSI-base2 */ 172 <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */ 173 <0x00 0x31200000 0x00 0x31200000 0x00 0x00040000>, /* USB1 DWC3 Core window */ 174 <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */ 175 <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */ 176 <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ 177 <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */ 178 <0x00 0x48000000 0x00 0x48000000 0x00 0x06408000>, /* DMSS */ 179 <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */ 180 <0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe0 DAT0 */ 181 <0x00 0x70000000 0x00 0x70000000 0x00 0x00040000>, /* OCSRAM */ 182 <0x00 0x78400000 0x00 0x78400000 0x00 0x00008000>, /* MAIN R5FSS0 ATCM */ 183 <0x00 0x78500000 0x00 0x78500000 0x00 0x00008000>, /* MAIN R5FSS0 BTCM */ 184 <0x00 0x7e000000 0x00 0x7e000000 0x00 0x00200000>, /* C7X_0 L2SRAM */ 185 <0x00 0x7e200000 0x00 0x7e200000 0x00 0x00200000>, /* C7X_1 L2SRAM */ 186 <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */ 187 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */ 188 <0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe0 DAT1 */ 189 190 /* MCU Domain Range */ 191 <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, 192 <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, 193 <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, 194 <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, 195 <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>, 196 197 /* Wakeup Domain Range */ 198 <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, 199 <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, 200 <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, 201 <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, 202 <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; 203 204 cbass_mcu: bus@4000000 { 205 compatible = "simple-bus"; 206 #address-cells = <2>; 207 #size-cells = <2>; 208 ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, /* Peripheral window */ 209 <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */ 210 <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */ 211 <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU IRAM0 */ 212 <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>; /* MCU IRAM1 */ 213 bootph-all; 214 }; 215 216 cbass_wakeup: bus@b00000 { 217 compatible = "simple-bus"; 218 #address-cells = <2>; 219 #size-cells = <2>; 220 ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */ 221 <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */ 222 <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* WKUP CTRL MMR */ 223 <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/ 224 <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/ 225 bootph-all; 226 }; 227 }; 228 229 #include "k3-am62p-j722s-common-thermal.dtsi" 230}; 231 232/* Include peripherals shared with AM62P */ 233#include "k3-am62p-j722s-common-main.dtsi" 234#include "k3-am62p-j722s-common-mcu.dtsi" 235#include "k3-am62p-j722s-common-wakeup.dtsi" 236 237/* Include J722S specific peripherals */ 238#include "k3-j722s-main.dtsi" 239