xref: /linux/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi (revision ec71f661a572a770d7c861cd52a50cbbb0e1a8d1)
1// SPDX-License-Identifier: GPL-2.0-only OR MIT
2/*
3 * Device Tree Source for J7200 SoC Family Main Domain peripherals
4 *
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8/ {
9	serdes_refclk: serdes-refclk {
10		#clock-cells = <0>;
11		compatible = "fixed-clock";
12	};
13};
14
15&cbass_main {
16	msmc_ram: sram@70000000 {
17		compatible = "mmio-sram";
18		reg = <0x00 0x70000000 0x00 0x100000>;
19		#address-cells = <1>;
20		#size-cells = <1>;
21		ranges = <0x00 0x00 0x70000000 0x100000>;
22
23		atf-sram@0 {
24			reg = <0x00 0x20000>;
25		};
26	};
27
28	scm_conf: scm-conf@100000 {
29		compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
30		reg = <0x00 0x00100000 0x00 0x1c000>;
31		#address-cells = <1>;
32		#size-cells = <1>;
33		ranges = <0x00 0x00 0x00100000 0x1c000>;
34
35		pcie1_ctrl: pcie-ctrl@4074 {
36			compatible = "ti,j784s4-pcie-ctrl", "syscon";
37			reg = <0x4074 0x4>;
38		};
39
40		serdes_ln_ctrl: mux-controller@4080 {
41			compatible = "reg-mux";
42			reg = <0x4080 0x20>;
43			#mux-control-cells = <1>;
44			mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
45					<0x8 0x3>, <0xc 0x3>; /* SERDES0 lane2/3 select */
46		};
47
48		cpsw0_phy_gmii_sel: phy@4044 {
49			compatible = "ti,j7200-cpsw5g-phy-gmii-sel";
50			ti,qsgmii-main-ports = <1>;
51			reg = <0x4044 0x10>;
52			#phy-cells = <1>;
53		};
54
55		usb_serdes_mux: mux-controller@4000 {
56			compatible = "reg-mux";
57			reg = <0x4000 0x4>;
58			#mux-control-cells = <1>;
59			mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
60		};
61	};
62
63	gic500: interrupt-controller@1800000 {
64		compatible = "arm,gic-v3";
65		#address-cells = <2>;
66		#size-cells = <2>;
67		ranges;
68		#interrupt-cells = <3>;
69		interrupt-controller;
70		reg = <0x00 0x01800000 0x00 0x10000>,	/* GICD */
71		      <0x00 0x01900000 0x00 0x100000>,	/* GICR */
72		      <0x00 0x6f000000 0x00 0x2000>,	/* GICC */
73		      <0x00 0x6f010000 0x00 0x1000>,	/* GICH */
74		      <0x00 0x6f020000 0x00 0x2000>;	/* GICV */
75
76		/* vcpumntirq: virtual CPU interface maintenance interrupt */
77		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
78
79		gic_its: msi-controller@1820000 {
80			compatible = "arm,gic-v3-its";
81			reg = <0x00 0x01820000 0x00 0x10000>;
82			socionext,synquacer-pre-its = <0x1000000 0x400000>;
83			msi-controller;
84			#msi-cells = <1>;
85		};
86	};
87
88	main_gpio_intr: interrupt-controller@a00000 {
89		compatible = "ti,sci-intr";
90		reg = <0x00 0x00a00000 0x00 0x800>;
91		ti,intr-trigger-type = <1>;
92		interrupt-controller;
93		interrupt-parent = <&gic500>;
94		#interrupt-cells = <1>;
95		ti,sci = <&dmsc>;
96		ti,sci-dev-id = <131>;
97		ti,interrupt-ranges = <8 392 56>;
98	};
99
100	main_navss: bus@30000000 {
101		compatible = "simple-bus";
102		#address-cells = <2>;
103		#size-cells = <2>;
104		ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
105		ti,sci-dev-id = <199>;
106		dma-coherent;
107		dma-ranges;
108
109		main_navss_intr: interrupt-controller@310e0000 {
110			compatible = "ti,sci-intr";
111			reg = <0x00 0x310e0000 0x00 0x4000>;
112			ti,intr-trigger-type = <4>;
113			interrupt-controller;
114			interrupt-parent = <&gic500>;
115			#interrupt-cells = <1>;
116			ti,sci = <&dmsc>;
117			ti,sci-dev-id = <213>;
118			ti,interrupt-ranges = <0 64 64>,
119					      <64 448 64>,
120					      <128 672 64>;
121		};
122
123		main_udmass_inta: msi-controller@33d00000 {
124			compatible = "ti,sci-inta";
125			reg = <0x00 0x33d00000 0x00 0x100000>;
126			interrupt-controller;
127			#interrupt-cells = <0>;
128			interrupt-parent = <&main_navss_intr>;
129			msi-controller;
130			ti,sci = <&dmsc>;
131			ti,sci-dev-id = <209>;
132			ti,interrupt-ranges = <0 0 256>;
133		};
134
135		secure_proxy_main: mailbox@32c00000 {
136			compatible = "ti,am654-secure-proxy";
137			#mbox-cells = <1>;
138			reg-names = "target_data", "rt", "scfg";
139			reg = <0x00 0x32c00000 0x00 0x100000>,
140			      <0x00 0x32400000 0x00 0x100000>,
141			      <0x00 0x32800000 0x00 0x100000>;
142			interrupt-names = "rx_011";
143			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
144			bootph-all;
145		};
146
147		hwspinlock: spinlock@30e00000 {
148			compatible = "ti,am654-hwspinlock";
149			reg = <0x00 0x30e00000 0x00 0x1000>;
150			#hwlock-cells = <1>;
151		};
152
153		mailbox0_cluster0: mailbox@31f80000 {
154			compatible = "ti,am654-mailbox";
155			reg = <0x00 0x31f80000 0x00 0x200>;
156			#mbox-cells = <1>;
157			ti,mbox-num-users = <4>;
158			ti,mbox-num-fifos = <16>;
159			interrupt-parent = <&main_navss_intr>;
160			status = "disabled";
161		};
162
163		mailbox0_cluster1: mailbox@31f81000 {
164			compatible = "ti,am654-mailbox";
165			reg = <0x00 0x31f81000 0x00 0x200>;
166			#mbox-cells = <1>;
167			ti,mbox-num-users = <4>;
168			ti,mbox-num-fifos = <16>;
169			interrupt-parent = <&main_navss_intr>;
170			status = "disabled";
171		};
172
173		mailbox0_cluster2: mailbox@31f82000 {
174			compatible = "ti,am654-mailbox";
175			reg = <0x00 0x31f82000 0x00 0x200>;
176			#mbox-cells = <1>;
177			ti,mbox-num-users = <4>;
178			ti,mbox-num-fifos = <16>;
179			interrupt-parent = <&main_navss_intr>;
180			status = "disabled";
181		};
182
183		mailbox0_cluster3: mailbox@31f83000 {
184			compatible = "ti,am654-mailbox";
185			reg = <0x00 0x31f83000 0x00 0x200>;
186			#mbox-cells = <1>;
187			ti,mbox-num-users = <4>;
188			ti,mbox-num-fifos = <16>;
189			interrupt-parent = <&main_navss_intr>;
190			status = "disabled";
191		};
192
193		mailbox0_cluster4: mailbox@31f84000 {
194			compatible = "ti,am654-mailbox";
195			reg = <0x00 0x31f84000 0x00 0x200>;
196			#mbox-cells = <1>;
197			ti,mbox-num-users = <4>;
198			ti,mbox-num-fifos = <16>;
199			interrupt-parent = <&main_navss_intr>;
200			status = "disabled";
201		};
202
203		mailbox0_cluster5: mailbox@31f85000 {
204			compatible = "ti,am654-mailbox";
205			reg = <0x00 0x31f85000 0x00 0x200>;
206			#mbox-cells = <1>;
207			ti,mbox-num-users = <4>;
208			ti,mbox-num-fifos = <16>;
209			interrupt-parent = <&main_navss_intr>;
210			status = "disabled";
211		};
212
213		mailbox0_cluster6: mailbox@31f86000 {
214			compatible = "ti,am654-mailbox";
215			reg = <0x00 0x31f86000 0x00 0x200>;
216			#mbox-cells = <1>;
217			ti,mbox-num-users = <4>;
218			ti,mbox-num-fifos = <16>;
219			interrupt-parent = <&main_navss_intr>;
220			status = "disabled";
221		};
222
223		mailbox0_cluster7: mailbox@31f87000 {
224			compatible = "ti,am654-mailbox";
225			reg = <0x00 0x31f87000 0x00 0x200>;
226			#mbox-cells = <1>;
227			ti,mbox-num-users = <4>;
228			ti,mbox-num-fifos = <16>;
229			interrupt-parent = <&main_navss_intr>;
230			status = "disabled";
231		};
232
233		mailbox0_cluster8: mailbox@31f88000 {
234			compatible = "ti,am654-mailbox";
235			reg = <0x00 0x31f88000 0x00 0x200>;
236			#mbox-cells = <1>;
237			ti,mbox-num-users = <4>;
238			ti,mbox-num-fifos = <16>;
239			interrupt-parent = <&main_navss_intr>;
240			status = "disabled";
241		};
242
243		mailbox0_cluster9: mailbox@31f89000 {
244			compatible = "ti,am654-mailbox";
245			reg = <0x00 0x31f89000 0x00 0x200>;
246			#mbox-cells = <1>;
247			ti,mbox-num-users = <4>;
248			ti,mbox-num-fifos = <16>;
249			interrupt-parent = <&main_navss_intr>;
250			status = "disabled";
251		};
252
253		mailbox0_cluster10: mailbox@31f8a000 {
254			compatible = "ti,am654-mailbox";
255			reg = <0x00 0x31f8a000 0x00 0x200>;
256			#mbox-cells = <1>;
257			ti,mbox-num-users = <4>;
258			ti,mbox-num-fifos = <16>;
259			interrupt-parent = <&main_navss_intr>;
260			status = "disabled";
261		};
262
263		mailbox0_cluster11: mailbox@31f8b000 {
264			compatible = "ti,am654-mailbox";
265			reg = <0x00 0x31f8b000 0x00 0x200>;
266			#mbox-cells = <1>;
267			ti,mbox-num-users = <4>;
268			ti,mbox-num-fifos = <16>;
269			interrupt-parent = <&main_navss_intr>;
270			status = "disabled";
271		};
272
273		main_ringacc: ringacc@3c000000 {
274			compatible = "ti,am654-navss-ringacc";
275			reg = <0x00 0x3c000000 0x00 0x400000>,
276			      <0x00 0x38000000 0x00 0x400000>,
277			      <0x00 0x31120000 0x00 0x100>,
278			      <0x00 0x33000000 0x00 0x40000>,
279			      <0x00 0x31080000 0x00 0x40000>;
280			reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
281			ti,num-rings = <1024>;
282			ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
283			ti,sci = <&dmsc>;
284			ti,sci-dev-id = <211>;
285			msi-parent = <&main_udmass_inta>;
286		};
287
288		main_udmap: dma-controller@31150000 {
289			compatible = "ti,j721e-navss-main-udmap";
290			reg = <0x00 0x31150000 0x00 0x100>,
291			      <0x00 0x34000000 0x00 0x100000>,
292			      <0x00 0x35000000 0x00 0x100000>,
293			      <0x00 0x30b00000 0x00 0x4000>,
294			      <0x00 0x30c00000 0x00 0x4000>,
295			      <0x00 0x30d00000 0x00 0x4000>;
296			reg-names = "gcfg", "rchanrt", "tchanrt",
297				    "tchan", "rchan", "rflow";
298			msi-parent = <&main_udmass_inta>;
299			#dma-cells = <1>;
300
301			ti,sci = <&dmsc>;
302			ti,sci-dev-id = <212>;
303			ti,ringacc = <&main_ringacc>;
304
305			ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
306						<0x0f>, /* TX_HCHAN */
307						<0x10>; /* TX_UHCHAN */
308			ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
309						<0x0b>, /* RX_HCHAN */
310						<0x0c>; /* RX_UHCHAN */
311			ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
312		};
313
314		cpts@310d0000 {
315			compatible = "ti,j721e-cpts";
316			reg = <0x00 0x310d0000 0x00 0x400>;
317			reg-names = "cpts";
318			clocks = <&k3_clks 201 1>;
319			clock-names = "cpts";
320			interrupts-extended = <&main_navss_intr 391>;
321			interrupt-names = "cpts";
322			ti,cpts-periodic-outputs = <6>;
323			ti,cpts-ext-ts-inputs = <8>;
324		};
325	};
326
327	cpsw0: ethernet@c000000 {
328		compatible = "ti,j7200-cpswxg-nuss";
329		#address-cells = <2>;
330		#size-cells = <2>;
331		reg = <0x00 0xc000000 0x00 0x200000>;
332		reg-names = "cpsw_nuss";
333		ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>;
334		clocks = <&k3_clks 19 33>;
335		clock-names = "fck";
336		power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>;
337
338		dmas = <&main_udmap 0xca00>,
339		       <&main_udmap 0xca01>,
340		       <&main_udmap 0xca02>,
341		       <&main_udmap 0xca03>,
342		       <&main_udmap 0xca04>,
343		       <&main_udmap 0xca05>,
344		       <&main_udmap 0xca06>,
345		       <&main_udmap 0xca07>,
346		       <&main_udmap 0x4a00>;
347		dma-names = "tx0", "tx1", "tx2", "tx3",
348			    "tx4", "tx5", "tx6", "tx7",
349			    "rx";
350
351		status = "disabled";
352
353		ethernet-ports {
354			#address-cells = <1>;
355			#size-cells = <0>;
356			cpsw0_port1: port@1 {
357				reg = <1>;
358				ti,mac-only;
359				label = "port1";
360				status = "disabled";
361			};
362
363			cpsw0_port2: port@2 {
364				reg = <2>;
365				ti,mac-only;
366				label = "port2";
367				status = "disabled";
368			};
369
370			cpsw0_port3: port@3 {
371				reg = <3>;
372				ti,mac-only;
373				label = "port3";
374				status = "disabled";
375			};
376
377			cpsw0_port4: port@4 {
378				reg = <4>;
379				ti,mac-only;
380				label = "port4";
381				status = "disabled";
382			};
383		};
384
385		cpsw5g_mdio: mdio@f00 {
386			compatible = "ti,cpsw-mdio","ti,davinci_mdio";
387			reg = <0x00 0xf00 0x00 0x100>;
388			#address-cells = <1>;
389			#size-cells = <0>;
390			clocks = <&k3_clks 19 33>;
391			clock-names = "fck";
392			bus_freq = <1000000>;
393			status = "disabled";
394		};
395
396		cpts@3d000 {
397			compatible = "ti,j721e-cpts";
398			reg = <0x00 0x3d000 0x00 0x400>;
399			clocks = <&k3_clks 19 16>;
400			clock-names = "cpts";
401			interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
402			interrupt-names = "cpts";
403			ti,cpts-ext-ts-inputs = <4>;
404			ti,cpts-periodic-outputs = <2>;
405		};
406	};
407
408	/* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
409	main_timerio_input: pinctrl@104200 {
410		compatible = "ti,j7200-padconf", "pinctrl-single";
411		reg = <0x0 0x104200 0x0 0x50>;
412		#pinctrl-cells = <1>;
413		pinctrl-single,register-width = <32>;
414		pinctrl-single,function-mask = <0x000001ff>;
415	};
416
417	/* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
418	main_timerio_output: pinctrl@104280 {
419		compatible = "ti,j7200-padconf", "pinctrl-single";
420		reg = <0x0 0x104280 0x0 0x20>;
421		#pinctrl-cells = <1>;
422		pinctrl-single,register-width = <32>;
423		pinctrl-single,function-mask = <0x0000001f>;
424	};
425
426	main_pmx0: pinctrl@11c000 {
427		compatible = "ti,j7200-padconf", "pinctrl-single";
428		/* Proxy 0 addressing */
429		reg = <0x00 0x11c000 0x00 0x10c>;
430		#pinctrl-cells = <1>;
431		pinctrl-single,register-width = <32>;
432		pinctrl-single,function-mask = <0xffffffff>;
433	};
434
435	main_pmx1: pinctrl@11c110 {
436		compatible = "ti,j7200-padconf", "pinctrl-single";
437		/* Proxy 0 addressing */
438		reg = <0x00 0x11c110 0x00 0x004>;
439		#pinctrl-cells = <1>;
440		pinctrl-single,register-width = <32>;
441		pinctrl-single,function-mask = <0xffffffff>;
442	};
443
444	main_pmx2: pinctrl@11c11c {
445		compatible = "ti,j7200-padconf", "pinctrl-single";
446		/* Proxy 0 addressing */
447		reg = <0x00 0x11c11c 0x00 0x00c>;
448		#pinctrl-cells = <1>;
449		pinctrl-single,register-width = <32>;
450		pinctrl-single,function-mask = <0xffffffff>;
451	};
452
453	main_pmx3: pinctrl@11c164 {
454		compatible = "ti,j7200-padconf", "pinctrl-single";
455		/* Proxy 0 addressing */
456		reg = <0x00 0x11c164 0x00 0x008>;
457		#pinctrl-cells = <1>;
458		pinctrl-single,register-width = <32>;
459		pinctrl-single,function-mask = <0xffffffff>;
460	};
461
462	main_uart0: serial@2800000 {
463		compatible = "ti,j721e-uart", "ti,am654-uart";
464		reg = <0x00 0x02800000 0x00 0x100>;
465		interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
466		clock-frequency = <48000000>;
467		power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
468		clocks = <&k3_clks 146 2>;
469		clock-names = "fclk";
470		status = "disabled";
471	};
472
473	main_uart1: serial@2810000 {
474		compatible = "ti,j721e-uart", "ti,am654-uart";
475		reg = <0x00 0x02810000 0x00 0x100>;
476		interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
477		clock-frequency = <48000000>;
478		power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
479		clocks = <&k3_clks 278 2>;
480		clock-names = "fclk";
481		status = "disabled";
482	};
483
484	main_uart2: serial@2820000 {
485		compatible = "ti,j721e-uart", "ti,am654-uart";
486		reg = <0x00 0x02820000 0x00 0x100>;
487		interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
488		clock-frequency = <48000000>;
489		power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
490		clocks = <&k3_clks 279 2>;
491		clock-names = "fclk";
492		status = "disabled";
493	};
494
495	main_uart3: serial@2830000 {
496		compatible = "ti,j721e-uart", "ti,am654-uart";
497		reg = <0x00 0x02830000 0x00 0x100>;
498		interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
499		clock-frequency = <48000000>;
500		power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
501		clocks = <&k3_clks 280 2>;
502		clock-names = "fclk";
503		status = "disabled";
504	};
505
506	main_uart4: serial@2840000 {
507		compatible = "ti,j721e-uart", "ti,am654-uart";
508		reg = <0x00 0x02840000 0x00 0x100>;
509		interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
510		clock-frequency = <48000000>;
511		power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
512		clocks = <&k3_clks 281 2>;
513		clock-names = "fclk";
514		status = "disabled";
515	};
516
517	main_uart5: serial@2850000 {
518		compatible = "ti,j721e-uart", "ti,am654-uart";
519		reg = <0x00 0x02850000 0x00 0x100>;
520		interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
521		clock-frequency = <48000000>;
522		power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
523		clocks = <&k3_clks 282 2>;
524		clock-names = "fclk";
525		status = "disabled";
526	};
527
528	main_uart6: serial@2860000 {
529		compatible = "ti,j721e-uart", "ti,am654-uart";
530		reg = <0x00 0x02860000 0x00 0x100>;
531		interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
532		clock-frequency = <48000000>;
533		power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
534		clocks = <&k3_clks 283 2>;
535		clock-names = "fclk";
536		status = "disabled";
537	};
538
539	main_uart7: serial@2870000 {
540		compatible = "ti,j721e-uart", "ti,am654-uart";
541		reg = <0x00 0x02870000 0x00 0x100>;
542		interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
543		clock-frequency = <48000000>;
544		power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
545		clocks = <&k3_clks 284 2>;
546		clock-names = "fclk";
547		status = "disabled";
548	};
549
550	main_uart8: serial@2880000 {
551		compatible = "ti,j721e-uart", "ti,am654-uart";
552		reg = <0x00 0x02880000 0x00 0x100>;
553		interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
554		clock-frequency = <48000000>;
555		power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
556		clocks = <&k3_clks 285 2>;
557		clock-names = "fclk";
558		status = "disabled";
559	};
560
561	main_uart9: serial@2890000 {
562		compatible = "ti,j721e-uart", "ti,am654-uart";
563		reg = <0x00 0x02890000 0x00 0x100>;
564		interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
565		clock-frequency = <48000000>;
566		power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
567		clocks = <&k3_clks 286 2>;
568		clock-names = "fclk";
569		status = "disabled";
570	};
571
572	main_i2c0: i2c@2000000 {
573		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
574		reg = <0x00 0x2000000 0x00 0x100>;
575		interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
576		#address-cells = <1>;
577		#size-cells = <0>;
578		clock-names = "fck";
579		clocks = <&k3_clks 187 1>;
580		power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
581		status = "disabled";
582	};
583
584	main_i2c1: i2c@2010000 {
585		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
586		reg = <0x00 0x2010000 0x00 0x100>;
587		interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
588		#address-cells = <1>;
589		#size-cells = <0>;
590		clock-names = "fck";
591		clocks = <&k3_clks 188 1>;
592		power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
593		status = "disabled";
594	};
595
596	main_i2c2: i2c@2020000 {
597		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
598		reg = <0x00 0x2020000 0x00 0x100>;
599		interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
600		#address-cells = <1>;
601		#size-cells = <0>;
602		clock-names = "fck";
603		clocks = <&k3_clks 189 1>;
604		power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
605		status = "disabled";
606	};
607
608	main_i2c3: i2c@2030000 {
609		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
610		reg = <0x00 0x2030000 0x00 0x100>;
611		interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
612		#address-cells = <1>;
613		#size-cells = <0>;
614		clock-names = "fck";
615		clocks = <&k3_clks 190 1>;
616		power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
617		status = "disabled";
618	};
619
620	main_i2c4: i2c@2040000 {
621		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
622		reg = <0x00 0x2040000 0x00 0x100>;
623		interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
624		#address-cells = <1>;
625		#size-cells = <0>;
626		clock-names = "fck";
627		clocks = <&k3_clks 191 1>;
628		power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
629		status = "disabled";
630	};
631
632	main_i2c5: i2c@2050000 {
633		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
634		reg = <0x00 0x2050000 0x00 0x100>;
635		interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
636		#address-cells = <1>;
637		#size-cells = <0>;
638		clock-names = "fck";
639		clocks = <&k3_clks 192 1>;
640		power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
641		status = "disabled";
642	};
643
644	main_i2c6: i2c@2060000 {
645		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
646		reg = <0x00 0x2060000 0x00 0x100>;
647		interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
648		#address-cells = <1>;
649		#size-cells = <0>;
650		clock-names = "fck";
651		clocks = <&k3_clks 193 1>;
652		power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
653		status = "disabled";
654	};
655
656	main_sdhci0: mmc@4f80000 {
657		compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit";
658		reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>;
659		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
660		power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
661		clock-names = "clk_ahb", "clk_xin";
662		clocks = <&k3_clks 91 0>, <&k3_clks 91 3>;
663		ti,otap-del-sel-legacy = <0x0>;
664		ti,otap-del-sel-mmc-hs = <0x0>;
665		ti,otap-del-sel-ddr52 = <0x6>;
666		ti,otap-del-sel-hs200 = <0x8>;
667		ti,otap-del-sel-hs400 = <0x5>;
668		ti,itap-del-sel-legacy = <0x10>;
669		ti,itap-del-sel-mmc-hs = <0xa>;
670		ti,itap-del-sel-ddr52 = <0x3>;
671		ti,strobe-sel = <0x77>;
672		ti,clkbuf-sel = <0x7>;
673		ti,trm-icp = <0x8>;
674		bus-width = <8>;
675		mmc-ddr-1_8v;
676		mmc-hs200-1_8v;
677		mmc-hs400-1_8v;
678		dma-coherent;
679		status = "disabled";
680	};
681
682	main_sdhci1: mmc@4fb0000 {
683		compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit";
684		reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>;
685		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
686		power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
687		clock-names = "clk_ahb", "clk_xin";
688		clocks = <&k3_clks 92 1>, <&k3_clks 92 2>;
689		ti,otap-del-sel-legacy = <0x0>;
690		ti,otap-del-sel-sd-hs = <0x0>;
691		ti,otap-del-sel-sdr12 = <0xf>;
692		ti,otap-del-sel-sdr25 = <0xf>;
693		ti,otap-del-sel-sdr50 = <0xc>;
694		ti,otap-del-sel-sdr104 = <0x5>;
695		ti,otap-del-sel-ddr50 = <0xc>;
696		ti,itap-del-sel-legacy = <0x0>;
697		ti,itap-del-sel-sd-hs = <0x0>;
698		ti,itap-del-sel-sdr12 = <0x0>;
699		ti,itap-del-sel-sdr25 = <0x0>;
700		ti,clkbuf-sel = <0x7>;
701		ti,trm-icp = <0x8>;
702		dma-coherent;
703		status = "disabled";
704	};
705
706	serdes_wiz0: wiz@5060000 {
707		compatible = "ti,j721e-wiz-10g";
708		#address-cells = <1>;
709		#size-cells = <1>;
710		power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
711		clocks = <&k3_clks 292 11>, <&k3_clks 292 85>, <&serdes_refclk>;
712		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
713		num-lanes = <4>;
714		#reset-cells = <1>;
715		ranges = <0x5060000 0x0 0x5060000 0x10000>;
716
717		assigned-clocks = <&k3_clks 292 85>;
718		assigned-clock-parents = <&k3_clks 292 89>;
719
720		wiz0_pll0_refclk: pll0-refclk {
721			clocks = <&k3_clks 292 85>, <&serdes_refclk>;
722			clock-output-names = "wiz0_pll0_refclk";
723			#clock-cells = <0>;
724			assigned-clocks = <&wiz0_pll0_refclk>;
725			assigned-clock-parents = <&k3_clks 292 85>;
726		};
727
728		wiz0_pll1_refclk: pll1-refclk {
729			clocks = <&k3_clks 292 85>, <&serdes_refclk>;
730			clock-output-names = "wiz0_pll1_refclk";
731			#clock-cells = <0>;
732			assigned-clocks = <&wiz0_pll1_refclk>;
733			assigned-clock-parents = <&k3_clks 292 85>;
734		};
735
736		wiz0_refclk_dig: refclk-dig {
737			clocks = <&k3_clks 292 85>, <&serdes_refclk>;
738			clock-output-names = "wiz0_refclk_dig";
739			#clock-cells = <0>;
740			assigned-clocks = <&wiz0_refclk_dig>;
741			assigned-clock-parents = <&k3_clks 292 85>;
742		};
743
744		wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
745			clocks = <&wiz0_refclk_dig>;
746			#clock-cells = <0>;
747		};
748
749		serdes0: serdes@5060000 {
750			compatible = "ti,j721e-serdes-10g";
751			reg = <0x05060000 0x00010000>;
752			reg-names = "torrent_phy";
753			resets = <&serdes_wiz0 0>;
754			reset-names = "torrent_reset";
755			clocks = <&wiz0_pll0_refclk>;
756			clock-names = "refclk";
757			#address-cells = <1>;
758			#size-cells = <0>;
759		};
760	};
761
762	pcie1_rc: pcie@2910000 {
763		compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
764		reg = <0x00 0x02910000 0x00 0x1000>,
765		      <0x00 0x02917000 0x00 0x400>,
766		      <0x00 0x0d800000 0x00 0x00800000>,
767		      <0x41 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */
768		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
769		interrupt-names = "link_state";
770		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
771		device_type = "pci";
772		ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>;
773		max-link-speed = <3>;
774		num-lanes = <4>;
775		power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
776		clocks = <&k3_clks 240 6>;
777		clock-names = "fck";
778		#address-cells = <3>;
779		#size-cells = <2>;
780		bus-range = <0x0 0xff>;
781		cdns,no-bar-match-nbits = <64>;
782		vendor-id = <0x104c>;
783		device-id = <0xb00f>;
784		msi-map = <0x0 &gic_its 0x0 0x10000>;
785		dma-coherent;
786		ranges = <0x01000000 0x00 0x00001000 0x41 0x00001000 0x00 0x00100000>, /* IO (1 MB) */
787			 <0x02000000 0x00 0x00101000 0x41 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */
788		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
789		status = "disabled";
790	};
791
792	usbss0: cdns-usb@4104000 {
793		compatible = "ti,j721e-usb";
794		reg = <0x00 0x4104000 0x00 0x100>;
795		dma-coherent;
796		power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
797		clocks = <&k3_clks 288 12>, <&k3_clks 288 3>;
798		clock-names = "ref", "lpm";
799		assigned-clocks = <&k3_clks 288 12>;	/* USB2_REFCLK */
800		assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */
801		#address-cells = <2>;
802		#size-cells = <2>;
803		ranges;
804
805		usb0: usb@6000000 {
806			compatible = "cdns,usb3";
807			reg = <0x00 0x6000000 0x00 0x10000>,
808			      <0x00 0x6010000 0x00 0x10000>,
809			      <0x00 0x6020000 0x00 0x10000>;
810			reg-names = "otg", "xhci", "dev";
811			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,	/* irq.0 */
812				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,	/* irq.6 */
813				     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;	/* otgirq.0 */
814			interrupt-names = "host",
815					  "peripheral",
816					  "otg";
817			maximum-speed = "super-speed";
818			dr_mode = "otg";
819			cdns,phyrst-a-enable;
820		};
821	};
822
823	main_gpio0: gpio@600000 {
824		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
825		reg = <0x00 0x00600000 0x00 0x100>;
826		gpio-controller;
827		#gpio-cells = <2>;
828		interrupt-parent = <&main_gpio_intr>;
829		interrupts = <145>, <146>, <147>, <148>,
830			     <149>;
831		interrupt-controller;
832		#interrupt-cells = <2>;
833		ti,ngpio = <69>;
834		ti,davinci-gpio-unbanked = <0>;
835		power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
836		clocks = <&k3_clks 105 0>;
837		clock-names = "gpio";
838		status = "disabled";
839	};
840
841	main_gpio2: gpio@610000 {
842		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
843		reg = <0x00 0x00610000 0x00 0x100>;
844		gpio-controller;
845		#gpio-cells = <2>;
846		interrupt-parent = <&main_gpio_intr>;
847		interrupts = <154>, <155>, <156>, <157>,
848			     <158>;
849		interrupt-controller;
850		#interrupt-cells = <2>;
851		ti,ngpio = <69>;
852		ti,davinci-gpio-unbanked = <0>;
853		power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
854		clocks = <&k3_clks 107 0>;
855		clock-names = "gpio";
856		status = "disabled";
857	};
858
859	main_gpio4: gpio@620000 {
860		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
861		reg = <0x00 0x00620000 0x00 0x100>;
862		gpio-controller;
863		#gpio-cells = <2>;
864		interrupt-parent = <&main_gpio_intr>;
865		interrupts = <163>, <164>, <165>, <166>,
866			     <167>;
867		interrupt-controller;
868		#interrupt-cells = <2>;
869		ti,ngpio = <69>;
870		ti,davinci-gpio-unbanked = <0>;
871		power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
872		clocks = <&k3_clks 109 0>;
873		clock-names = "gpio";
874		status = "disabled";
875	};
876
877	main_gpio6: gpio@630000 {
878		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
879		reg = <0x00 0x00630000 0x00 0x100>;
880		gpio-controller;
881		#gpio-cells = <2>;
882		interrupt-parent = <&main_gpio_intr>;
883		interrupts = <172>, <173>, <174>, <175>,
884			     <176>;
885		interrupt-controller;
886		#interrupt-cells = <2>;
887		ti,ngpio = <69>;
888		ti,davinci-gpio-unbanked = <0>;
889		power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
890		clocks = <&k3_clks 111 0>;
891		clock-names = "gpio";
892		status = "disabled";
893	};
894
895	main_mcan0: can@2701000 {
896		compatible = "bosch,m_can";
897		reg = <0x00 0x02701000 0x00 0x200>,
898		      <0x00 0x02708000 0x00 0x8000>;
899		reg-names = "m_can", "message_ram";
900		power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
901		clocks = <&k3_clks 156 0>, <&k3_clks 156 2>;
902		clock-names = "hclk", "cclk";
903		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
904			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
905		interrupt-names = "int0", "int1";
906		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
907		status = "disabled";
908	};
909
910	main_mcan1: can@2711000 {
911		compatible = "bosch,m_can";
912		reg = <0x00 0x02711000 0x00 0x200>,
913		      <0x00 0x02718000 0x00 0x8000>;
914		reg-names = "m_can", "message_ram";
915		power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
916		clocks = <&k3_clks 158 0>, <&k3_clks 158 2>;
917		clock-names = "hclk", "cclk";
918		interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
919			     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
920		interrupt-names = "int0", "int1";
921		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
922		status = "disabled";
923	};
924
925	main_mcan2: can@2721000 {
926		compatible = "bosch,m_can";
927		reg = <0x00 0x02721000 0x00 0x200>,
928		      <0x00 0x02728000 0x00 0x8000>;
929		reg-names = "m_can", "message_ram";
930		power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
931		clocks = <&k3_clks 160 0>, <&k3_clks 160 2>;
932		clock-names = "hclk", "cclk";
933		interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
934			     <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
935		interrupt-names = "int0", "int1";
936		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
937		status = "disabled";
938	};
939
940	main_mcan3: can@2731000 {
941		compatible = "bosch,m_can";
942		reg = <0x00 0x02731000 0x00 0x200>,
943		      <0x00 0x02738000 0x00 0x8000>;
944		reg-names = "m_can", "message_ram";
945		power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
946		clocks = <&k3_clks 161 0>, <&k3_clks 161 2>;
947		clock-names = "hclk", "cclk";
948		interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
949			     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
950		interrupt-names = "int0", "int1";
951		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
952		status = "disabled";
953	};
954
955	main_mcan4: can@2741000 {
956		compatible = "bosch,m_can";
957		reg = <0x00 0x02741000 0x00 0x200>,
958		      <0x00 0x02748000 0x00 0x8000>;
959		reg-names = "m_can", "message_ram";
960		power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
961		clocks = <&k3_clks 162 0>, <&k3_clks 162 2>;
962		clock-names = "hclk", "cclk";
963		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
964			     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
965		interrupt-names = "int0", "int1";
966		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
967		status = "disabled";
968	};
969
970	main_mcan5: can@2751000 {
971		compatible = "bosch,m_can";
972		reg = <0x00 0x02751000 0x00 0x200>,
973		      <0x00 0x02758000 0x00 0x8000>;
974		reg-names = "m_can", "message_ram";
975		power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
976		clocks = <&k3_clks 163 0>, <&k3_clks 163 2>;
977		clock-names = "hclk", "cclk";
978		interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
979			     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
980		interrupt-names = "int0", "int1";
981		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
982		status = "disabled";
983	};
984
985	main_mcan6: can@2761000 {
986		compatible = "bosch,m_can";
987		reg = <0x00 0x02761000 0x00 0x200>,
988		      <0x00 0x02768000 0x00 0x8000>;
989		reg-names = "m_can", "message_ram";
990		power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
991		clocks = <&k3_clks 164 0>, <&k3_clks 164 2>;
992		clock-names = "hclk", "cclk";
993		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
994			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
995		interrupt-names = "int0", "int1";
996		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
997		status = "disabled";
998	};
999
1000	main_mcan7: can@2771000 {
1001		compatible = "bosch,m_can";
1002		reg = <0x00 0x02771000 0x00 0x200>,
1003		      <0x00 0x02778000 0x00 0x8000>;
1004		reg-names = "m_can", "message_ram";
1005		power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
1006		clocks = <&k3_clks 165 0>, <&k3_clks 165 2>;
1007		clock-names = "hclk", "cclk";
1008		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1009			     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1010		interrupt-names = "int0", "int1";
1011		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1012		status = "disabled";
1013	};
1014
1015	main_mcan8: can@2781000 {
1016		compatible = "bosch,m_can";
1017		reg = <0x00 0x02781000 0x00 0x200>,
1018		      <0x00 0x02788000 0x00 0x8000>;
1019		reg-names = "m_can", "message_ram";
1020		power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
1021		clocks = <&k3_clks 166 0>, <&k3_clks 166 2>;
1022		clock-names = "hclk", "cclk";
1023		interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
1024			     <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>;
1025		interrupt-names = "int0", "int1";
1026		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1027		status = "disabled";
1028	};
1029
1030	main_mcan9: can@2791000 {
1031		compatible = "bosch,m_can";
1032		reg = <0x00 0x02791000 0x00 0x200>,
1033		      <0x00 0x02798000 0x00 0x8000>;
1034		reg-names = "m_can", "message_ram";
1035		power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>;
1036		clocks = <&k3_clks 167 0>, <&k3_clks 167 2>;
1037		clock-names = "hclk", "cclk";
1038		interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>,
1039			     <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
1040		interrupt-names = "int0", "int1";
1041		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1042		status = "disabled";
1043	};
1044
1045	main_mcan10: can@27a1000 {
1046		compatible = "bosch,m_can";
1047		reg = <0x00 0x027a1000 0x00 0x200>,
1048		      <0x00 0x027a8000 0x00 0x8000>;
1049		reg-names = "m_can", "message_ram";
1050		power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>;
1051		clocks = <&k3_clks 168 0>, <&k3_clks 168 2>;
1052		clock-names = "hclk", "cclk";
1053		interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>,
1054			     <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1055		interrupt-names = "int0", "int1";
1056		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1057		status = "disabled";
1058	};
1059
1060	main_mcan11: can@27b1000 {
1061		compatible = "bosch,m_can";
1062		reg = <0x00 0x027b1000 0x00 0x200>,
1063		      <0x00 0x027b8000 0x00 0x8000>;
1064		reg-names = "m_can", "message_ram";
1065		power-domains = <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>;
1066		clocks = <&k3_clks 169 0>, <&k3_clks 169 2>;
1067		clock-names = "hclk", "cclk";
1068		interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
1069			     <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1070		interrupt-names = "int0", "int1";
1071		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1072		status = "disabled";
1073	};
1074
1075	main_mcan12: can@27c1000 {
1076		compatible = "bosch,m_can";
1077		reg = <0x00 0x027c1000 0x00 0x200>,
1078		      <0x00 0x027c8000 0x00 0x8000>;
1079		reg-names = "m_can", "message_ram";
1080		power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>;
1081		clocks = <&k3_clks 170 0>, <&k3_clks 170 2>;
1082		clock-names = "hclk", "cclk";
1083		interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
1084			     <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
1085		interrupt-names = "int0", "int1";
1086		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1087		status = "disabled";
1088	};
1089
1090	main_mcan13: can@27d1000 {
1091		compatible = "bosch,m_can";
1092		reg = <0x00 0x027d1000 0x00 0x200>,
1093		      <0x00 0x027d8000 0x00 0x8000>;
1094		reg-names = "m_can", "message_ram";
1095		power-domains = <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>;
1096		clocks = <&k3_clks 171 0>, <&k3_clks 171 2>;
1097		clock-names = "hclk", "cclk";
1098		interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
1099			     <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>;
1100		interrupt-names = "int0", "int1";
1101		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1102		status = "disabled";
1103	};
1104
1105	main_mcan14: can@2681000 {
1106		compatible = "bosch,m_can";
1107		reg = <0x00 0x02681000 0x00 0x200>,
1108		      <0x00 0x02688000 0x00 0x8000>;
1109		reg-names = "m_can", "message_ram";
1110		power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>;
1111		clocks = <&k3_clks 150 0>, <&k3_clks 150 2>;
1112		clock-names = "hclk", "cclk";
1113		interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
1114			     <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>;
1115		interrupt-names = "int0", "int1";
1116		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1117		status = "disabled";
1118	};
1119
1120	main_mcan15: can@2691000 {
1121		compatible = "bosch,m_can";
1122		reg = <0x00 0x02691000 0x00 0x200>,
1123		      <0x00 0x02698000 0x00 0x8000>;
1124		reg-names = "m_can", "message_ram";
1125		power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
1126		clocks = <&k3_clks 151 0>, <&k3_clks 151 2>;
1127		clock-names = "hclk", "cclk";
1128		interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
1129			     <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>;
1130		interrupt-names = "int0", "int1";
1131		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1132		status = "disabled";
1133	};
1134
1135	main_mcan16: can@26a1000 {
1136		compatible = "bosch,m_can";
1137		reg = <0x00 0x026a1000 0x00 0x200>,
1138		      <0x00 0x026a8000 0x00 0x8000>;
1139		reg-names = "m_can", "message_ram";
1140		power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
1141		clocks = <&k3_clks 152 0>, <&k3_clks 152 2>;
1142		clock-names = "hclk", "cclk";
1143		interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
1144			     <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>;
1145		interrupt-names = "int0", "int1";
1146		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1147		status = "disabled";
1148	};
1149
1150	main_mcan17: can@26b1000 {
1151		compatible = "bosch,m_can";
1152		reg = <0x00 0x026b1000 0x00 0x200>,
1153		      <0x00 0x026b8000 0x00 0x8000>;
1154		reg-names = "m_can", "message_ram";
1155		power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
1156		clocks = <&k3_clks 153 0>, <&k3_clks 153 2>;
1157		clock-names = "hclk", "cclk";
1158		interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>,
1159			     <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>;
1160		interrupt-names = "int0", "int1";
1161		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1162		status = "disabled";
1163	};
1164
1165	main_spi0: spi@2100000 {
1166		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1167		reg = <0x00 0x02100000 0x00 0x400>;
1168		interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
1169		#address-cells = <1>;
1170		#size-cells = <0>;
1171		power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>;
1172		clocks = <&k3_clks 266 4>;
1173		status = "disabled";
1174	};
1175
1176	main_spi1: spi@2110000 {
1177		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1178		reg = <0x00 0x02110000 0x00 0x400>;
1179		interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
1180		#address-cells = <1>;
1181		#size-cells = <0>;
1182		power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>;
1183		clocks = <&k3_clks 267 4>;
1184		status = "disabled";
1185	};
1186
1187	main_spi2: spi@2120000 {
1188		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1189		reg = <0x00 0x02120000 0x00 0x400>;
1190		interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1191		#address-cells = <1>;
1192		#size-cells = <0>;
1193		power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>;
1194		clocks = <&k3_clks 268 4>;
1195		status = "disabled";
1196	};
1197
1198	main_spi3: spi@2130000 {
1199		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1200		reg = <0x00 0x02130000 0x00 0x400>;
1201		interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1202		#address-cells = <1>;
1203		#size-cells = <0>;
1204		power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>;
1205		clocks = <&k3_clks 269 4>;
1206		status = "disabled";
1207	};
1208
1209	main_spi4: spi@2140000 {
1210		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1211		reg = <0x00 0x02140000 0x00 0x400>;
1212		interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
1213		#address-cells = <1>;
1214		#size-cells = <0>;
1215		power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>;
1216		clocks = <&k3_clks 270 2>;
1217		status = "disabled";
1218	};
1219
1220	main_spi5: spi@2150000 {
1221		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1222		reg = <0x00 0x02150000 0x00 0x400>;
1223		interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
1224		#address-cells = <1>;
1225		#size-cells = <0>;
1226		power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>;
1227		clocks = <&k3_clks 271 4>;
1228		status = "disabled";
1229	};
1230
1231	main_spi6: spi@2160000 {
1232		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1233		reg = <0x00 0x02160000 0x00 0x400>;
1234		interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1235		#address-cells = <1>;
1236		#size-cells = <0>;
1237		power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>;
1238		clocks = <&k3_clks 272 4>;
1239		status = "disabled";
1240	};
1241
1242	main_spi7: spi@2170000 {
1243		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1244		reg = <0x00 0x02170000 0x00 0x400>;
1245		interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
1246		#address-cells = <1>;
1247		#size-cells = <0>;
1248		power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>;
1249		clocks = <&k3_clks 273 4>;
1250		status = "disabled";
1251	};
1252
1253	watchdog0: watchdog@2200000 {
1254		compatible = "ti,j7-rti-wdt";
1255		reg = <0x0 0x2200000 0x0 0x100>;
1256		clocks = <&k3_clks 252 1>;
1257		power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
1258		assigned-clocks = <&k3_clks 252 1>;
1259		assigned-clock-parents = <&k3_clks 252 5>;
1260	};
1261
1262	watchdog1: watchdog@2210000 {
1263		compatible = "ti,j7-rti-wdt";
1264		reg = <0x0 0x2210000 0x0 0x100>;
1265		clocks = <&k3_clks 253 1>;
1266		power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
1267		assigned-clocks = <&k3_clks 253 1>;
1268		assigned-clock-parents = <&k3_clks 253 5>;
1269	};
1270
1271	main_timer0: timer@2400000 {
1272		compatible = "ti,am654-timer";
1273		reg = <0x00 0x2400000 0x00 0x400>;
1274		interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
1275		clocks = <&k3_clks 49 1>;
1276		clock-names = "fck";
1277		assigned-clocks = <&k3_clks 49 1>;
1278		assigned-clock-parents = <&k3_clks 49 2>;
1279		power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
1280		ti,timer-pwm;
1281	};
1282
1283	main_timer1: timer@2410000 {
1284		compatible = "ti,am654-timer";
1285		reg = <0x00 0x2410000 0x00 0x400>;
1286		interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1287		clocks = <&k3_clks 50 1>;
1288		clock-names = "fck";
1289		assigned-clocks = <&k3_clks 50 1>, <&k3_clks 313 0>;
1290		assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 313 1>;
1291		power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
1292		ti,timer-pwm;
1293	};
1294
1295	main_timer2: timer@2420000 {
1296		compatible = "ti,am654-timer";
1297		reg = <0x00 0x2420000 0x00 0x400>;
1298		interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1299		clocks = <&k3_clks 51 1>;
1300		clock-names = "fck";
1301		assigned-clocks = <&k3_clks 51 1>;
1302		assigned-clock-parents = <&k3_clks 51 2>;
1303		power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
1304		ti,timer-pwm;
1305	};
1306
1307	main_timer3: timer@2430000 {
1308		compatible = "ti,am654-timer";
1309		reg = <0x00 0x2430000 0x00 0x400>;
1310		interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
1311		clocks = <&k3_clks 52 1>;
1312		clock-names = "fck";
1313		assigned-clocks = <&k3_clks 52 1>, <&k3_clks 314 0>;
1314		assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 314 1>;
1315		power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
1316		ti,timer-pwm;
1317	};
1318
1319	main_timer4: timer@2440000 {
1320		compatible = "ti,am654-timer";
1321		reg = <0x00 0x2440000 0x00 0x400>;
1322		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
1323		clocks = <&k3_clks 53 1>;
1324		clock-names = "fck";
1325		assigned-clocks = <&k3_clks 53 1>;
1326		assigned-clock-parents = <&k3_clks 53 2>;
1327		power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
1328		ti,timer-pwm;
1329	};
1330
1331	main_timer5: timer@2450000 {
1332		compatible = "ti,am654-timer";
1333		reg = <0x00 0x2450000 0x00 0x400>;
1334		interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
1335		clocks = <&k3_clks 54 1>;
1336		clock-names = "fck";
1337		assigned-clocks = <&k3_clks 54 1>, <&k3_clks 315 0>;
1338		assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 315 1>;
1339		power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>;
1340		ti,timer-pwm;
1341	};
1342
1343	main_timer6: timer@2460000 {
1344		compatible = "ti,am654-timer";
1345		reg = <0x00 0x2460000 0x00 0x400>;
1346		interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
1347		clocks = <&k3_clks 55 1>;
1348		clock-names = "fck";
1349		assigned-clocks = <&k3_clks 55 1>;
1350		assigned-clock-parents = <&k3_clks 55 2>;
1351		power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>;
1352		ti,timer-pwm;
1353	};
1354
1355	main_timer7: timer@2470000 {
1356		compatible = "ti,am654-timer";
1357		reg = <0x00 0x2470000 0x00 0x400>;
1358		interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
1359		clocks = <&k3_clks 57 1>;
1360		clock-names = "fck";
1361		assigned-clocks = <&k3_clks 57 1>, <&k3_clks 316 0>;
1362		assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 316 1>;
1363		power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
1364		ti,timer-pwm;
1365	};
1366
1367	main_timer8: timer@2480000 {
1368		compatible = "ti,am654-timer";
1369		reg = <0x00 0x2480000 0x00 0x400>;
1370		interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
1371		clocks = <&k3_clks 58 1>;
1372		clock-names = "fck";
1373		assigned-clocks = <&k3_clks 58 1>;
1374		assigned-clock-parents = <&k3_clks 58 2>;
1375		power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
1376		ti,timer-pwm;
1377	};
1378
1379	main_timer9: timer@2490000 {
1380		compatible = "ti,am654-timer";
1381		reg = <0x00 0x2490000 0x00 0x400>;
1382		interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
1383		clocks = <&k3_clks 59 1>;
1384		clock-names = "fck";
1385		assigned-clocks = <&k3_clks 59 1>, <&k3_clks 317 0>;
1386		assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 317 1>;
1387		power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>;
1388		ti,timer-pwm;
1389	};
1390
1391	main_timer10: timer@24a0000 {
1392		compatible = "ti,am654-timer";
1393		reg = <0x00 0x24a0000 0x00 0x400>;
1394		interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
1395		clocks = <&k3_clks 60 1>;
1396		clock-names = "fck";
1397		assigned-clocks = <&k3_clks 60 1>;
1398		assigned-clock-parents = <&k3_clks 60 2>;
1399		power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>;
1400		ti,timer-pwm;
1401	};
1402
1403	main_timer11: timer@24b0000 {
1404		compatible = "ti,am654-timer";
1405		reg = <0x00 0x24b0000 0x00 0x400>;
1406		interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
1407		clocks = <&k3_clks 62 1>;
1408		clock-names = "fck";
1409		assigned-clocks = <&k3_clks 62 1>, <&k3_clks 318 0>;
1410		assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 318 1>;
1411		power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
1412		ti,timer-pwm;
1413	};
1414
1415	main_timer12: timer@24c0000 {
1416		compatible = "ti,am654-timer";
1417		reg = <0x00 0x24c0000 0x00 0x400>;
1418		interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
1419		clocks = <&k3_clks 63 1>;
1420		clock-names = "fck";
1421		assigned-clocks = <&k3_clks 63 1>;
1422		assigned-clock-parents = <&k3_clks 63 2>;
1423		power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
1424		ti,timer-pwm;
1425	};
1426
1427	main_timer13: timer@24d0000 {
1428		compatible = "ti,am654-timer";
1429		reg = <0x00 0x24d0000 0x00 0x400>;
1430		interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
1431		clocks = <&k3_clks 64 1>;
1432		clock-names = "fck";
1433		assigned-clocks = <&k3_clks 64 1>, <&k3_clks 319 0>;
1434		assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 319 1>;
1435		power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
1436		ti,timer-pwm;
1437	};
1438
1439	main_timer14: timer@24e0000 {
1440		compatible = "ti,am654-timer";
1441		reg = <0x00 0x24e0000 0x00 0x400>;
1442		interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1443		clocks = <&k3_clks 65 1>;
1444		clock-names = "fck";
1445		assigned-clocks = <&k3_clks 65 1>;
1446		assigned-clock-parents = <&k3_clks 65 2>;
1447		power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
1448		ti,timer-pwm;
1449	};
1450
1451	main_timer15: timer@24f0000 {
1452		compatible = "ti,am654-timer";
1453		reg = <0x00 0x24f0000 0x00 0x400>;
1454		interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
1455		clocks = <&k3_clks 66 1>;
1456		clock-names = "fck";
1457		assigned-clocks = <&k3_clks 66 1>, <&k3_clks 320 0>;
1458		assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 320 1>;
1459		power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>;
1460		ti,timer-pwm;
1461	};
1462
1463	main_timer16: timer@2500000 {
1464		compatible = "ti,am654-timer";
1465		reg = <0x00 0x2500000 0x00 0x400>;
1466		interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
1467		clocks = <&k3_clks 67 1>;
1468		clock-names = "fck";
1469		assigned-clocks = <&k3_clks 67 1>;
1470		assigned-clock-parents = <&k3_clks 67 2>;
1471		power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
1472		ti,timer-pwm;
1473	};
1474
1475	main_timer17: timer@2510000 {
1476		compatible = "ti,am654-timer";
1477		reg = <0x00 0x2510000 0x00 0x400>;
1478		interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
1479		clocks = <&k3_clks 68 1>;
1480		clock-names = "fck";
1481		assigned-clocks = <&k3_clks 68 1>, <&k3_clks 321 0>;
1482		assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 321 1>;
1483		power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>;
1484		ti,timer-pwm;
1485	};
1486
1487	main_timer18: timer@2520000 {
1488		compatible = "ti,am654-timer";
1489		reg = <0x00 0x2520000 0x00 0x400>;
1490		interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
1491		clocks = <&k3_clks 69 1>;
1492		clock-names = "fck";
1493		assigned-clocks = <&k3_clks 69 1>;
1494		assigned-clock-parents = <&k3_clks 69 2>;
1495		power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>;
1496		ti,timer-pwm;
1497	};
1498
1499	main_timer19: timer@2530000 {
1500		compatible = "ti,am654-timer";
1501		reg = <0x00 0x2530000 0x00 0x400>;
1502		interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
1503		clocks = <&k3_clks 70 1>;
1504		clock-names = "fck";
1505		assigned-clocks = <&k3_clks 70 1>, <&k3_clks 322 0>;
1506		assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 322 1>;
1507		power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>;
1508		ti,timer-pwm;
1509	};
1510
1511	main_r5fss0: r5fss@5c00000 {
1512		compatible = "ti,j7200-r5fss";
1513		ti,cluster-mode = <1>;
1514		#address-cells = <1>;
1515		#size-cells = <1>;
1516		ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
1517			 <0x5d00000 0x00 0x5d00000 0x20000>;
1518		power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
1519
1520		main_r5fss0_core0: r5f@5c00000 {
1521			compatible = "ti,j7200-r5f";
1522			reg = <0x5c00000 0x00010000>,
1523			      <0x5c10000 0x00010000>;
1524			reg-names = "atcm", "btcm";
1525			ti,sci = <&dmsc>;
1526			ti,sci-dev-id = <245>;
1527			ti,sci-proc-ids = <0x06 0xff>;
1528			resets = <&k3_reset 245 1>;
1529			firmware-name = "j7200-main-r5f0_0-fw";
1530			ti,atcm-enable = <1>;
1531			ti,btcm-enable = <1>;
1532			ti,loczrama = <1>;
1533		};
1534
1535		main_r5fss0_core1: r5f@5d00000 {
1536			compatible = "ti,j7200-r5f";
1537			reg = <0x5d00000 0x00008000>,
1538			      <0x5d10000 0x00008000>;
1539			reg-names = "atcm", "btcm";
1540			ti,sci = <&dmsc>;
1541			ti,sci-dev-id = <246>;
1542			ti,sci-proc-ids = <0x07 0xff>;
1543			resets = <&k3_reset 246 1>;
1544			firmware-name = "j7200-main-r5f0_1-fw";
1545			ti,atcm-enable = <1>;
1546			ti,btcm-enable = <1>;
1547			ti,loczrama = <1>;
1548		};
1549	};
1550
1551	main_esm: esm@700000 {
1552		compatible = "ti,j721e-esm";
1553		reg = <0x0 0x700000 0x0 0x1000>;
1554		bootph-pre-ram;
1555		ti,esm-pins = <656>, <657>;
1556	};
1557};
1558