1// SPDX-License-Identifier: GPL-2.0 OR MIT 2/* 3 * Copyright (c) 2024 Yixun Lan <dlan@gentoo.org> 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7 8#define K1_PADCONF(pin, func) (((pin) << 16) | (func)) 9 10/* Map GPIO pin to each bank's <index, offset> */ 11#define K1_GPIO(x) (x / 32) (x % 32) 12 13&pinctrl { 14 gmac0_cfg: gmac0-cfg { 15 gmac0-pins { 16 pinmux = <K1_PADCONF(0, 1)>, /* gmac0_rxdv */ 17 <K1_PADCONF(1, 1)>, /* gmac0_rx_d0 */ 18 <K1_PADCONF(2, 1)>, /* gmac0_rx_d1 */ 19 <K1_PADCONF(3, 1)>, /* gmac0_rx_clk */ 20 <K1_PADCONF(4, 1)>, /* gmac0_rx_d2 */ 21 <K1_PADCONF(5, 1)>, /* gmac0_rx_d3 */ 22 <K1_PADCONF(6, 1)>, /* gmac0_tx_d0 */ 23 <K1_PADCONF(7, 1)>, /* gmac0_tx_d1 */ 24 <K1_PADCONF(8, 1)>, /* gmac0_tx */ 25 <K1_PADCONF(9, 1)>, /* gmac0_tx_d2 */ 26 <K1_PADCONF(10, 1)>, /* gmac0_tx_d3 */ 27 <K1_PADCONF(11, 1)>, /* gmac0_tx_en */ 28 <K1_PADCONF(12, 1)>, /* gmac0_mdc */ 29 <K1_PADCONF(13, 1)>, /* gmac0_mdio */ 30 <K1_PADCONF(14, 1)>, /* gmac0_int_n */ 31 <K1_PADCONF(45, 1)>; /* gmac0_clk_ref */ 32 33 bias-pull-up = <0>; 34 drive-strength = <21>; 35 }; 36 }; 37 38 gmac1_cfg: gmac1-cfg { 39 gmac1-pins { 40 pinmux = <K1_PADCONF(29, 1)>, /* gmac1_rxdv */ 41 <K1_PADCONF(30, 1)>, /* gmac1_rx_d0 */ 42 <K1_PADCONF(31, 1)>, /* gmac1_rx_d1 */ 43 <K1_PADCONF(32, 1)>, /* gmac1_rx_clk */ 44 <K1_PADCONF(33, 1)>, /* gmac1_rx_d2 */ 45 <K1_PADCONF(34, 1)>, /* gmac1_rx_d3 */ 46 <K1_PADCONF(35, 1)>, /* gmac1_tx_d0 */ 47 <K1_PADCONF(36, 1)>, /* gmac1_tx_d1 */ 48 <K1_PADCONF(37, 1)>, /* gmac1_tx */ 49 <K1_PADCONF(38, 1)>, /* gmac1_tx_d2 */ 50 <K1_PADCONF(39, 1)>, /* gmac1_tx_d3 */ 51 <K1_PADCONF(40, 1)>, /* gmac1_tx_en */ 52 <K1_PADCONF(41, 1)>, /* gmac1_mdc */ 53 <K1_PADCONF(42, 1)>, /* gmac1_mdio */ 54 <K1_PADCONF(43, 1)>, /* gmac1_int_n */ 55 <K1_PADCONF(46, 1)>; /* gmac1_clk_ref */ 56 57 bias-pull-up = <0>; 58 drive-strength = <21>; 59 }; 60 }; 61 62 i2c2_0_cfg: i2c2-0-cfg { 63 i2c2-0-pins { 64 pinmux = <K1_PADCONF(84, 4)>, /* I2C2_SCL */ 65 <K1_PADCONF(85, 4)>; /* I2C2_SDA */ 66 }; 67 }; 68 69 i2c8_cfg: i2c8-cfg { 70 i2c8-0-pins { 71 pinmux = <K1_PADCONF(93, 0)>, /* PWR_SCL */ 72 <K1_PADCONF(94, 0)>; /* PWR_SDA */ 73 }; 74 }; 75 76 qspi_cfg: qspi-cfg { 77 qspi-pins { 78 pinmux = <K1_PADCONF(98, 0)>, /* QSPI_DATA3 */ 79 <K1_PADCONF(99, 0)>, /* QSPI_DATA2 */ 80 <K1_PADCONF(100, 0)>, /* QSPI_DATA1 */ 81 <K1_PADCONF(101, 0)>, /* QSPI_DATA0 */ 82 <K1_PADCONF(102, 0)>; /* QSPI_CLK */ 83 84 bias-disable; 85 drive-strength = <19>; 86 power-source = <3300>; 87 }; 88 89 qspi-cs1-pins { 90 pinmux = <K1_PADCONF(103, 0)>; /* QSPI_CS1 */ 91 bias-pull-up = <0>; 92 drive-strength = <19>; 93 power-source = <3300>; 94 }; 95 }; 96 97 /omit-if-no-ref/ 98 uart0_0_cfg: uart0-0-cfg { 99 uart0-0-pins { 100 pinmux = <K1_PADCONF(104, 3)>, /* uart0_txd */ 101 <K1_PADCONF(105, 3)>; /* uart0_rxd */ 102 power-source = <3300>; 103 bias-pull-up = <0>; 104 drive-strength = <19>; 105 }; 106 }; 107 108 /omit-if-no-ref/ 109 uart0_1_cfg: uart0-1-cfg { 110 uart0-1-pins { 111 pinmux = <K1_PADCONF(108, 1)>, /* uart0_txd */ 112 <K1_PADCONF(80, 3)>; /* uart0_rxd */ 113 power-source = <3300>; 114 bias-pull-up = <0>; 115 drive-strength = <19>; 116 }; 117 }; 118 119 /omit-if-no-ref/ 120 uart0_2_cfg: uart0-2-cfg { 121 uart0-2-pins { 122 pinmux = <K1_PADCONF(68, 2)>, /* uart0_txd */ 123 <K1_PADCONF(69, 2)>; /* uart0_rxd */ 124 bias-pull-up = <0>; 125 drive-strength = <32>; 126 }; 127 }; 128 129 /omit-if-no-ref/ 130 uart2_0_cfg: uart2-0-cfg { 131 uart2-0-pins { 132 pinmux = <K1_PADCONF(21, 1)>, /* uart2_txd */ 133 <K1_PADCONF(22, 1)>; /* uart2_rxd */ 134 bias-pull-up = <0>; 135 drive-strength = <32>; 136 }; 137 }; 138 139 /omit-if-no-ref/ 140 uart2_0_cts_rts_cfg: uart2-0-cts-rts-cfg { 141 uart2-0-pins { 142 pinmux = <K1_PADCONF(23, 1)>, /* uart2_cts */ 143 <K1_PADCONF(24, 1)>; /* uart2_rts */ 144 bias-pull-up = <0>; 145 drive-strength = <32>; 146 }; 147 }; 148 149 /omit-if-no-ref/ 150 uart3_0_cfg: uart3-0-cfg { 151 uart3-0-pins { 152 pinmux = <K1_PADCONF(81, 2)>, /* uart3_txd */ 153 <K1_PADCONF(82, 2)>; /* uart3_rxd */ 154 bias-pull-up = <0>; 155 drive-strength = <32>; 156 }; 157 }; 158 159 /omit-if-no-ref/ 160 uart3_0_cts_rts_cfg: uart3-0-cts-rts-cfg { 161 uart3-0-pins { 162 pinmux = <K1_PADCONF(83, 2)>, /* uart3_cts */ 163 <K1_PADCONF(84, 2)>; /* uart3_rts */ 164 bias-pull-up = <0>; 165 drive-strength = <32>; 166 }; 167 }; 168 169 /omit-if-no-ref/ 170 uart3_1_cfg: uart3-1-cfg { 171 uart3-1-pins { 172 pinmux = <K1_PADCONF(18, 2)>, /* uart3_txd */ 173 <K1_PADCONF(19, 2)>; /* uart3_rxd */ 174 bias-pull-up = <0>; 175 drive-strength = <32>; 176 }; 177 }; 178 179 /omit-if-no-ref/ 180 uart3_1_cts_rts_cfg: uart3-1-cts-rts-cfg { 181 uart3-1-pins { 182 pinmux = <K1_PADCONF(20, 2)>, /* uart3_cts */ 183 <K1_PADCONF(21, 2)>; /* uart3_rts */ 184 bias-pull-up = <0>; 185 drive-strength = <32>; 186 }; 187 }; 188 189 /omit-if-no-ref/ 190 uart3_2_cfg: uart3-2-cfg { 191 uart3-2-pins { 192 pinmux = <K1_PADCONF(53, 4)>, /* uart3_txd */ 193 <K1_PADCONF(54, 4)>; /* uart3_rxd */ 194 bias-pull-up = <0>; 195 drive-strength = <32>; 196 }; 197 }; 198 199 /omit-if-no-ref/ 200 uart3_2_cts_rts_cfg: uart3-2-cts-rts-cfg { 201 uart3-2-pins { 202 pinmux = <K1_PADCONF(55, 4)>, /* uart3_cts */ 203 <K1_PADCONF(56, 4)>; /* uart3_rts */ 204 bias-pull-up = <0>; 205 drive-strength = <32>; 206 }; 207 }; 208 209 /omit-if-no-ref/ 210 uart4_0_cfg: uart4-0-cfg { 211 uart4-0-pins { 212 pinmux = <K1_PADCONF(100, 4)>, /* uart4_txd */ 213 <K1_PADCONF(101, 4)>; /* uart4_rxd */ 214 power-source = <3300>; 215 bias-pull-up = <0>; 216 drive-strength = <19>; 217 }; 218 }; 219 220 /omit-if-no-ref/ 221 uart4_1_cfg: uart4-1-cfg { 222 uart4-1-pins { 223 pinmux = <K1_PADCONF(83, 3)>, /* uart4_txd */ 224 <K1_PADCONF(84, 3)>; /* uart4_rxd */ 225 bias-pull-up = <0>; 226 drive-strength = <32>; 227 }; 228 }; 229 230 /omit-if-no-ref/ 231 uart4_1_cts_rts_cfg: uart4-1-cts-rts-cfg { 232 uart4-1-pins { 233 pinmux = <K1_PADCONF(81, 3)>, /* uart4_cts */ 234 <K1_PADCONF(82, 3)>; /* uart4_rts */ 235 bias-pull-up = <0>; 236 drive-strength = <32>; 237 }; 238 }; 239 240 /omit-if-no-ref/ 241 uart4_2_cfg: uart4-2-cfg { 242 uart4-2-pins { 243 pinmux = <K1_PADCONF(23, 2)>, /* uart4_txd */ 244 <K1_PADCONF(24, 2)>; /* uart4_rxd */ 245 bias-pull-up = <0>; 246 drive-strength = <32>; 247 }; 248 }; 249 250 /omit-if-no-ref/ 251 uart4_3_cfg: uart4-3-cfg { 252 uart4-3-pins { 253 pinmux = <K1_PADCONF(33, 2)>, /* uart4_txd */ 254 <K1_PADCONF(34, 2)>; /* uart4_rxd */ 255 bias-pull-up = <0>; 256 drive-strength = <32>; 257 }; 258 }; 259 260 /omit-if-no-ref/ 261 uart4_3_cts_rts_cfg: uart4-3-cts-rts-cfg { 262 uart4-3-pins { 263 pinmux = <K1_PADCONF(35, 2)>, /* uart4_cts */ 264 <K1_PADCONF(36, 2)>; /* uart4_rts */ 265 bias-pull-up = <0>; 266 drive-strength = <32>; 267 }; 268 }; 269 270 /omit-if-no-ref/ 271 uart4_4_cfg: uart4-4-cfg { 272 uart4-4-pins { 273 pinmux = <K1_PADCONF(111, 4)>, /* uart4_txd */ 274 <K1_PADCONF(112, 4)>; /* uart4_rxd */ 275 bias-pull-up = <0>; 276 drive-strength = <32>; 277 }; 278 }; 279 280 /omit-if-no-ref/ 281 uart4_4_cts_rts_cfg: uart4-4-cts-rts-cfg { 282 uart4-4-pins { 283 pinmux = <K1_PADCONF(113, 4)>, /* uart4_cts */ 284 <K1_PADCONF(114, 4)>; /* uart4_rts */ 285 bias-pull-up = <0>; 286 drive-strength = <32>; 287 }; 288 }; 289 290 /omit-if-no-ref/ 291 uart5_0_cfg: uart5-0-cfg { 292 uart5-0-pins { 293 pinmux = <K1_PADCONF(102, 3)>, /* uart5_txd */ 294 <K1_PADCONF(103, 3)>; /* uart5_rxd */ 295 power-source = <3300>; 296 bias-pull-up = <0>; 297 drive-strength = <19>; 298 }; 299 }; 300 301 /omit-if-no-ref/ 302 uart5_1_cfg: uart5-1-cfg { 303 uart5-1-pins { 304 pinmux = <K1_PADCONF(25, 2)>, /* uart5_txd */ 305 <K1_PADCONF(26, 2)>; /* uart5_rxd */ 306 bias-pull-up = <0>; 307 drive-strength = <32>; 308 }; 309 }; 310 311 /omit-if-no-ref/ 312 uart5_1_cts_rts_cfg: uart5-1-cts-rts-cfg { 313 uart5-1-pins { 314 pinmux = <K1_PADCONF(27, 2)>, /* uart5_cts */ 315 <K1_PADCONF(28, 2)>; /* uart5_rts */ 316 bias-pull-up = <0>; 317 drive-strength = <32>; 318 }; 319 }; 320 321 /omit-if-no-ref/ 322 uart5_2_cfg: uart5-2-cfg { 323 uart5-2-pins { 324 pinmux = <K1_PADCONF(42, 2)>, /* uart5_txd */ 325 <K1_PADCONF(43, 2)>; /* uart5_rxd */ 326 bias-pull-up = <0>; 327 drive-strength = <32>; 328 }; 329 }; 330 331 /omit-if-no-ref/ 332 uart5_2_cts_rts_cfg: uart5-2-cts-rts-cfg { 333 uart5-2-pins { 334 pinmux = <K1_PADCONF(44, 2)>, /* uart5_cts */ 335 <K1_PADCONF(45, 2)>; /* uart5_rts */ 336 bias-pull-up = <0>; 337 drive-strength = <32>; 338 }; 339 }; 340 341 /omit-if-no-ref/ 342 uart5_3_cfg: uart5-3-cfg { 343 uart5-3-pins { 344 pinmux = <K1_PADCONF(70, 4)>, /* uart5_txd */ 345 <K1_PADCONF(71, 4)>; /* uart5_rxd */ 346 bias-pull-up = <0>; 347 drive-strength = <32>; 348 }; 349 }; 350 351 /omit-if-no-ref/ 352 uart5_3_cts_rts_cfg: uart5-3-cts-rts-cfg { 353 uart5-3-pins { 354 pinmux = <K1_PADCONF(72, 4)>, /* uart5_cts */ 355 <K1_PADCONF(73, 4)>; /* uart5_rts */ 356 bias-pull-up = <0>; 357 drive-strength = <32>; 358 }; 359 }; 360 361 /omit-if-no-ref/ 362 uart6_0_cfg: uart6-0-cfg { 363 uart6-0-pins { 364 pinmux = <K1_PADCONF(86, 2)>, /* uart6_txd */ 365 <K1_PADCONF(87, 2)>; /* uart6_rxd */ 366 bias-pull-up = <0>; 367 drive-strength = <32>; 368 }; 369 }; 370 371 /omit-if-no-ref/ 372 uart6_0_cts_rts_cfg: uart6-0-cts-rts-cfg { 373 uart6-0-pins { 374 pinmux = <K1_PADCONF(85, 2)>, /* uart6_cts */ 375 <K1_PADCONF(90, 2)>; /* uart6_rts */ 376 bias-pull-up = <0>; 377 drive-strength = <32>; 378 }; 379 }; 380 381 /omit-if-no-ref/ 382 uart6_1_cfg: uart6-1-cfg { 383 uart6-1-pins { 384 pinmux = <K1_PADCONF(0, 2)>, /* uart6_txd */ 385 <K1_PADCONF(1, 2)>; /* uart6_rxd */ 386 bias-pull-up = <0>; 387 drive-strength = <32>; 388 }; 389 }; 390 391 /omit-if-no-ref/ 392 uart6_1_cts_rts_cfg: uart6-1-cts-rts-cfg { 393 uart6-1-pins { 394 pinmux = <K1_PADCONF(2, 2)>, /* uart6_cts */ 395 <K1_PADCONF(3, 2)>; /* uart6_rts */ 396 bias-pull-up = <0>; 397 drive-strength = <32>; 398 }; 399 }; 400 401 /omit-if-no-ref/ 402 uart6_2_cfg: uart6-2-cfg { 403 uart6-2-pins { 404 pinmux = <K1_PADCONF(56, 2)>, /* uart6_txd */ 405 <K1_PADCONF(57, 2)>; /* uart6_rxd */ 406 bias-pull-up = <0>; 407 drive-strength = <32>; 408 }; 409 }; 410 411 /omit-if-no-ref/ 412 uart7_0_cfg: uart7-0-cfg { 413 uart7-0-pins { 414 pinmux = <K1_PADCONF(88, 2)>, /* uart7_txd */ 415 <K1_PADCONF(89, 2)>; /* uart7_rxd */ 416 bias-pull-up = <0>; 417 drive-strength = <32>; 418 }; 419 }; 420 421 /omit-if-no-ref/ 422 uart7_1_cfg: uart7-1-cfg { 423 uart7-1-pins { 424 pinmux = <K1_PADCONF(4, 2)>, /* uart7_txd */ 425 <K1_PADCONF(5, 2)>; /* uart7_rxd */ 426 bias-pull-up = <0>; 427 drive-strength = <32>; 428 }; 429 }; 430 431 /omit-if-no-ref/ 432 uart7_1_cts_rts_cfg: uart7-1-cts-rts-cfg { 433 uart7-1-pins { 434 pinmux = <K1_PADCONF(6, 2)>, /* uart7_cts */ 435 <K1_PADCONF(7, 2)>; /* uart7_rts */ 436 bias-pull-up = <0>; 437 drive-strength = <32>; 438 }; 439 }; 440 441 /omit-if-no-ref/ 442 uart8_0_cfg: uart8-0-cfg { 443 uart8-0-pins { 444 pinmux = <K1_PADCONF(82, 4)>, /* uart8_txd */ 445 <K1_PADCONF(83, 4)>; /* uart8_rxd */ 446 bias-pull-up = <0>; 447 drive-strength = <32>; 448 }; 449 }; 450 451 /omit-if-no-ref/ 452 uart8_1_cfg: uart8-1-cfg { 453 uart8-1-pins { 454 pinmux = <K1_PADCONF(8, 2)>, /* uart8_txd */ 455 <K1_PADCONF(9, 2)>; /* uart8_rxd */ 456 bias-pull-up = <0>; 457 drive-strength = <32>; 458 }; 459 }; 460 461 /omit-if-no-ref/ 462 uart8_1_cts_rts_cfg: uart8-1-cts-rts-cfg { 463 uart8-1-pins { 464 pinmux = <K1_PADCONF(10, 2)>, /* uart8_cts */ 465 <K1_PADCONF(11, 2)>; /* uart8_rts */ 466 bias-pull-up = <0>; 467 drive-strength = <32>; 468 }; 469 }; 470 471 /omit-if-no-ref/ 472 uart8_2_cfg: uart8-2-cfg { 473 uart8-2-pins { 474 pinmux = <K1_PADCONF(75, 4)>, /* uart8_txd */ 475 <K1_PADCONF(76, 4)>; /* uart8_rxd */ 476 power-source = <3300>; 477 bias-pull-up = <0>; 478 drive-strength = <19>; 479 }; 480 }; 481 482 /omit-if-no-ref/ 483 uart8_2_cts_rts_cfg: uart8-2-cts-rts-cfg { 484 uart8-2-pins { 485 pinmux = <K1_PADCONF(77, 4)>, /* uart8_cts */ 486 <K1_PADCONF(78, 4)>; /* uart8_rts */ 487 power-source = <3300>; 488 bias-pull-up = <0>; 489 drive-strength = <19>; 490 }; 491 }; 492 493 /omit-if-no-ref/ 494 uart9_0_cfg: uart9-0-cfg { 495 uart9-0-pins { 496 pinmux = <K1_PADCONF(12, 2)>, /* uart9_txd */ 497 <K1_PADCONF(13, 2)>; /* uart9_rxd */ 498 bias-pull-up = <0>; 499 drive-strength = <32>; 500 }; 501 }; 502 503 /omit-if-no-ref/ 504 uart9_1_cfg: uart9-1-cfg { 505 uart9-1-pins { 506 pinmux = <K1_PADCONF(116, 3)>, /* uart9_txd */ 507 <K1_PADCONF(117, 3)>; /* uart9_rxd */ 508 bias-pull-up = <0>; 509 drive-strength = <32>; 510 }; 511 }; 512 513 /omit-if-no-ref/ 514 uart9_1_cts_rts_cfg: uart9-1-cts-rts-cfg { 515 uart9-1-pins { 516 pinmux = <K1_PADCONF(110, 3)>, /* uart9_cts */ 517 <K1_PADCONF(115, 3)>; /* uart9_rts */ 518 bias-pull-up = <0>; 519 drive-strength = <32>; 520 }; 521 }; 522 523 /omit-if-no-ref/ 524 uart9_2_cfg: uart9-2-cfg { 525 uart9-2-pins { 526 pinmux = <K1_PADCONF(72, 2)>, /* uart9_txd */ 527 <K1_PADCONF(73, 2)>; /* uart9_rxd */ 528 bias-pull-up = <0>; 529 drive-strength = <32>; 530 }; 531 }; 532 533 pwm14_1_cfg: pwm14-1-cfg { 534 pwm14-1-pins { 535 pinmux = <K1_PADCONF(44, 4)>; 536 bias-pull-up = <0>; 537 drive-strength = <32>; 538 }; 539 }; 540}; 541