1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2020 Microsemi Corporation 4 */ 5 6/ { 7 #address-cells = <1>; 8 #size-cells = <1>; 9 compatible = "mscc,jr2"; 10 11 aliases { 12 serial0 = &uart0; 13 serial1 = &uart2; 14 gpio0 = &gpio; 15 }; 16 17 cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 21 cpu@0 { 22 compatible = "mips,mips24KEc"; 23 device_type = "cpu"; 24 clocks = <&cpu_clk>; 25 reg = <0>; 26 }; 27 }; 28 29 cpuintc: interrupt-controller { 30 #address-cells = <0>; 31 #interrupt-cells = <1>; 32 interrupt-controller; 33 compatible = "mti,cpu-interrupt-controller"; 34 }; 35 36 cpu_clk: cpu-clock { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 clock-frequency = <500000000>; 40 }; 41 42 ahb_clk: ahb-clk { 43 compatible = "fixed-factor-clock"; 44 #clock-cells = <0>; 45 clocks = <&cpu_clk>; 46 clock-div = <2>; 47 clock-mult = <1>; 48 }; 49 50 ahb: ahb { 51 compatible = "simple-bus"; 52 #address-cells = <1>; 53 #size-cells = <1>; 54 ranges; 55 56 interrupt-parent = <&intc>; 57 58 cpu_ctrl: syscon@70000000 { 59 compatible = "mscc,ocelot-cpu-syscon", "syscon"; 60 reg = <0x70000000 0x2c>; 61 }; 62 63 intc: interrupt-controller@70000070 { 64 compatible = "mscc,jaguar2-icpu-intr"; 65 reg = <0x70000070 0x94>; 66 #interrupt-cells = <1>; 67 interrupt-controller; 68 interrupt-parent = <&cpuintc>; 69 interrupts = <2>; 70 }; 71 72 uart0: serial@70100000 { 73 pinctrl-0 = <&uart_pins>; 74 pinctrl-names = "default"; 75 compatible = "ns16550a"; 76 reg = <0x70100000 0x20>; 77 interrupts = <6>; 78 clocks = <&ahb_clk>; 79 reg-io-width = <4>; 80 reg-shift = <2>; 81 82 status = "disabled"; 83 }; 84 85 uart2: serial@70100800 { 86 pinctrl-0 = <&uart2_pins>; 87 pinctrl-names = "default"; 88 compatible = "ns16550a"; 89 reg = <0x70100800 0x20>; 90 interrupts = <7>; 91 clocks = <&ahb_clk>; 92 reg-io-width = <4>; 93 reg-shift = <2>; 94 95 status = "disabled"; 96 }; 97 98 gpio: pinctrl@71010038 { 99 compatible = "mscc,jaguar2-pinctrl"; 100 reg = <0x71010038 0x90>; 101 gpio-controller; 102 #gpio-cells = <2>; 103 gpio-ranges = <&gpio 0 0 64>; 104 105 uart_pins: uart-pins { 106 pins = "GPIO_10", "GPIO_11"; 107 function = "uart"; 108 }; 109 110 uart2_pins: uart2-pins { 111 pins = "GPIO_24", "GPIO_25"; 112 function = "uart2"; 113 }; 114 115 cs1_pins: cs1-pins { 116 pins = "GPIO_16"; 117 function = "si"; 118 }; 119 120 cs2_pins: cs2-pins { 121 pins = "GPIO_17"; 122 function = "si"; 123 }; 124 125 cs3_pins: cs3-pins { 126 pins = "GPIO_18"; 127 function = "si"; 128 }; 129 130 i2c_pins: i2c-pins { 131 pins = "GPIO_14", "GPIO_15"; 132 function = "twi"; 133 }; 134 135 i2c2_pins: i2c2-pins { 136 pins = "GPIO_28", "GPIO_29"; 137 function = "twi2"; 138 }; 139 }; 140 141 i2c0: i2c@70100400 { 142 compatible = "mscc,ocelot-i2c", "snps,designware-i2c"; 143 status = "disabled"; 144 pinctrl-0 = <&i2c_pins>; 145 pinctrl-names = "default"; 146 reg = <0x70100400 0x100>, <0x700001b8 0x8>; 147 #address-cells = <1>; 148 #size-cells = <0>; 149 interrupts = <8>; 150 clock-frequency = <100000>; 151 clocks = <&ahb_clk>; 152 }; 153 154 i2c2: i2c@70100c00 { 155 compatible = "mscc,ocelot-i2c", "snps,designware-i2c"; 156 status = "disabled"; 157 pinctrl-0 = <&i2c2_pins>; 158 pinctrl-names = "default"; 159 reg = <0x70100c00 0x100>; 160 #address-cells = <1>; 161 #size-cells = <0>; 162 interrupts = <8>; 163 clock-frequency = <100000>; 164 clocks = <&ahb_clk>; 165 }; 166 }; 167}; 168