1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * IPQ9574 SoC device tree source 4 * 5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. 6 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. 7 */ 8 9#include <dt-bindings/clock/qcom,apss-ipq.h> 10#include <dt-bindings/clock/qcom,ipq9574-gcc.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/reset/qcom,ipq9574-gcc.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 interrupt-parent = <&intc>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 clocks { 21 sleep_clk: sleep-clk { 22 compatible = "fixed-clock"; 23 #clock-cells = <0>; 24 }; 25 26 xo_board_clk: xo-board-clk { 27 compatible = "fixed-clock"; 28 #clock-cells = <0>; 29 }; 30 }; 31 32 cpus { 33 #address-cells = <1>; 34 #size-cells = <0>; 35 36 CPU0: cpu@0 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-a73"; 39 reg = <0x0>; 40 enable-method = "psci"; 41 next-level-cache = <&L2_0>; 42 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 43 clock-names = "cpu"; 44 operating-points-v2 = <&cpu_opp_table>; 45 cpu-supply = <&ipq9574_s1>; 46 #cooling-cells = <2>; 47 }; 48 49 CPU1: cpu@1 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a73"; 52 reg = <0x1>; 53 enable-method = "psci"; 54 next-level-cache = <&L2_0>; 55 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 56 clock-names = "cpu"; 57 operating-points-v2 = <&cpu_opp_table>; 58 cpu-supply = <&ipq9574_s1>; 59 #cooling-cells = <2>; 60 }; 61 62 CPU2: cpu@2 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a73"; 65 reg = <0x2>; 66 enable-method = "psci"; 67 next-level-cache = <&L2_0>; 68 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 69 clock-names = "cpu"; 70 operating-points-v2 = <&cpu_opp_table>; 71 cpu-supply = <&ipq9574_s1>; 72 #cooling-cells = <2>; 73 }; 74 75 CPU3: cpu@3 { 76 device_type = "cpu"; 77 compatible = "arm,cortex-a73"; 78 reg = <0x3>; 79 enable-method = "psci"; 80 next-level-cache = <&L2_0>; 81 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 82 clock-names = "cpu"; 83 operating-points-v2 = <&cpu_opp_table>; 84 cpu-supply = <&ipq9574_s1>; 85 #cooling-cells = <2>; 86 }; 87 88 L2_0: l2-cache { 89 compatible = "cache"; 90 cache-level = <2>; 91 cache-unified; 92 }; 93 }; 94 95 firmware { 96 scm { 97 compatible = "qcom,scm-ipq9574", "qcom,scm"; 98 qcom,dload-mode = <&tcsr 0x6100>; 99 }; 100 }; 101 102 memory@40000000 { 103 device_type = "memory"; 104 /* We expect the bootloader to fill in the size */ 105 reg = <0x0 0x40000000 0x0 0x0>; 106 }; 107 108 cpu_opp_table: opp-table-cpu { 109 compatible = "operating-points-v2-kryo-cpu"; 110 opp-shared; 111 nvmem-cells = <&cpu_speed_bin>; 112 113 opp-936000000 { 114 opp-hz = /bits/ 64 <936000000>; 115 opp-microvolt = <725000>; 116 opp-supported-hw = <0xf>; 117 clock-latency-ns = <200000>; 118 }; 119 120 opp-1104000000 { 121 opp-hz = /bits/ 64 <1104000000>; 122 opp-microvolt = <787500>; 123 opp-supported-hw = <0xf>; 124 clock-latency-ns = <200000>; 125 }; 126 127 opp-1200000000 { 128 opp-hz = /bits/ 64 <1200000000>; 129 opp-microvolt = <862500>; 130 opp-supported-hw = <0xf>; 131 clock-latency-ns = <200000>; 132 }; 133 134 opp-1416000000 { 135 opp-hz = /bits/ 64 <1416000000>; 136 opp-microvolt = <862500>; 137 opp-supported-hw = <0x7>; 138 clock-latency-ns = <200000>; 139 }; 140 141 opp-1488000000 { 142 opp-hz = /bits/ 64 <1488000000>; 143 opp-microvolt = <925000>; 144 opp-supported-hw = <0x7>; 145 clock-latency-ns = <200000>; 146 }; 147 148 opp-1800000000 { 149 opp-hz = /bits/ 64 <1800000000>; 150 opp-microvolt = <987500>; 151 opp-supported-hw = <0x5>; 152 clock-latency-ns = <200000>; 153 }; 154 155 opp-2208000000 { 156 opp-hz = /bits/ 64 <2208000000>; 157 opp-microvolt = <1062500>; 158 opp-supported-hw = <0x1>; 159 clock-latency-ns = <200000>; 160 }; 161 }; 162 163 pmu { 164 compatible = "arm,cortex-a73-pmu"; 165 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 166 }; 167 168 psci { 169 compatible = "arm,psci-1.0"; 170 method = "smc"; 171 }; 172 173 rpm: remoteproc { 174 compatible = "qcom,ipq9574-rpm-proc", "qcom,rpm-proc"; 175 176 glink-edge { 177 compatible = "qcom,glink-rpm"; 178 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 179 qcom,rpm-msg-ram = <&rpm_msg_ram>; 180 mboxes = <&apcs_glb 0>; 181 182 rpm_requests: rpm-requests { 183 compatible = "qcom,rpm-ipq9574"; 184 qcom,glink-channels = "rpm_requests"; 185 }; 186 }; 187 }; 188 189 reserved-memory { 190 #address-cells = <2>; 191 #size-cells = <2>; 192 ranges; 193 194 bootloader@4a100000 { 195 reg = <0x0 0x4a100000 0x0 0x400000>; 196 no-map; 197 }; 198 199 sbl@4a500000 { 200 reg = <0x0 0x4a500000 0x0 0x100000>; 201 no-map; 202 }; 203 204 tz_region: tz@4a600000 { 205 reg = <0x0 0x4a600000 0x0 0x400000>; 206 no-map; 207 }; 208 209 smem@4aa00000 { 210 compatible = "qcom,smem"; 211 reg = <0x0 0x4aa00000 0x0 0x100000>; 212 hwlocks = <&tcsr_mutex 3>; 213 no-map; 214 }; 215 }; 216 217 soc: soc@0 { 218 compatible = "simple-bus"; 219 #address-cells = <1>; 220 #size-cells = <1>; 221 ranges = <0 0 0 0xffffffff>; 222 223 rpm_msg_ram: sram@60000 { 224 compatible = "qcom,rpm-msg-ram"; 225 reg = <0x00060000 0x6000>; 226 }; 227 228 rng: rng@e3000 { 229 compatible = "qcom,prng-ee"; 230 reg = <0x000e3000 0x1000>; 231 clocks = <&gcc GCC_PRNG_AHB_CLK>; 232 clock-names = "core"; 233 }; 234 235 qfprom: efuse@a4000 { 236 compatible = "qcom,ipq9574-qfprom", "qcom,qfprom"; 237 reg = <0x000a4000 0x5a1>; 238 #address-cells = <1>; 239 #size-cells = <1>; 240 241 cpu_speed_bin: cpu-speed-bin@15 { 242 reg = <0x15 0x2>; 243 bits = <7 2>; 244 }; 245 }; 246 247 cryptobam: dma-controller@704000 { 248 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 249 reg = <0x00704000 0x20000>; 250 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 251 #dma-cells = <1>; 252 qcom,ee = <1>; 253 qcom,controlled-remotely; 254 }; 255 256 crypto: crypto@73a000 { 257 compatible = "qcom,ipq9574-qce", "qcom,ipq4019-qce", "qcom,qce"; 258 reg = <0x0073a000 0x6000>; 259 clocks = <&gcc GCC_CRYPTO_AHB_CLK>, 260 <&gcc GCC_CRYPTO_AXI_CLK>, 261 <&gcc GCC_CRYPTO_CLK>; 262 clock-names = "iface", "bus", "core"; 263 dmas = <&cryptobam 2>, <&cryptobam 3>; 264 dma-names = "rx", "tx"; 265 }; 266 267 tsens: thermal-sensor@4a9000 { 268 compatible = "qcom,ipq9574-tsens", "qcom,ipq8074-tsens"; 269 reg = <0x004a9000 0x1000>, 270 <0x004a8000 0x1000>; 271 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 272 interrupt-names = "combined"; 273 #qcom,sensors = <16>; 274 #thermal-sensor-cells = <1>; 275 }; 276 277 tlmm: pinctrl@1000000 { 278 compatible = "qcom,ipq9574-tlmm"; 279 reg = <0x01000000 0x300000>; 280 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 281 gpio-controller; 282 #gpio-cells = <2>; 283 gpio-ranges = <&tlmm 0 0 65>; 284 interrupt-controller; 285 #interrupt-cells = <2>; 286 287 uart2_pins: uart2-state { 288 pins = "gpio34", "gpio35"; 289 function = "blsp2_uart"; 290 drive-strength = <8>; 291 bias-disable; 292 }; 293 }; 294 295 gcc: clock-controller@1800000 { 296 compatible = "qcom,ipq9574-gcc"; 297 reg = <0x01800000 0x80000>; 298 clocks = <&xo_board_clk>, 299 <&sleep_clk>, 300 <0>, 301 <0>, 302 <0>, 303 <0>, 304 <0>, 305 <0>; 306 #clock-cells = <1>; 307 #reset-cells = <1>; 308 #power-domain-cells = <1>; 309 }; 310 311 tcsr_mutex: hwlock@1905000 { 312 compatible = "qcom,tcsr-mutex"; 313 reg = <0x01905000 0x20000>; 314 #hwlock-cells = <1>; 315 }; 316 317 tcsr: syscon@1937000 { 318 compatible = "qcom,tcsr-ipq9574", "syscon"; 319 reg = <0x01937000 0x21000>; 320 }; 321 322 sdhc_1: mmc@7804000 { 323 compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5"; 324 reg = <0x07804000 0x1000>, <0x07805000 0x1000>; 325 reg-names = "hc", "cqhci"; 326 327 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 328 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 329 interrupt-names = "hc_irq", "pwr_irq"; 330 331 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 332 <&gcc GCC_SDCC1_APPS_CLK>, 333 <&xo_board_clk>; 334 clock-names = "iface", "core", "xo"; 335 non-removable; 336 status = "disabled"; 337 }; 338 339 blsp_dma: dma-controller@7884000 { 340 compatible = "qcom,bam-v1.7.0"; 341 reg = <0x07884000 0x2b000>; 342 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 343 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 344 clock-names = "bam_clk"; 345 #dma-cells = <1>; 346 qcom,ee = <0>; 347 }; 348 349 blsp1_uart0: serial@78af000 { 350 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 351 reg = <0x078af000 0x200>; 352 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 353 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 354 <&gcc GCC_BLSP1_AHB_CLK>; 355 clock-names = "core", "iface"; 356 status = "disabled"; 357 }; 358 359 blsp1_uart1: serial@78b0000 { 360 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 361 reg = <0x078b0000 0x200>; 362 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 363 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 364 <&gcc GCC_BLSP1_AHB_CLK>; 365 clock-names = "core", "iface"; 366 status = "disabled"; 367 }; 368 369 blsp1_uart2: serial@78b1000 { 370 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 371 reg = <0x078b1000 0x200>; 372 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 373 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 374 <&gcc GCC_BLSP1_AHB_CLK>; 375 clock-names = "core", "iface"; 376 status = "disabled"; 377 }; 378 379 blsp1_uart3: serial@78b2000 { 380 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 381 reg = <0x078b2000 0x200>; 382 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 383 clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, 384 <&gcc GCC_BLSP1_AHB_CLK>; 385 clock-names = "core", "iface"; 386 status = "disabled"; 387 }; 388 389 blsp1_uart4: serial@78b3000 { 390 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 391 reg = <0x078b3000 0x200>; 392 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 393 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, 394 <&gcc GCC_BLSP1_AHB_CLK>; 395 clock-names = "core", "iface"; 396 status = "disabled"; 397 }; 398 399 blsp1_uart5: serial@78b4000 { 400 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 401 reg = <0x078b4000 0x200>; 402 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 403 clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>, 404 <&gcc GCC_BLSP1_AHB_CLK>; 405 clock-names = "core", "iface"; 406 status = "disabled"; 407 }; 408 409 blsp1_spi0: spi@78b5000 { 410 compatible = "qcom,spi-qup-v2.2.1"; 411 reg = <0x078b5000 0x600>; 412 #address-cells = <1>; 413 #size-cells = <0>; 414 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 415 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 416 <&gcc GCC_BLSP1_AHB_CLK>; 417 clock-names = "core", "iface"; 418 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 419 dma-names = "tx", "rx"; 420 status = "disabled"; 421 }; 422 423 blsp1_i2c1: i2c@78b6000 { 424 compatible = "qcom,i2c-qup-v2.2.1"; 425 reg = <0x078b6000 0x600>; 426 #address-cells = <1>; 427 #size-cells = <0>; 428 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 429 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 430 <&gcc GCC_BLSP1_AHB_CLK>; 431 clock-names = "core", "iface"; 432 assigned-clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; 433 assigned-clock-rates = <50000000>; 434 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 435 dma-names = "tx", "rx"; 436 status = "disabled"; 437 }; 438 439 blsp1_spi1: spi@78b6000 { 440 compatible = "qcom,spi-qup-v2.2.1"; 441 reg = <0x078b6000 0x600>; 442 #address-cells = <1>; 443 #size-cells = <0>; 444 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 445 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 446 <&gcc GCC_BLSP1_AHB_CLK>; 447 clock-names = "core", "iface"; 448 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 449 dma-names = "tx", "rx"; 450 status = "disabled"; 451 }; 452 453 blsp1_i2c2: i2c@78b7000 { 454 compatible = "qcom,i2c-qup-v2.2.1"; 455 reg = <0x078b7000 0x600>; 456 #address-cells = <1>; 457 #size-cells = <0>; 458 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 459 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 460 <&gcc GCC_BLSP1_AHB_CLK>; 461 clock-names = "core", "iface"; 462 assigned-clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; 463 assigned-clock-rates = <50000000>; 464 dmas = <&blsp_dma 16>, <&blsp_dma 17>; 465 dma-names = "tx", "rx"; 466 status = "disabled"; 467 }; 468 469 blsp1_spi2: spi@78b7000 { 470 compatible = "qcom,spi-qup-v2.2.1"; 471 reg = <0x078b7000 0x600>; 472 #address-cells = <1>; 473 #size-cells = <0>; 474 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 475 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 476 <&gcc GCC_BLSP1_AHB_CLK>; 477 clock-names = "core", "iface"; 478 dmas = <&blsp_dma 16>, <&blsp_dma 17>; 479 dma-names = "tx", "rx"; 480 status = "disabled"; 481 }; 482 483 blsp1_i2c3: i2c@78b8000 { 484 compatible = "qcom,i2c-qup-v2.2.1"; 485 reg = <0x078b8000 0x600>; 486 #address-cells = <1>; 487 #size-cells = <0>; 488 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 489 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 490 <&gcc GCC_BLSP1_AHB_CLK>; 491 clock-names = "core", "iface"; 492 assigned-clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; 493 assigned-clock-rates = <50000000>; 494 dmas = <&blsp_dma 18>, <&blsp_dma 19>; 495 dma-names = "tx", "rx"; 496 status = "disabled"; 497 }; 498 499 blsp1_spi3: spi@78b8000 { 500 compatible = "qcom,spi-qup-v2.2.1"; 501 reg = <0x078b8000 0x600>; 502 #address-cells = <1>; 503 #size-cells = <0>; 504 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 505 spi-max-frequency = <50000000>; 506 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, 507 <&gcc GCC_BLSP1_AHB_CLK>; 508 clock-names = "core", "iface"; 509 dmas = <&blsp_dma 18>, <&blsp_dma 19>; 510 dma-names = "tx", "rx"; 511 status = "disabled"; 512 }; 513 514 blsp1_i2c4: i2c@78b9000 { 515 compatible = "qcom,i2c-qup-v2.2.1"; 516 reg = <0x078b9000 0x600>; 517 #address-cells = <1>; 518 #size-cells = <0>; 519 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 520 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 521 <&gcc GCC_BLSP1_AHB_CLK>; 522 clock-names = "core", "iface"; 523 assigned-clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>; 524 assigned-clock-rates = <50000000>; 525 dmas = <&blsp_dma 20>, <&blsp_dma 21>; 526 dma-names = "tx", "rx"; 527 status = "disabled"; 528 }; 529 530 blsp1_spi4: spi@78b9000 { 531 compatible = "qcom,spi-qup-v2.2.1"; 532 reg = <0x078b9000 0x600>; 533 #address-cells = <1>; 534 #size-cells = <0>; 535 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 536 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, 537 <&gcc GCC_BLSP1_AHB_CLK>; 538 clock-names = "core", "iface"; 539 dmas = <&blsp_dma 20>, <&blsp_dma 21>; 540 dma-names = "tx", "rx"; 541 status = "disabled"; 542 }; 543 544 usb_0_qusbphy: phy@7b000 { 545 compatible = "qcom,ipq9574-qusb2-phy"; 546 reg = <0x0007b000 0x180>; 547 #phy-cells = <0>; 548 549 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 550 <&xo_board_clk>; 551 clock-names = "cfg_ahb", 552 "ref"; 553 554 resets = <&gcc GCC_QUSB2_0_PHY_BCR>; 555 status = "disabled"; 556 }; 557 558 usb_0_qmpphy: phy@7d000 { 559 compatible = "qcom,ipq9574-qmp-usb3-phy"; 560 reg = <0x0007d000 0xa00>; 561 #phy-cells = <0>; 562 563 clocks = <&gcc GCC_USB0_AUX_CLK>, 564 <&xo_board_clk>, 565 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 566 <&gcc GCC_USB0_PIPE_CLK>; 567 clock-names = "aux", 568 "ref", 569 "cfg_ahb", 570 "pipe"; 571 572 resets = <&gcc GCC_USB0_PHY_BCR>, 573 <&gcc GCC_USB3PHY_0_PHY_BCR>; 574 reset-names = "phy", 575 "phy_phy"; 576 577 #clock-cells = <0>; 578 clock-output-names = "usb0_pipe_clk"; 579 580 status = "disabled"; 581 }; 582 583 usb3: usb@8af8800 { 584 compatible = "qcom,ipq9574-dwc3", "qcom,dwc3"; 585 reg = <0x08af8800 0x400>; 586 #address-cells = <1>; 587 #size-cells = <1>; 588 ranges; 589 590 clocks = <&gcc GCC_SNOC_USB_CLK>, 591 <&gcc GCC_USB0_MASTER_CLK>, 592 <&gcc GCC_ANOC_USB_AXI_CLK>, 593 <&gcc GCC_USB0_SLEEP_CLK>, 594 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 595 596 clock-names = "cfg_noc", 597 "core", 598 "iface", 599 "sleep", 600 "mock_utmi"; 601 602 assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>, 603 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 604 assigned-clock-rates = <200000000>, 605 <24000000>; 606 607 interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 608 interrupt-names = "pwr_event"; 609 610 resets = <&gcc GCC_USB_BCR>; 611 status = "disabled"; 612 613 usb_0_dwc3: usb@8a00000 { 614 compatible = "snps,dwc3"; 615 reg = <0x8a00000 0xcd00>; 616 clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>; 617 clock-names = "ref"; 618 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 619 phys = <&usb_0_qusbphy>, <&usb_0_qmpphy>; 620 phy-names = "usb2-phy", "usb3-phy"; 621 tx-fifo-resize; 622 snps,is-utmi-l1-suspend; 623 snps,hird-threshold = /bits/ 8 <0x0>; 624 snps,dis_u2_susphy_quirk; 625 snps,dis_u3_susphy_quirk; 626 }; 627 }; 628 629 intc: interrupt-controller@b000000 { 630 compatible = "qcom,msm-qgic2"; 631 reg = <0x0b000000 0x1000>, /* GICD */ 632 <0x0b002000 0x2000>, /* GICC */ 633 <0x0b001000 0x1000>, /* GICH */ 634 <0x0b004000 0x2000>; /* GICV */ 635 #address-cells = <1>; 636 #size-cells = <1>; 637 interrupt-controller; 638 #interrupt-cells = <3>; 639 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 640 ranges = <0 0x0b00c000 0x3000>; 641 642 v2m0: v2m@0 { 643 compatible = "arm,gic-v2m-frame"; 644 reg = <0x00000000 0xffd>; 645 msi-controller; 646 }; 647 648 v2m1: v2m@1000 { 649 compatible = "arm,gic-v2m-frame"; 650 reg = <0x00001000 0xffd>; 651 msi-controller; 652 }; 653 654 v2m2: v2m@2000 { 655 compatible = "arm,gic-v2m-frame"; 656 reg = <0x00002000 0xffd>; 657 msi-controller; 658 }; 659 }; 660 661 watchdog: watchdog@b017000 { 662 compatible = "qcom,apss-wdt-ipq9574", "qcom,kpss-wdt"; 663 reg = <0x0b017000 0x1000>; 664 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 665 clocks = <&sleep_clk>; 666 timeout-sec = <30>; 667 }; 668 669 apcs_glb: mailbox@b111000 { 670 compatible = "qcom,ipq9574-apcs-apps-global", 671 "qcom,ipq6018-apcs-apps-global"; 672 reg = <0x0b111000 0x1000>; 673 #clock-cells = <1>; 674 clocks = <&a73pll>, <&xo_board_clk>, <&gcc GPLL0>; 675 clock-names = "pll", "xo", "gpll0"; 676 #mbox-cells = <1>; 677 }; 678 679 a73pll: clock@b116000 { 680 compatible = "qcom,ipq9574-a73pll"; 681 reg = <0x0b116000 0x40>; 682 #clock-cells = <0>; 683 clocks = <&xo_board_clk>; 684 clock-names = "xo"; 685 }; 686 687 timer@b120000 { 688 compatible = "arm,armv7-timer-mem"; 689 reg = <0x0b120000 0x1000>; 690 #address-cells = <1>; 691 #size-cells = <1>; 692 ranges; 693 694 frame@b120000 { 695 reg = <0x0b121000 0x1000>, 696 <0x0b122000 0x1000>; 697 frame-number = <0>; 698 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 699 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 700 }; 701 702 frame@b123000 { 703 reg = <0x0b123000 0x1000>; 704 frame-number = <1>; 705 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 706 status = "disabled"; 707 }; 708 709 frame@b124000 { 710 reg = <0x0b124000 0x1000>; 711 frame-number = <2>; 712 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 713 status = "disabled"; 714 }; 715 716 frame@b125000 { 717 reg = <0x0b125000 0x1000>; 718 frame-number = <3>; 719 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 720 status = "disabled"; 721 }; 722 723 frame@b126000 { 724 reg = <0x0b126000 0x1000>; 725 frame-number = <4>; 726 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 727 status = "disabled"; 728 }; 729 730 frame@b127000 { 731 reg = <0x0b127000 0x1000>; 732 frame-number = <5>; 733 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 734 status = "disabled"; 735 }; 736 737 frame@b128000 { 738 reg = <0x0b128000 0x1000>; 739 frame-number = <6>; 740 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 741 status = "disabled"; 742 }; 743 }; 744 }; 745 746 thermal-zones { 747 nss-top-thermal { 748 polling-delay-passive = <0>; 749 polling-delay = <0>; 750 thermal-sensors = <&tsens 3>; 751 752 trips { 753 nss-top-critical { 754 temperature = <125000>; 755 hysteresis = <1000>; 756 type = "critical"; 757 }; 758 }; 759 }; 760 761 ubi-0-thermal { 762 polling-delay-passive = <0>; 763 polling-delay = <0>; 764 thermal-sensors = <&tsens 4>; 765 766 trips { 767 ubi_0-critical { 768 temperature = <125000>; 769 hysteresis = <1000>; 770 type = "critical"; 771 }; 772 }; 773 }; 774 775 ubi-1-thermal { 776 polling-delay-passive = <0>; 777 polling-delay = <0>; 778 thermal-sensors = <&tsens 5>; 779 780 trips { 781 ubi_1-critical { 782 temperature = <125000>; 783 hysteresis = <1000>; 784 type = "critical"; 785 }; 786 }; 787 }; 788 789 ubi-2-thermal { 790 polling-delay-passive = <0>; 791 polling-delay = <0>; 792 thermal-sensors = <&tsens 6>; 793 794 trips { 795 ubi_2-critical { 796 temperature = <125000>; 797 hysteresis = <1000>; 798 type = "critical"; 799 }; 800 }; 801 }; 802 803 ubi-3-thermal { 804 polling-delay-passive = <0>; 805 polling-delay = <0>; 806 thermal-sensors = <&tsens 7>; 807 808 trips { 809 ubi_3-critical { 810 temperature = <125000>; 811 hysteresis = <1000>; 812 type = "critical"; 813 }; 814 }; 815 }; 816 817 cpuss0-thermal { 818 polling-delay-passive = <0>; 819 polling-delay = <0>; 820 thermal-sensors = <&tsens 8>; 821 822 trips { 823 cpu-critical { 824 temperature = <125000>; 825 hysteresis = <1000>; 826 type = "critical"; 827 }; 828 }; 829 }; 830 831 cpuss1-thermal { 832 polling-delay-passive = <0>; 833 polling-delay = <0>; 834 thermal-sensors = <&tsens 9>; 835 836 trips { 837 cpu-critical { 838 temperature = <125000>; 839 hysteresis = <1000>; 840 type = "critical"; 841 }; 842 }; 843 }; 844 845 cpu0-thermal { 846 polling-delay-passive = <0>; 847 polling-delay = <0>; 848 thermal-sensors = <&tsens 10>; 849 850 trips { 851 cpu0_crit: cpu-critical { 852 temperature = <120000>; 853 hysteresis = <10000>; 854 type = "critical"; 855 }; 856 857 cpu0_alert: cpu-passive { 858 temperature = <110000>; 859 hysteresis = <1000>; 860 type = "passive"; 861 }; 862 }; 863 864 cooling-maps { 865 map0 { 866 trip = <&cpu0_alert>; 867 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 868 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 869 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 870 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 871 }; 872 }; 873 }; 874 875 cpu1-thermal { 876 polling-delay-passive = <0>; 877 polling-delay = <0>; 878 thermal-sensors = <&tsens 11>; 879 880 trips { 881 cpu1_crit: cpu-critical { 882 temperature = <120000>; 883 hysteresis = <10000>; 884 type = "critical"; 885 }; 886 887 cpu1_alert: cpu-passive { 888 temperature = <110000>; 889 hysteresis = <1000>; 890 type = "passive"; 891 }; 892 }; 893 894 cooling-maps { 895 map0 { 896 trip = <&cpu1_alert>; 897 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 898 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 899 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 900 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 901 }; 902 }; 903 }; 904 905 cpu2-thermal { 906 polling-delay-passive = <0>; 907 polling-delay = <0>; 908 thermal-sensors = <&tsens 12>; 909 910 trips { 911 cpu2_crit: cpu-critical { 912 temperature = <120000>; 913 hysteresis = <10000>; 914 type = "critical"; 915 }; 916 917 cpu2_alert: cpu-passive { 918 temperature = <110000>; 919 hysteresis = <1000>; 920 type = "passive"; 921 }; 922 }; 923 924 cooling-maps { 925 map0 { 926 trip = <&cpu2_alert>; 927 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 928 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 929 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 930 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 931 }; 932 }; 933 }; 934 935 cpu3-thermal { 936 polling-delay-passive = <0>; 937 polling-delay = <0>; 938 thermal-sensors = <&tsens 13>; 939 940 trips { 941 cpu3_crit: cpu-critical { 942 temperature = <120000>; 943 hysteresis = <10000>; 944 type = "critical"; 945 }; 946 947 cpu3_alert: cpu-passive { 948 temperature = <110000>; 949 hysteresis = <1000>; 950 type = "passive"; 951 }; 952 }; 953 954 cooling-maps { 955 map0 { 956 trip = <&cpu3_alert>; 957 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 958 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 959 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 960 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 961 }; 962 }; 963 }; 964 965 wcss-phyb-thermal { 966 polling-delay-passive = <0>; 967 polling-delay = <0>; 968 thermal-sensors = <&tsens 14>; 969 970 trips { 971 wcss_phyb-critical { 972 temperature = <125000>; 973 hysteresis = <1000>; 974 type = "critical"; 975 }; 976 }; 977 }; 978 979 top-glue-thermal { 980 polling-delay-passive = <0>; 981 polling-delay = <0>; 982 thermal-sensors = <&tsens 15>; 983 984 trips { 985 top_glue-critical { 986 temperature = <125000>; 987 hysteresis = <1000>; 988 type = "critical"; 989 }; 990 }; 991 }; 992 }; 993 994 timer { 995 compatible = "arm,armv8-timer"; 996 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 997 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 998 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 999 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1000 }; 1001}; 1002