1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * IPQ5332 device tree source 4 * 5 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,apss-ipq.h> 9#include <dt-bindings/clock/qcom,ipq5332-gcc.h> 10#include <dt-bindings/interconnect/qcom,ipq5332.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12 13/ { 14 interrupt-parent = <&intc>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 clocks { 19 sleep_clk: sleep-clk { 20 compatible = "fixed-clock"; 21 #clock-cells = <0>; 22 }; 23 24 xo_board: xo-board-clk { 25 compatible = "fixed-clock"; 26 #clock-cells = <0>; 27 }; 28 }; 29 30 cpus { 31 #address-cells = <1>; 32 #size-cells = <0>; 33 34 cpu0: cpu@0 { 35 device_type = "cpu"; 36 compatible = "arm,cortex-a53"; 37 reg = <0x0>; 38 enable-method = "psci"; 39 next-level-cache = <&l2_0>; 40 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 41 operating-points-v2 = <&cpu_opp_table>; 42 }; 43 44 cpu1: cpu@1 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a53"; 47 reg = <0x1>; 48 enable-method = "psci"; 49 next-level-cache = <&l2_0>; 50 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 51 operating-points-v2 = <&cpu_opp_table>; 52 }; 53 54 cpu2: cpu@2 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a53"; 57 reg = <0x2>; 58 enable-method = "psci"; 59 next-level-cache = <&l2_0>; 60 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 61 operating-points-v2 = <&cpu_opp_table>; 62 }; 63 64 cpu3: cpu@3 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a53"; 67 reg = <0x3>; 68 enable-method = "psci"; 69 next-level-cache = <&l2_0>; 70 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 71 operating-points-v2 = <&cpu_opp_table>; 72 }; 73 74 l2_0: l2-cache { 75 compatible = "cache"; 76 cache-level = <2>; 77 cache-unified; 78 }; 79 }; 80 81 firmware { 82 scm { 83 compatible = "qcom,scm-ipq5332", "qcom,scm"; 84 qcom,dload-mode = <&tcsr 0x6100>; 85 }; 86 }; 87 88 memory@40000000 { 89 device_type = "memory"; 90 /* We expect the bootloader to fill in the size */ 91 reg = <0x0 0x40000000 0x0 0x0>; 92 }; 93 94 cpu_opp_table: opp-table-cpu { 95 compatible = "operating-points-v2-kryo-cpu"; 96 opp-shared; 97 nvmem-cells = <&cpu_speed_bin>; 98 99 opp-1100000000 { 100 opp-hz = /bits/ 64 <1100000000>; 101 opp-supported-hw = <0x7>; 102 clock-latency-ns = <200000>; 103 }; 104 105 opp-1500000000 { 106 opp-hz = /bits/ 64 <1500000000>; 107 opp-supported-hw = <0x3>; 108 clock-latency-ns = <200000>; 109 }; 110 }; 111 112 pmu { 113 compatible = "arm,cortex-a53-pmu"; 114 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 115 }; 116 117 psci { 118 compatible = "arm,psci-1.0"; 119 method = "smc"; 120 }; 121 122 reserved-memory { 123 #address-cells = <2>; 124 #size-cells = <2>; 125 ranges; 126 127 bootloader@4a100000 { 128 reg = <0x0 0x4a100000 0x0 0x400000>; 129 no-map; 130 }; 131 132 sbl@4a500000 { 133 reg = <0x0 0x4a500000 0x0 0x100000>; 134 no-map; 135 }; 136 137 tz_mem: tz@4a600000 { 138 reg = <0x0 0x4a600000 0x0 0x200000>; 139 no-map; 140 }; 141 142 smem@4a800000 { 143 compatible = "qcom,smem"; 144 reg = <0x0 0x4a800000 0x0 0x100000>; 145 no-map; 146 147 hwlocks = <&tcsr_mutex 3>; 148 }; 149 }; 150 151 soc@0 { 152 compatible = "simple-bus"; 153 #address-cells = <1>; 154 #size-cells = <1>; 155 ranges = <0 0 0 0xffffffff>; 156 157 usbphy0: phy@7b000 { 158 compatible = "qcom,ipq5332-usb-hsphy"; 159 reg = <0x0007b000 0x12c>; 160 161 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>; 162 163 resets = <&gcc GCC_QUSB2_0_PHY_BCR>; 164 165 #phy-cells = <0>; 166 167 status = "disabled"; 168 }; 169 170 qfprom: efuse@a4000 { 171 compatible = "qcom,ipq5332-qfprom", "qcom,qfprom"; 172 reg = <0x000a4000 0x721>; 173 #address-cells = <1>; 174 #size-cells = <1>; 175 176 cpu_speed_bin: cpu-speed-bin@1d { 177 reg = <0x1d 0x2>; 178 bits = <7 2>; 179 }; 180 }; 181 182 rng: rng@e3000 { 183 compatible = "qcom,prng-ee"; 184 reg = <0x000e3000 0x1000>; 185 clocks = <&gcc GCC_PRNG_AHB_CLK>; 186 clock-names = "core"; 187 }; 188 189 tlmm: pinctrl@1000000 { 190 compatible = "qcom,ipq5332-tlmm"; 191 reg = <0x01000000 0x300000>; 192 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 193 gpio-controller; 194 #gpio-cells = <2>; 195 gpio-ranges = <&tlmm 0 0 53>; 196 interrupt-controller; 197 #interrupt-cells = <2>; 198 199 serial_0_pins: serial0-state { 200 pins = "gpio18", "gpio19"; 201 function = "blsp0_uart0"; 202 drive-strength = <8>; 203 bias-pull-up; 204 }; 205 }; 206 207 gcc: clock-controller@1800000 { 208 compatible = "qcom,ipq5332-gcc"; 209 reg = <0x01800000 0x80000>; 210 #clock-cells = <1>; 211 #reset-cells = <1>; 212 #interconnect-cells = <1>; 213 clocks = <&xo_board>, 214 <&sleep_clk>, 215 <0>, 216 <0>, 217 <0>; 218 }; 219 220 tcsr_mutex: hwlock@1905000 { 221 compatible = "qcom,tcsr-mutex"; 222 reg = <0x01905000 0x20000>; 223 #hwlock-cells = <1>; 224 }; 225 226 tcsr: syscon@1937000 { 227 compatible = "qcom,tcsr-ipq5332", "syscon"; 228 reg = <0x01937000 0x21000>; 229 }; 230 231 sdhc: mmc@7804000 { 232 compatible = "qcom,ipq5332-sdhci", "qcom,sdhci-msm-v5"; 233 reg = <0x07804000 0x1000>, <0x07805000 0x1000>; 234 235 interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 236 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>; 237 interrupt-names = "hc_irq", "pwr_irq"; 238 239 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 240 <&gcc GCC_SDCC1_APPS_CLK>, 241 <&xo_board>; 242 clock-names = "iface", "core", "xo"; 243 status = "disabled"; 244 }; 245 246 blsp_dma: dma-controller@7884000 { 247 compatible = "qcom,bam-v1.7.0"; 248 reg = <0x07884000 0x1d000>; 249 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>; 250 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 251 clock-names = "bam_clk"; 252 #dma-cells = <1>; 253 qcom,ee = <0>; 254 }; 255 256 blsp1_uart0: serial@78af000 { 257 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 258 reg = <0x078af000 0x200>; 259 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 260 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 261 <&gcc GCC_BLSP1_AHB_CLK>; 262 clock-names = "core", "iface"; 263 status = "disabled"; 264 }; 265 266 blsp1_uart1: serial@78b0000 { 267 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 268 reg = <0x078b0000 0x200>; 269 interrupts = <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>; 270 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 271 <&gcc GCC_BLSP1_AHB_CLK>; 272 clock-names = "core", "iface"; 273 dmas = <&blsp_dma 2>, <&blsp_dma 3>; 274 dma-names = "tx", "rx"; 275 status = "disabled"; 276 }; 277 278 blsp1_spi0: spi@78b5000 { 279 compatible = "qcom,spi-qup-v2.2.1"; 280 reg = <0x078b5000 0x600>; 281 #address-cells = <1>; 282 #size-cells = <0>; 283 interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>; 284 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 285 <&gcc GCC_BLSP1_AHB_CLK>; 286 clock-names = "core", "iface"; 287 dmas = <&blsp_dma 4>, <&blsp_dma 5>; 288 dma-names = "tx", "rx"; 289 status = "disabled"; 290 }; 291 292 blsp1_i2c1: i2c@78b6000 { 293 compatible = "qcom,i2c-qup-v2.2.1"; 294 reg = <0x078b6000 0x600>; 295 #address-cells = <1>; 296 #size-cells = <0>; 297 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>; 298 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 299 <&gcc GCC_BLSP1_AHB_CLK>; 300 clock-names = "core", "iface"; 301 dmas = <&blsp_dma 6>, <&blsp_dma 7>; 302 dma-names = "tx", "rx"; 303 status = "disabled"; 304 }; 305 306 blsp1_spi2: spi@78b7000 { 307 compatible = "qcom,spi-qup-v2.2.1"; 308 reg = <0x078b7000 0x600>; 309 #address-cells = <1>; 310 #size-cells = <0>; 311 interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>; 312 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 313 <&gcc GCC_BLSP1_AHB_CLK>; 314 clock-names = "core", "iface"; 315 dmas = <&blsp_dma 8>, <&blsp_dma 9>; 316 dma-names = "tx", "rx"; 317 status = "disabled"; 318 }; 319 320 usb: usb@8af8800 { 321 compatible = "qcom,ipq5332-dwc3", "qcom,dwc3"; 322 reg = <0x08af8800 0x400>; 323 324 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 325 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 326 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 327 interrupt-names = "pwr_event", 328 "dp_hs_phy_irq", 329 "dm_hs_phy_irq"; 330 331 clocks = <&gcc GCC_USB0_MASTER_CLK>, 332 <&gcc GCC_USB0_SLEEP_CLK>, 333 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 334 clock-names = "core", 335 "sleep", 336 "mock_utmi"; 337 338 resets = <&gcc GCC_USB_BCR>; 339 340 qcom,select-utmi-as-pipe-clk; 341 342 #address-cells = <1>; 343 #size-cells = <1>; 344 ranges; 345 interconnects = <&gcc MASTER_SNOC_USB &gcc SLAVE_SNOC_USB>, 346 <&gcc MASTER_SNOC_USB &gcc SLAVE_SNOC_USB>; 347 interconnect-names = "usb-ddr", "apps-usb"; 348 349 status = "disabled"; 350 351 usb_dwc: usb@8a00000 { 352 compatible = "snps,dwc3"; 353 reg = <0x08a00000 0xe000>; 354 clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>; 355 clock-names = "ref"; 356 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 357 phy-names = "usb2-phy"; 358 phys = <&usbphy0>; 359 tx-fifo-resize; 360 snps,is-utmi-l1-suspend; 361 snps,hird-threshold = /bits/ 8 <0x0>; 362 snps,dis_u2_susphy_quirk; 363 snps,dis_u3_susphy_quirk; 364 }; 365 }; 366 367 intc: interrupt-controller@b000000 { 368 compatible = "qcom,msm-qgic2"; 369 reg = <0x0b000000 0x1000>, /* GICD */ 370 <0x0b002000 0x1000>, /* GICC */ 371 <0x0b001000 0x1000>, /* GICH */ 372 <0x0b004000 0x1000>; /* GICV */ 373 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 374 interrupt-controller; 375 #interrupt-cells = <3>; 376 #address-cells = <1>; 377 #size-cells = <1>; 378 ranges = <0 0x0b00c000 0x3000>; 379 380 v2m0: v2m@0 { 381 compatible = "arm,gic-v2m-frame"; 382 reg = <0x00000000 0xffd>; 383 msi-controller; 384 }; 385 386 v2m1: v2m@1000 { 387 compatible = "arm,gic-v2m-frame"; 388 reg = <0x00001000 0xffd>; 389 msi-controller; 390 }; 391 392 v2m2: v2m@2000 { 393 compatible = "arm,gic-v2m-frame"; 394 reg = <0x00002000 0xffd>; 395 msi-controller; 396 }; 397 }; 398 399 watchdog: watchdog@b017000 { 400 compatible = "qcom,apss-wdt-ipq5332", "qcom,kpss-wdt"; 401 reg = <0x0b017000 0x1000>; 402 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 403 clocks = <&sleep_clk>; 404 timeout-sec = <30>; 405 }; 406 407 apcs_glb: mailbox@b111000 { 408 compatible = "qcom,ipq5332-apcs-apps-global", 409 "qcom,ipq6018-apcs-apps-global"; 410 reg = <0x0b111000 0x1000>; 411 #clock-cells = <1>; 412 clocks = <&a53pll>, <&xo_board>, <&gcc GPLL0>; 413 clock-names = "pll", "xo", "gpll0"; 414 #mbox-cells = <1>; 415 }; 416 417 a53pll: clock@b116000 { 418 compatible = "qcom,ipq5332-a53pll"; 419 reg = <0x0b116000 0x40>; 420 #clock-cells = <0>; 421 clocks = <&xo_board>; 422 clock-names = "xo"; 423 }; 424 425 timer@b120000 { 426 compatible = "arm,armv7-timer-mem"; 427 reg = <0x0b120000 0x1000>; 428 #address-cells = <1>; 429 #size-cells = <1>; 430 ranges; 431 432 frame@b120000 { 433 reg = <0x0b121000 0x1000>, 434 <0x0b122000 0x1000>; 435 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 437 frame-number = <0>; 438 }; 439 440 frame@b123000 { 441 reg = <0x0b123000 0x1000>; 442 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 443 frame-number = <1>; 444 status = "disabled"; 445 }; 446 447 frame@b124000 { 448 reg = <0x0b124000 0x1000>; 449 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 450 frame-number = <2>; 451 status = "disabled"; 452 }; 453 454 frame@b125000 { 455 reg = <0x0b125000 0x1000>; 456 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 457 frame-number = <3>; 458 status = "disabled"; 459 }; 460 461 frame@b126000 { 462 reg = <0x0b126000 0x1000>; 463 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 464 frame-number = <4>; 465 status = "disabled"; 466 }; 467 468 frame@b127000 { 469 reg = <0x0b127000 0x1000>; 470 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 471 frame-number = <5>; 472 status = "disabled"; 473 }; 474 475 frame@b128000 { 476 reg = <0x0b128000 0x1000>; 477 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 478 frame-number = <6>; 479 status = "disabled"; 480 }; 481 }; 482 }; 483 484 timer { 485 compatible = "arm,armv8-timer"; 486 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 487 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 488 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 489 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 490 }; 491}; 492