1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * IPQ5332 device tree source 4 * 5 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,apss-ipq.h> 9#include <dt-bindings/clock/qcom,ipq5332-gcc.h> 10#include <dt-bindings/interconnect/qcom,ipq5332.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12 13/ { 14 interrupt-parent = <&intc>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 clocks { 19 sleep_clk: sleep-clk { 20 compatible = "fixed-clock"; 21 #clock-cells = <0>; 22 }; 23 24 xo_board: xo-board-clk { 25 compatible = "fixed-clock"; 26 #clock-cells = <0>; 27 }; 28 }; 29 30 cpus { 31 #address-cells = <1>; 32 #size-cells = <0>; 33 34 cpu0: cpu@0 { 35 device_type = "cpu"; 36 compatible = "arm,cortex-a53"; 37 reg = <0x0>; 38 enable-method = "psci"; 39 next-level-cache = <&l2_0>; 40 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 41 operating-points-v2 = <&cpu_opp_table>; 42 }; 43 44 cpu1: cpu@1 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a53"; 47 reg = <0x1>; 48 enable-method = "psci"; 49 next-level-cache = <&l2_0>; 50 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 51 operating-points-v2 = <&cpu_opp_table>; 52 }; 53 54 cpu2: cpu@2 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a53"; 57 reg = <0x2>; 58 enable-method = "psci"; 59 next-level-cache = <&l2_0>; 60 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 61 operating-points-v2 = <&cpu_opp_table>; 62 }; 63 64 cpu3: cpu@3 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a53"; 67 reg = <0x3>; 68 enable-method = "psci"; 69 next-level-cache = <&l2_0>; 70 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 71 operating-points-v2 = <&cpu_opp_table>; 72 }; 73 74 l2_0: l2-cache { 75 compatible = "cache"; 76 cache-level = <2>; 77 cache-unified; 78 }; 79 }; 80 81 firmware { 82 scm { 83 compatible = "qcom,scm-ipq5332", "qcom,scm"; 84 qcom,dload-mode = <&tcsr 0x6100>; 85 }; 86 }; 87 88 memory@40000000 { 89 device_type = "memory"; 90 /* We expect the bootloader to fill in the size */ 91 reg = <0x0 0x40000000 0x0 0x0>; 92 }; 93 94 cpu_opp_table: opp-table-cpu { 95 compatible = "operating-points-v2-kryo-cpu"; 96 opp-shared; 97 nvmem-cells = <&cpu_speed_bin>; 98 99 opp-1100000000 { 100 opp-hz = /bits/ 64 <1100000000>; 101 opp-supported-hw = <0x7>; 102 clock-latency-ns = <200000>; 103 }; 104 105 opp-1500000000 { 106 opp-hz = /bits/ 64 <1500000000>; 107 opp-supported-hw = <0x3>; 108 clock-latency-ns = <200000>; 109 }; 110 }; 111 112 pmu { 113 compatible = "arm,cortex-a53-pmu"; 114 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 115 }; 116 117 psci { 118 compatible = "arm,psci-1.0"; 119 method = "smc"; 120 }; 121 122 reserved-memory { 123 #address-cells = <2>; 124 #size-cells = <2>; 125 ranges; 126 127 bootloader@4a100000 { 128 reg = <0x0 0x4a100000 0x0 0x400000>; 129 no-map; 130 }; 131 132 sbl@4a500000 { 133 reg = <0x0 0x4a500000 0x0 0x100000>; 134 no-map; 135 }; 136 137 tz_mem: tz@4a600000 { 138 reg = <0x0 0x4a600000 0x0 0x200000>; 139 no-map; 140 }; 141 142 smem@4a800000 { 143 compatible = "qcom,smem"; 144 reg = <0x0 0x4a800000 0x0 0x100000>; 145 no-map; 146 147 hwlocks = <&tcsr_mutex 3>; 148 }; 149 }; 150 151 soc@0 { 152 compatible = "simple-bus"; 153 #address-cells = <1>; 154 #size-cells = <1>; 155 ranges = <0 0 0 0xffffffff>; 156 157 usbphy0: phy@7b000 { 158 compatible = "qcom,ipq5332-usb-hsphy"; 159 reg = <0x0007b000 0x12c>; 160 161 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>; 162 163 resets = <&gcc GCC_QUSB2_0_PHY_BCR>; 164 165 #phy-cells = <0>; 166 167 status = "disabled"; 168 }; 169 170 qfprom: efuse@a4000 { 171 compatible = "qcom,ipq5332-qfprom", "qcom,qfprom"; 172 reg = <0x000a4000 0x721>; 173 #address-cells = <1>; 174 #size-cells = <1>; 175 176 cpu_speed_bin: cpu-speed-bin@1d { 177 reg = <0x1d 0x2>; 178 bits = <7 2>; 179 }; 180 181 tsens_sens11_off: s11@3a5 { 182 reg = <0x3a5 0x1>; 183 bits = <4 4>; 184 }; 185 186 tsens_sens12_off: s12@3a6 { 187 reg = <0x3a6 0x1>; 188 bits = <0 4>; 189 }; 190 191 tsens_sens13_off: s13@3a6 { 192 reg = <0x3a6 0x1>; 193 bits = <4 4>; 194 }; 195 196 tsens_sens14_off: s14@3ad { 197 reg = <0x3ad 0x2>; 198 bits = <7 4>; 199 }; 200 201 tsens_sens15_off: s15@3ae { 202 reg = <0x3ae 0x1>; 203 bits = <3 4>; 204 }; 205 206 tsens_mode: mode@3e1 { 207 reg = <0x3e1 0x1>; 208 bits = <0 3>; 209 }; 210 211 tsens_base0: base0@3e1 { 212 reg = <0x3e1 0x2>; 213 bits = <3 10>; 214 }; 215 216 tsens_base1: base1@3e2 { 217 reg = <0x3e2 0x2>; 218 bits = <5 10>; 219 }; 220 }; 221 222 rng: rng@e3000 { 223 compatible = "qcom,ipq5332-trng", "qcom,trng"; 224 reg = <0x000e3000 0x1000>; 225 clocks = <&gcc GCC_PRNG_AHB_CLK>; 226 clock-names = "core"; 227 }; 228 229 tsens: thermal-sensor@4a9000 { 230 compatible = "qcom,ipq5332-tsens"; 231 reg = <0x004a9000 0x1000>, 232 <0x004a8000 0x1000>; 233 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>; 234 interrupt-names = "combined"; 235 nvmem-cells = <&tsens_mode>, 236 <&tsens_base0>, 237 <&tsens_base1>, 238 <&tsens_sens11_off>, 239 <&tsens_sens12_off>, 240 <&tsens_sens13_off>, 241 <&tsens_sens14_off>, 242 <&tsens_sens15_off>; 243 nvmem-cell-names = "mode", 244 "base0", 245 "base1", 246 "tsens_sens11_off", 247 "tsens_sens12_off", 248 "tsens_sens13_off", 249 "tsens_sens14_off", 250 "tsens_sens15_off"; 251 #qcom,sensors = <5>; 252 #thermal-sensor-cells = <1>; 253 }; 254 255 pcie0_phy: phy@4b0000 { 256 compatible = "qcom,ipq5332-uniphy-pcie-phy"; 257 reg = <0x004b0000 0x800>; 258 259 clocks = <&gcc GCC_PCIE3X1_0_PIPE_CLK>, 260 <&gcc GCC_PCIE3X1_PHY_AHB_CLK>; 261 262 resets = <&gcc GCC_PCIE3X1_0_PHY_BCR>, 263 <&gcc GCC_PCIE3X1_PHY_AHB_CLK_ARES>, 264 <&gcc GCC_PCIE3X1_0_PHY_PHY_BCR>; 265 266 #clock-cells = <0>; 267 268 #phy-cells = <0>; 269 270 num-lanes = <1>; 271 272 status = "disabled"; 273 }; 274 275 pcie1_phy: phy@4b1000 { 276 compatible = "qcom,ipq5332-uniphy-pcie-phy"; 277 reg = <0x004b1000 0x1000>; 278 279 clocks = <&gcc GCC_PCIE3X2_PIPE_CLK>, 280 <&gcc GCC_PCIE3X2_PHY_AHB_CLK>; 281 282 resets = <&gcc GCC_PCIE3X2_PHY_BCR>, 283 <&gcc GCC_PCIE3X2_PHY_AHB_CLK_ARES>, 284 <&gcc GCC_PCIE3X2PHY_PHY_BCR>; 285 286 #clock-cells = <0>; 287 288 #phy-cells = <0>; 289 290 num-lanes = <2>; 291 292 status = "disabled"; 293 }; 294 295 tlmm: pinctrl@1000000 { 296 compatible = "qcom,ipq5332-tlmm"; 297 reg = <0x01000000 0x300000>; 298 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 299 gpio-controller; 300 #gpio-cells = <2>; 301 gpio-ranges = <&tlmm 0 0 53>; 302 interrupt-controller; 303 #interrupt-cells = <2>; 304 305 serial_0_pins: serial0-state { 306 pins = "gpio18", "gpio19"; 307 function = "blsp0_uart0"; 308 drive-strength = <8>; 309 bias-pull-up; 310 }; 311 }; 312 313 gcc: clock-controller@1800000 { 314 compatible = "qcom,ipq5332-gcc"; 315 reg = <0x01800000 0x80000>; 316 #clock-cells = <1>; 317 #reset-cells = <1>; 318 #interconnect-cells = <1>; 319 clocks = <&xo_board>, 320 <&sleep_clk>, 321 <&pcie1_phy>, 322 <&pcie0_phy>, 323 <0>; 324 }; 325 326 tcsr_mutex: hwlock@1905000 { 327 compatible = "qcom,tcsr-mutex"; 328 reg = <0x01905000 0x20000>; 329 #hwlock-cells = <1>; 330 }; 331 332 tcsr: syscon@1937000 { 333 compatible = "qcom,tcsr-ipq5332", "syscon"; 334 reg = <0x01937000 0x21000>; 335 }; 336 337 sdhc: mmc@7804000 { 338 compatible = "qcom,ipq5332-sdhci", "qcom,sdhci-msm-v5"; 339 reg = <0x07804000 0x1000>, <0x07805000 0x1000>; 340 341 interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 342 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>; 343 interrupt-names = "hc_irq", "pwr_irq"; 344 345 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 346 <&gcc GCC_SDCC1_APPS_CLK>, 347 <&xo_board>; 348 clock-names = "iface", "core", "xo"; 349 status = "disabled"; 350 }; 351 352 blsp_dma: dma-controller@7884000 { 353 compatible = "qcom,bam-v1.7.0"; 354 reg = <0x07884000 0x1d000>; 355 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>; 356 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 357 clock-names = "bam_clk"; 358 #dma-cells = <1>; 359 qcom,ee = <0>; 360 }; 361 362 blsp1_uart0: serial@78af000 { 363 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 364 reg = <0x078af000 0x200>; 365 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 366 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 367 <&gcc GCC_BLSP1_AHB_CLK>; 368 clock-names = "core", "iface"; 369 status = "disabled"; 370 }; 371 372 blsp1_uart1: serial@78b0000 { 373 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 374 reg = <0x078b0000 0x200>; 375 interrupts = <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>; 376 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 377 <&gcc GCC_BLSP1_AHB_CLK>; 378 clock-names = "core", "iface"; 379 dmas = <&blsp_dma 2>, <&blsp_dma 3>; 380 dma-names = "tx", "rx"; 381 status = "disabled"; 382 }; 383 384 blsp1_spi0: spi@78b5000 { 385 compatible = "qcom,spi-qup-v2.2.1"; 386 reg = <0x078b5000 0x600>; 387 #address-cells = <1>; 388 #size-cells = <0>; 389 interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>; 390 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 391 <&gcc GCC_BLSP1_AHB_CLK>; 392 clock-names = "core", "iface"; 393 dmas = <&blsp_dma 4>, <&blsp_dma 5>; 394 dma-names = "tx", "rx"; 395 status = "disabled"; 396 }; 397 398 blsp1_i2c1: i2c@78b6000 { 399 compatible = "qcom,i2c-qup-v2.2.1"; 400 reg = <0x078b6000 0x600>; 401 #address-cells = <1>; 402 #size-cells = <0>; 403 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>; 404 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 405 <&gcc GCC_BLSP1_AHB_CLK>; 406 clock-names = "core", "iface"; 407 dmas = <&blsp_dma 6>, <&blsp_dma 7>; 408 dma-names = "tx", "rx"; 409 status = "disabled"; 410 }; 411 412 blsp1_spi2: spi@78b7000 { 413 compatible = "qcom,spi-qup-v2.2.1"; 414 reg = <0x078b7000 0x600>; 415 #address-cells = <1>; 416 #size-cells = <0>; 417 interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>; 418 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 419 <&gcc GCC_BLSP1_AHB_CLK>; 420 clock-names = "core", "iface"; 421 dmas = <&blsp_dma 8>, <&blsp_dma 9>; 422 dma-names = "tx", "rx"; 423 status = "disabled"; 424 }; 425 426 usb: usb@8af8800 { 427 compatible = "qcom,ipq5332-dwc3", "qcom,dwc3"; 428 reg = <0x08af8800 0x400>; 429 430 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 431 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 432 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 433 interrupt-names = "pwr_event", 434 "dp_hs_phy_irq", 435 "dm_hs_phy_irq"; 436 437 clocks = <&gcc GCC_USB0_MASTER_CLK>, 438 <&gcc GCC_USB0_SLEEP_CLK>, 439 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 440 clock-names = "core", 441 "sleep", 442 "mock_utmi"; 443 444 resets = <&gcc GCC_USB_BCR>; 445 446 qcom,select-utmi-as-pipe-clk; 447 448 #address-cells = <1>; 449 #size-cells = <1>; 450 ranges; 451 interconnects = <&gcc MASTER_SNOC_USB &gcc SLAVE_SNOC_USB>, 452 <&gcc MASTER_SNOC_USB &gcc SLAVE_SNOC_USB>; 453 interconnect-names = "usb-ddr", "apps-usb"; 454 455 status = "disabled"; 456 457 usb_dwc: usb@8a00000 { 458 compatible = "snps,dwc3"; 459 reg = <0x08a00000 0xe000>; 460 clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>; 461 clock-names = "ref"; 462 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 463 phy-names = "usb2-phy"; 464 phys = <&usbphy0>; 465 tx-fifo-resize; 466 snps,is-utmi-l1-suspend; 467 snps,hird-threshold = /bits/ 8 <0x0>; 468 snps,dis_u2_susphy_quirk; 469 snps,dis_u3_susphy_quirk; 470 }; 471 }; 472 473 intc: interrupt-controller@b000000 { 474 compatible = "qcom,msm-qgic2"; 475 reg = <0x0b000000 0x1000>, /* GICD */ 476 <0x0b002000 0x1000>, /* GICC */ 477 <0x0b001000 0x1000>, /* GICH */ 478 <0x0b004000 0x1000>; /* GICV */ 479 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 480 interrupt-controller; 481 #interrupt-cells = <3>; 482 #address-cells = <1>; 483 #size-cells = <1>; 484 ranges = <0 0x0b00c000 0x3000>; 485 486 v2m0: v2m@0 { 487 compatible = "arm,gic-v2m-frame"; 488 reg = <0x00000000 0xffd>; 489 msi-controller; 490 }; 491 492 v2m1: v2m@1000 { 493 compatible = "arm,gic-v2m-frame"; 494 reg = <0x00001000 0xffd>; 495 msi-controller; 496 }; 497 498 v2m2: v2m@2000 { 499 compatible = "arm,gic-v2m-frame"; 500 reg = <0x00002000 0xffd>; 501 msi-controller; 502 }; 503 }; 504 505 watchdog: watchdog@b017000 { 506 compatible = "qcom,apss-wdt-ipq5332", "qcom,kpss-wdt"; 507 reg = <0x0b017000 0x1000>; 508 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 509 clocks = <&sleep_clk>; 510 timeout-sec = <30>; 511 }; 512 513 apcs_glb: mailbox@b111000 { 514 compatible = "qcom,ipq5332-apcs-apps-global", 515 "qcom,ipq6018-apcs-apps-global"; 516 reg = <0x0b111000 0x1000>; 517 #clock-cells = <1>; 518 clocks = <&a53pll>, <&xo_board>, <&gcc GPLL0>; 519 clock-names = "pll", "xo", "gpll0"; 520 #mbox-cells = <1>; 521 }; 522 523 a53pll: clock@b116000 { 524 compatible = "qcom,ipq5332-a53pll"; 525 reg = <0x0b116000 0x40>; 526 #clock-cells = <0>; 527 clocks = <&xo_board>; 528 clock-names = "xo"; 529 }; 530 531 timer@b120000 { 532 compatible = "arm,armv7-timer-mem"; 533 reg = <0x0b120000 0x1000>; 534 #address-cells = <1>; 535 #size-cells = <1>; 536 ranges; 537 538 frame@b120000 { 539 reg = <0x0b121000 0x1000>, 540 <0x0b122000 0x1000>; 541 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 542 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 543 frame-number = <0>; 544 }; 545 546 frame@b123000 { 547 reg = <0x0b123000 0x1000>; 548 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 549 frame-number = <1>; 550 status = "disabled"; 551 }; 552 553 frame@b124000 { 554 reg = <0x0b124000 0x1000>; 555 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 556 frame-number = <2>; 557 status = "disabled"; 558 }; 559 560 frame@b125000 { 561 reg = <0x0b125000 0x1000>; 562 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 563 frame-number = <3>; 564 status = "disabled"; 565 }; 566 567 frame@b126000 { 568 reg = <0x0b126000 0x1000>; 569 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 570 frame-number = <4>; 571 status = "disabled"; 572 }; 573 574 frame@b127000 { 575 reg = <0x0b127000 0x1000>; 576 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 577 frame-number = <5>; 578 status = "disabled"; 579 }; 580 581 frame@b128000 { 582 reg = <0x0b128000 0x1000>; 583 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 584 frame-number = <6>; 585 status = "disabled"; 586 }; 587 }; 588 589 pcie1: pcie@18000000 { 590 compatible = "qcom,pcie-ipq5332", "qcom,pcie-ipq9574"; 591 reg = <0x18000000 0xf1c>, 592 <0x18000f20 0xa8>, 593 <0x18001000 0x1000>, 594 <0x00088000 0x3000>, 595 <0x18100000 0x1000>, 596 <0x0008b000 0x1000>; 597 reg-names = "dbi", 598 "elbi", 599 "atu", 600 "parf", 601 "config", 602 "mhi"; 603 device_type = "pci"; 604 linux,pci-domain = <1>; 605 num-lanes = <2>; 606 #address-cells = <3>; 607 #size-cells = <2>; 608 609 ranges = <0x01000000 0x0 0x00000000 0x18200000 0x0 0x00100000>, 610 <0x02000000 0x0 0x18300000 0x18300000 0x0 0x07d00000>; 611 612 msi-map = <0x0 &v2m0 0x0 0xffd>; 613 614 interrupts = <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 619 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 620 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 621 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 622 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>; 623 interrupt-names = "msi0", 624 "msi1", 625 "msi2", 626 "msi3", 627 "msi4", 628 "msi5", 629 "msi6", 630 "msi7", 631 "global"; 632 633 #interrupt-cells = <1>; 634 interrupt-map-mask = <0 0 0 0x7>; 635 interrupt-map = <0 0 0 1 &intc 0 0 412 IRQ_TYPE_LEVEL_HIGH>, 636 <0 0 0 2 &intc 0 0 413 IRQ_TYPE_LEVEL_HIGH>, 637 <0 0 0 3 &intc 0 0 414 IRQ_TYPE_LEVEL_HIGH>, 638 <0 0 0 4 &intc 0 0 415 IRQ_TYPE_LEVEL_HIGH>; 639 640 clocks = <&gcc GCC_PCIE3X2_AXI_M_CLK>, 641 <&gcc GCC_PCIE3X2_AXI_S_CLK>, 642 <&gcc GCC_PCIE3X2_AXI_S_BRIDGE_CLK>, 643 <&gcc GCC_PCIE3X2_RCHG_CLK>, 644 <&gcc GCC_PCIE3X2_AHB_CLK>, 645 <&gcc GCC_PCIE3X2_AUX_CLK>; 646 clock-names = "axi_m", 647 "axi_s", 648 "axi_bridge", 649 "rchng", 650 "ahb", 651 "aux"; 652 653 assigned-clocks = <&gcc GCC_PCIE3X2_AUX_CLK>; 654 655 assigned-clock-rates = <2000000>; 656 657 resets = <&gcc GCC_PCIE3X2_PIPE_ARES>, 658 <&gcc GCC_PCIE3X2_CORE_STICKY_ARES>, 659 <&gcc GCC_PCIE3X2_AXI_S_STICKY_ARES>, 660 <&gcc GCC_PCIE3X2_AXI_S_CLK_ARES>, 661 <&gcc GCC_PCIE3X2_AXI_M_STICKY_ARES>, 662 <&gcc GCC_PCIE3X2_AXI_M_CLK_ARES>, 663 <&gcc GCC_PCIE3X2_AUX_CLK_ARES>, 664 <&gcc GCC_PCIE3X2_AHB_CLK_ARES>; 665 reset-names = "pipe", 666 "sticky", 667 "axi_s_sticky", 668 "axi_s", 669 "axi_m_sticky", 670 "axi_m", 671 "aux", 672 "ahb"; 673 674 phys = <&pcie1_phy>; 675 phy-names = "pciephy"; 676 677 interconnects = <&gcc MASTER_SNOC_PCIE3_2_M &gcc SLAVE_SNOC_PCIE3_2_M>, 678 <&gcc MASTER_ANOC_PCIE3_2_S &gcc SLAVE_ANOC_PCIE3_2_S>; 679 interconnect-names = "pcie-mem", "cpu-pcie"; 680 681 status = "disabled"; 682 683 pcie@0 { 684 device_type = "pci"; 685 reg = <0x0 0x0 0x0 0x0 0x0>; 686 687 #address-cells = <3>; 688 #size-cells = <2>; 689 ranges; 690 }; 691 }; 692 693 pcie0: pcie@20000000 { 694 compatible = "qcom,pcie-ipq5332", "qcom,pcie-ipq9574"; 695 reg = <0x20000000 0xf1c>, 696 <0x20000f20 0xa8>, 697 <0x20001000 0x1000>, 698 <0x00080000 0x3000>, 699 <0x20100000 0x1000>, 700 <0x00083000 0x1000>; 701 reg-names = "dbi", 702 "elbi", 703 "atu", 704 "parf", 705 "config", 706 "mhi"; 707 device_type = "pci"; 708 linux,pci-domain = <0>; 709 num-lanes = <1>; 710 #address-cells = <3>; 711 #size-cells = <2>; 712 713 ranges = <0x01000000 0x0 0x00000000 0x20200000 0x0 0x00100000>, 714 <0x02000000 0x0 0x20300000 0x20300000 0x0 0x0fd00000>; 715 716 msi-map = <0x0 &v2m0 0x0 0xffd>; 717 718 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 719 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 720 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 721 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 722 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 723 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 724 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 725 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 726 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 727 interrupt-names = "msi0", 728 "msi1", 729 "msi2", 730 "msi3", 731 "msi4", 732 "msi5", 733 "msi6", 734 "msi7", 735 "global"; 736 737 #interrupt-cells = <1>; 738 interrupt-map-mask = <0 0 0 0x7>; 739 interrupt-map = <0 0 0 1 &intc 0 0 35 IRQ_TYPE_LEVEL_HIGH>, 740 <0 0 0 2 &intc 0 0 36 IRQ_TYPE_LEVEL_HIGH>, 741 <0 0 0 3 &intc 0 0 37 IRQ_TYPE_LEVEL_HIGH>, 742 <0 0 0 4 &intc 0 0 38 IRQ_TYPE_LEVEL_HIGH>; 743 744 clocks = <&gcc GCC_PCIE3X1_0_AXI_M_CLK>, 745 <&gcc GCC_PCIE3X1_0_AXI_S_CLK>, 746 <&gcc GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK>, 747 <&gcc GCC_PCIE3X1_0_RCHG_CLK>, 748 <&gcc GCC_PCIE3X1_0_AHB_CLK>, 749 <&gcc GCC_PCIE3X1_0_AUX_CLK>; 750 clock-names = "axi_m", 751 "axi_s", 752 "axi_bridge", 753 "rchng", 754 "ahb", 755 "aux"; 756 757 assigned-clocks = <&gcc GCC_PCIE3X1_0_AUX_CLK>; 758 759 assigned-clock-rates = <2000000>; 760 761 resets = <&gcc GCC_PCIE3X1_0_PIPE_ARES>, 762 <&gcc GCC_PCIE3X1_0_CORE_STICKY_ARES>, 763 <&gcc GCC_PCIE3X1_0_AXI_S_STICKY_ARES>, 764 <&gcc GCC_PCIE3X1_0_AXI_S_CLK_ARES>, 765 <&gcc GCC_PCIE3X1_0_AXI_M_STICKY_ARES>, 766 <&gcc GCC_PCIE3X1_0_AXI_M_CLK_ARES>, 767 <&gcc GCC_PCIE3X1_0_AUX_CLK_ARES>, 768 <&gcc GCC_PCIE3X1_0_AHB_CLK_ARES>; 769 reset-names = "pipe", 770 "sticky", 771 "axi_s_sticky", 772 "axi_s", 773 "axi_m_sticky", 774 "axi_m", 775 "aux", 776 "ahb"; 777 778 phys = <&pcie0_phy>; 779 phy-names = "pciephy"; 780 781 interconnects = <&gcc MASTER_SNOC_PCIE3_1_M &gcc SLAVE_SNOC_PCIE3_1_M>, 782 <&gcc MASTER_ANOC_PCIE3_1_S &gcc SLAVE_ANOC_PCIE3_1_S>; 783 interconnect-names = "pcie-mem", "cpu-pcie"; 784 785 status = "disabled"; 786 787 pcie@0 { 788 device_type = "pci"; 789 reg = <0x0 0x0 0x0 0x0 0x0>; 790 791 #address-cells = <3>; 792 #size-cells = <2>; 793 ranges; 794 }; 795 }; 796 }; 797 798 thermal-zones { 799 rfa-0-thermal { 800 thermal-sensors = <&tsens 11>; 801 802 trips { 803 rfa-0-critical { 804 temperature = <125000>; 805 hysteresis = <1000>; 806 type = "critical"; 807 }; 808 }; 809 }; 810 811 rfa-1-thermal { 812 thermal-sensors = <&tsens 12>; 813 814 trips { 815 rfa-1-critical { 816 temperature = <125000>; 817 hysteresis = <1000>; 818 type = "critical"; 819 }; 820 }; 821 }; 822 823 misc-thermal { 824 thermal-sensors = <&tsens 13>; 825 826 trips { 827 misc-critical { 828 temperature = <125000>; 829 hysteresis = <1000>; 830 type = "critical"; 831 }; 832 }; 833 }; 834 835 cpu-top-thermal { 836 polling-delay-passive = <100>; 837 thermal-sensors = <&tsens 14>; 838 839 trips { 840 cpu-top-critical { 841 temperature = <115000>; 842 hysteresis = <1000>; 843 type = "critical"; 844 }; 845 846 cpu-passive { 847 temperature = <105000>; 848 hysteresis = <1000>; 849 type = "passive"; 850 }; 851 }; 852 }; 853 854 top-glue-thermal { 855 thermal-sensors = <&tsens 15>; 856 857 trips { 858 top-glue-critical { 859 temperature = <125000>; 860 hysteresis = <1000>; 861 type = "critical"; 862 }; 863 }; 864 }; 865 }; 866 867 timer { 868 compatible = "arm,armv8-timer"; 869 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 870 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 871 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 872 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 873 }; 874}; 875