1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #ifndef __INTEL_CDCLK_H__ 7 #define __INTEL_CDCLK_H__ 8 9 #include <linux/types.h> 10 11 #include "intel_display_limits.h" 12 #include "intel_global_state.h" 13 14 struct drm_i915_private; 15 struct intel_atomic_state; 16 struct intel_crtc_state; 17 18 struct intel_cdclk_config { 19 unsigned int cdclk, vco, ref, bypass; 20 u8 voltage_level; 21 /* This field is only valid for Xe2LPD and above. */ 22 bool joined_mbus; 23 }; 24 25 struct intel_cdclk_state { 26 struct intel_global_state base; 27 28 /* 29 * Logical configuration of cdclk (used for all scaling, 30 * watermark, etc. calculations and checks). This is 31 * computed as if all enabled crtcs were active. 32 */ 33 struct intel_cdclk_config logical; 34 35 /* 36 * Actual configuration of cdclk, can be different from the 37 * logical configuration only when all crtc's are DPMS off. 38 */ 39 struct intel_cdclk_config actual; 40 41 /* minimum acceptable cdclk to satisfy bandwidth requirements */ 42 int bw_min_cdclk; 43 /* minimum acceptable cdclk for each pipe */ 44 int min_cdclk[I915_MAX_PIPES]; 45 /* minimum acceptable voltage level for each pipe */ 46 u8 min_voltage_level[I915_MAX_PIPES]; 47 48 /* pipe to which cd2x update is synchronized */ 49 enum pipe pipe; 50 51 /* forced minimum cdclk for glk+ audio w/a */ 52 int force_min_cdclk; 53 54 /* bitmask of active pipes */ 55 u8 active_pipes; 56 57 /* update cdclk with pipes disabled */ 58 bool disable_pipes; 59 }; 60 61 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state); 62 void intel_cdclk_init_hw(struct drm_i915_private *i915); 63 void intel_cdclk_uninit_hw(struct drm_i915_private *i915); 64 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv); 65 void intel_update_max_cdclk(struct drm_i915_private *dev_priv); 66 void intel_update_cdclk(struct drm_i915_private *dev_priv); 67 u32 intel_read_rawclk(struct drm_i915_private *dev_priv); 68 bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a, 69 const struct intel_cdclk_config *b); 70 int intel_mdclk_cdclk_ratio(struct drm_i915_private *i915, 71 const struct intel_cdclk_config *cdclk_config); 72 bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state); 73 void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state); 74 void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state); 75 void intel_cdclk_dump_config(struct drm_i915_private *i915, 76 const struct intel_cdclk_config *cdclk_config, 77 const char *context); 78 int intel_modeset_calc_cdclk(struct intel_atomic_state *state); 79 void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv, 80 struct intel_cdclk_config *cdclk_config); 81 int intel_cdclk_atomic_check(struct intel_atomic_state *state, 82 bool *need_cdclk_calc); 83 int intel_cdclk_state_set_joined_mbus(struct intel_atomic_state *state, bool joined_mbus); 84 struct intel_cdclk_state * 85 intel_atomic_get_cdclk_state(struct intel_atomic_state *state); 86 87 #define to_intel_cdclk_state(global_state) \ 88 container_of_const((global_state), struct intel_cdclk_state, base) 89 90 #define intel_atomic_get_old_cdclk_state(state) \ 91 to_intel_cdclk_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->display.cdclk.obj)) 92 #define intel_atomic_get_new_cdclk_state(state) \ 93 to_intel_cdclk_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->display.cdclk.obj)) 94 95 int intel_cdclk_init(struct drm_i915_private *dev_priv); 96 void intel_cdclk_debugfs_register(struct drm_i915_private *i915); 97 98 #endif /* __INTEL_CDCLK_H__ */ 99