1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Copyright(c) 2021-2024 Intel Corporation 4 // 5 // Authors: Cezary Rojewski <cezary.rojewski@intel.com> 6 // Amadeusz Slawinski <amadeuszx.slawinski@linux.intel.com> 7 // 8 9 #include <sound/hdaudio_ext.h> 10 #include "avs.h" 11 #include "messages.h" 12 #include "registers.h" 13 14 static void avs_cnl_ipc_interrupt(struct avs_dev *adev) 15 { 16 const struct avs_spec *spec = adev->spec; 17 u32 hipc_ack, hipc_rsp; 18 19 snd_hdac_adsp_updatel(adev, spec->hipc->ctl_offset, 20 AVS_ADSP_HIPCCTL_DONE | AVS_ADSP_HIPCCTL_BUSY, 0); 21 22 hipc_ack = snd_hdac_adsp_readl(adev, spec->hipc->ack_offset); 23 hipc_rsp = snd_hdac_adsp_readl(adev, spec->hipc->rsp_offset); 24 25 /* DSP acked host's request. */ 26 if (hipc_ack & spec->hipc->ack_done_mask) { 27 complete(&adev->ipc->done_completion); 28 29 /* Tell DSP it has our attention. */ 30 snd_hdac_adsp_updatel(adev, spec->hipc->ack_offset, spec->hipc->ack_done_mask, 31 spec->hipc->ack_done_mask); 32 } 33 34 /* DSP sent new response to process. */ 35 if (hipc_rsp & spec->hipc->rsp_busy_mask) { 36 union avs_reply_msg msg; 37 u32 hipctda; 38 39 msg.primary = snd_hdac_adsp_readl(adev, CNL_ADSP_REG_HIPCTDR); 40 msg.ext.val = snd_hdac_adsp_readl(adev, CNL_ADSP_REG_HIPCTDD); 41 42 avs_dsp_process_response(adev, msg.val); 43 44 /* Tell DSP we accepted its message. */ 45 snd_hdac_adsp_updatel(adev, CNL_ADSP_REG_HIPCTDR, 46 CNL_ADSP_HIPCTDR_BUSY, CNL_ADSP_HIPCTDR_BUSY); 47 /* Ack this response. */ 48 snd_hdac_adsp_updatel(adev, CNL_ADSP_REG_HIPCTDA, 49 CNL_ADSP_HIPCTDA_DONE, CNL_ADSP_HIPCTDA_DONE); 50 /* HW might have been clock gated, give some time for change to propagate. */ 51 snd_hdac_adsp_readl_poll(adev, CNL_ADSP_REG_HIPCTDA, hipctda, 52 !(hipctda & CNL_ADSP_HIPCTDA_DONE), 10, 1000); 53 } 54 55 snd_hdac_adsp_updatel(adev, spec->hipc->ctl_offset, 56 AVS_ADSP_HIPCCTL_DONE | AVS_ADSP_HIPCCTL_BUSY, 57 AVS_ADSP_HIPCCTL_DONE | AVS_ADSP_HIPCCTL_BUSY); 58 } 59 60 irqreturn_t avs_cnl_dsp_interrupt(struct avs_dev *adev) 61 { 62 u32 adspis = snd_hdac_adsp_readl(adev, AVS_ADSP_REG_ADSPIS); 63 irqreturn_t ret = IRQ_NONE; 64 65 if (adspis == UINT_MAX) 66 return ret; 67 68 if (adspis & AVS_ADSP_ADSPIS_IPC) { 69 avs_cnl_ipc_interrupt(adev); 70 ret = IRQ_HANDLED; 71 } 72 73 return ret; 74 } 75 76 const struct avs_dsp_ops avs_cnl_dsp_ops = { 77 .power = avs_dsp_core_power, 78 .reset = avs_dsp_core_reset, 79 .stall = avs_dsp_core_stall, 80 .dsp_interrupt = avs_cnl_dsp_interrupt, 81 .int_control = avs_dsp_interrupt_control, 82 .load_basefw = avs_hda_load_basefw, 83 .load_lib = avs_hda_load_library, 84 .transfer_mods = avs_hda_transfer_modules, 85 .log_buffer_offset = avs_skl_log_buffer_offset, 86 .log_buffer_status = avs_apl_log_buffer_status, 87 .coredump = avs_apl_coredump, 88 .d0ix_toggle = avs_apl_d0ix_toggle, 89 .set_d0ix = avs_apl_set_d0ix, 90 AVS_SET_ENABLE_LOGS_OP(apl) 91 }; 92