1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2022 NXP 4 */ 5 6#include <dt-bindings/clock/imx93-clock.h> 7#include <dt-bindings/dma/fsl-edma.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/input.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/power/fsl,imx93-power.h> 12#include <dt-bindings/thermal/thermal.h> 13 14#include "imx93-pinfunc.h" 15 16/ { 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 gpio0 = &gpio1; 23 gpio1 = &gpio2; 24 gpio2 = &gpio3; 25 gpio3 = &gpio4; 26 i2c0 = &lpi2c1; 27 i2c1 = &lpi2c2; 28 i2c2 = &lpi2c3; 29 i2c3 = &lpi2c4; 30 i2c4 = &lpi2c5; 31 i2c5 = &lpi2c6; 32 i2c6 = &lpi2c7; 33 i2c7 = &lpi2c8; 34 mmc0 = &usdhc1; 35 mmc1 = &usdhc2; 36 mmc2 = &usdhc3; 37 serial0 = &lpuart1; 38 serial1 = &lpuart2; 39 serial2 = &lpuart3; 40 serial3 = &lpuart4; 41 serial4 = &lpuart5; 42 serial5 = &lpuart6; 43 serial6 = &lpuart7; 44 serial7 = &lpuart8; 45 spi0 = &lpspi1; 46 spi1 = &lpspi2; 47 spi2 = &lpspi3; 48 spi3 = &lpspi4; 49 spi4 = &lpspi5; 50 spi5 = &lpspi6; 51 spi6 = &lpspi7; 52 spi7 = &lpspi8; 53 }; 54 55 cpus { 56 #address-cells = <1>; 57 #size-cells = <0>; 58 59 idle-states { 60 entry-method = "psci"; 61 62 cpu_pd_wait: cpu-pd-wait { 63 compatible = "arm,idle-state"; 64 arm,psci-suspend-param = <0x0010033>; 65 local-timer-stop; 66 entry-latency-us = <10000>; 67 exit-latency-us = <7000>; 68 min-residency-us = <27000>; 69 wakeup-latency-us = <15000>; 70 }; 71 }; 72 73 A55_0: cpu@0 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a55"; 76 reg = <0x0>; 77 enable-method = "psci"; 78 #cooling-cells = <2>; 79 cpu-idle-states = <&cpu_pd_wait>; 80 i-cache-size = <32768>; 81 i-cache-line-size = <64>; 82 i-cache-sets = <128>; 83 d-cache-size = <32768>; 84 d-cache-line-size = <64>; 85 d-cache-sets = <128>; 86 next-level-cache = <&l2_cache_l0>; 87 }; 88 89 A55_1: cpu@100 { 90 device_type = "cpu"; 91 compatible = "arm,cortex-a55"; 92 reg = <0x100>; 93 enable-method = "psci"; 94 #cooling-cells = <2>; 95 cpu-idle-states = <&cpu_pd_wait>; 96 i-cache-size = <32768>; 97 i-cache-line-size = <64>; 98 i-cache-sets = <128>; 99 d-cache-size = <32768>; 100 d-cache-line-size = <64>; 101 d-cache-sets = <128>; 102 next-level-cache = <&l2_cache_l1>; 103 }; 104 105 l2_cache_l0: l2-cache-l0 { 106 compatible = "cache"; 107 cache-size = <65536>; 108 cache-line-size = <64>; 109 cache-sets = <256>; 110 cache-level = <2>; 111 cache-unified; 112 next-level-cache = <&l3_cache>; 113 }; 114 115 l2_cache_l1: l2-cache-l1 { 116 compatible = "cache"; 117 cache-size = <65536>; 118 cache-line-size = <64>; 119 cache-sets = <256>; 120 cache-level = <2>; 121 cache-unified; 122 next-level-cache = <&l3_cache>; 123 }; 124 125 l3_cache: l3-cache { 126 compatible = "cache"; 127 cache-size = <262144>; 128 cache-line-size = <64>; 129 cache-sets = <256>; 130 cache-level = <3>; 131 cache-unified; 132 }; 133 }; 134 135 osc_32k: clock-osc-32k { 136 compatible = "fixed-clock"; 137 #clock-cells = <0>; 138 clock-frequency = <32768>; 139 clock-output-names = "osc_32k"; 140 }; 141 142 osc_24m: clock-osc-24m { 143 compatible = "fixed-clock"; 144 #clock-cells = <0>; 145 clock-frequency = <24000000>; 146 clock-output-names = "osc_24m"; 147 }; 148 149 clk_ext1: clock-ext1 { 150 compatible = "fixed-clock"; 151 #clock-cells = <0>; 152 clock-frequency = <133000000>; 153 clock-output-names = "clk_ext1"; 154 }; 155 156 pmu { 157 compatible = "arm,cortex-a55-pmu"; 158 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 159 }; 160 161 psci { 162 compatible = "arm,psci-1.0"; 163 method = "smc"; 164 }; 165 166 timer { 167 compatible = "arm,armv8-timer"; 168 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 169 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 170 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 171 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 172 clock-frequency = <24000000>; 173 arm,no-tick-in-suspend; 174 interrupt-parent = <&gic>; 175 }; 176 177 gic: interrupt-controller@48000000 { 178 compatible = "arm,gic-v3"; 179 reg = <0 0x48000000 0 0x10000>, 180 <0 0x48040000 0 0xc0000>; 181 #interrupt-cells = <3>; 182 interrupt-controller; 183 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 184 interrupt-parent = <&gic>; 185 }; 186 187 thermal-zones { 188 cpu-thermal { 189 polling-delay-passive = <250>; 190 polling-delay = <2000>; 191 192 thermal-sensors = <&tmu 0>; 193 194 trips { 195 cpu_alert: cpu-alert { 196 temperature = <80000>; 197 hysteresis = <2000>; 198 type = "passive"; 199 }; 200 201 cpu_crit: cpu-crit { 202 temperature = <90000>; 203 hysteresis = <2000>; 204 type = "critical"; 205 }; 206 }; 207 208 cooling-maps { 209 map0 { 210 trip = <&cpu_alert>; 211 cooling-device = 212 <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 213 <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 214 }; 215 }; 216 }; 217 }; 218 219 cm33: remoteproc-cm33 { 220 compatible = "fsl,imx93-cm33"; 221 clocks = <&clk IMX93_CLK_CM33_GATE>; 222 status = "disabled"; 223 }; 224 225 mqs1: mqs1 { 226 compatible = "fsl,imx93-mqs"; 227 gpr = <&aonmix_ns_gpr>; 228 status = "disabled"; 229 }; 230 231 mqs2: mqs2 { 232 compatible = "fsl,imx93-mqs"; 233 gpr = <&wakeupmix_gpr>; 234 status = "disabled"; 235 }; 236 237 usbphynop1: usbphynop1 { 238 compatible = "usb-nop-xceiv"; 239 #phy-cells = <0>; 240 clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>; 241 clock-names = "main_clk"; 242 }; 243 244 usbphynop2: usbphynop2 { 245 compatible = "usb-nop-xceiv"; 246 #phy-cells = <0>; 247 clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>; 248 clock-names = "main_clk"; 249 }; 250 251 soc@0 { 252 compatible = "simple-bus"; 253 #address-cells = <1>; 254 #size-cells = <1>; 255 ranges = <0x0 0x0 0x0 0x80000000>, 256 <0x28000000 0x0 0x28000000 0x10000000>; 257 258 aips1: bus@44000000 { 259 compatible = "fsl,aips-bus", "simple-bus"; 260 reg = <0x44000000 0x800000>; 261 #address-cells = <1>; 262 #size-cells = <1>; 263 ranges; 264 265 edma1: dma-controller@44000000 { 266 compatible = "fsl,imx93-edma3"; 267 reg = <0x44000000 0x200000>; 268 #dma-cells = <3>; 269 dma-channels = <31>; 270 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, // 0: Reserved 271 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, // 1: CANFD1 272 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, // 2: Reserved 273 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, // 3: GPIO1 CH0 274 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, // 4: GPIO1 CH1 275 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, // 5: I3C1 TO Bus 276 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, // 6: I3C1 From Bus 277 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, // 7: LPI2C1 M TX 278 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, // 8: LPI2C1 S TX 279 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, // 9: LPI2C2 M RX 280 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, // 10: LPI2C2 S RX 281 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, // 11: LPSPI1 TX 282 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, // 12: LPSPI1 RX 283 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, // 13: LPSPI2 TX 284 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, // 14: LPSPI2 RX 285 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, // 15: LPTMR1 286 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, // 16: LPUART1 TX 287 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, // 17: LPUART1 RX 288 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, // 18: LPUART2 TX 289 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, // 19: LPUART2 RX 290 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, // 20: S400 291 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, // 21: SAI TX 292 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, // 22: SAI RX 293 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, // 23: TPM1 CH0/CH2 294 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, // 24: TPM1 CH1/CH3 295 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, // 25: TPM1 Overflow 296 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, // 26: TMP2 CH0/CH2 297 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, // 27: TMP2 CH1/CH3 298 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, // 28: TMP2 Overflow 299 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, // 29: PDM 300 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, // 30: ADC1 301 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; // err 302 clocks = <&clk IMX93_CLK_EDMA1_GATE>; 303 clock-names = "dma"; 304 }; 305 306 aonmix_ns_gpr: syscon@44210000 { 307 compatible = "fsl,imx93-aonmix-ns-syscfg", "syscon"; 308 reg = <0x44210000 0x1000>; 309 }; 310 311 mu1: mailbox@44230000 { 312 compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; 313 reg = <0x44230000 0x10000>; 314 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 315 clocks = <&clk IMX93_CLK_MU1_B_GATE>; 316 #mbox-cells = <2>; 317 status = "disabled"; 318 }; 319 320 system_counter: timer@44290000 { 321 compatible = "nxp,sysctr-timer"; 322 reg = <0x44290000 0x30000>; 323 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 324 clocks = <&osc_24m>; 325 clock-names = "per"; 326 nxp,no-divider; 327 }; 328 329 wdog1: watchdog@442d0000 { 330 compatible = "fsl,imx93-wdt"; 331 reg = <0x442d0000 0x10000>; 332 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 333 clocks = <&clk IMX93_CLK_WDOG1_GATE>; 334 timeout-sec = <40>; 335 status = "disabled"; 336 }; 337 338 wdog2: watchdog@442e0000 { 339 compatible = "fsl,imx93-wdt"; 340 reg = <0x442e0000 0x10000>; 341 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 342 clocks = <&clk IMX93_CLK_WDOG2_GATE>; 343 timeout-sec = <40>; 344 status = "disabled"; 345 }; 346 347 tpm1: pwm@44310000 { 348 compatible = "fsl,imx7ulp-pwm"; 349 reg = <0x44310000 0x1000>; 350 clocks = <&clk IMX93_CLK_TPM1_GATE>; 351 #pwm-cells = <3>; 352 status = "disabled"; 353 }; 354 355 tpm2: pwm@44320000 { 356 compatible = "fsl,imx7ulp-pwm"; 357 reg = <0x44320000 0x10000>; 358 clocks = <&clk IMX93_CLK_TPM2_GATE>; 359 #pwm-cells = <3>; 360 status = "disabled"; 361 }; 362 363 i3c1: i3c@44330000 { 364 compatible = "silvaco,i3c-master-v1"; 365 reg = <0x44330000 0x10000>; 366 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 367 #address-cells = <3>; 368 #size-cells = <0>; 369 clocks = <&clk IMX93_CLK_BUS_AON>, 370 <&clk IMX93_CLK_I3C1_GATE>, 371 <&clk IMX93_CLK_I3C1_SLOW>; 372 clock-names = "pclk", "fast_clk", "slow_clk"; 373 status = "disabled"; 374 }; 375 376 lpi2c1: i2c@44340000 { 377 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 378 reg = <0x44340000 0x10000>; 379 #address-cells = <1>; 380 #size-cells = <0>; 381 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 382 clocks = <&clk IMX93_CLK_LPI2C1_GATE>, 383 <&clk IMX93_CLK_BUS_AON>; 384 clock-names = "per", "ipg"; 385 dmas = <&edma1 7 0 0>, <&edma1 8 0 FSL_EDMA_RX>; 386 dma-names = "tx", "rx"; 387 status = "disabled"; 388 }; 389 390 lpi2c2: i2c@44350000 { 391 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 392 reg = <0x44350000 0x10000>; 393 #address-cells = <1>; 394 #size-cells = <0>; 395 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 396 clocks = <&clk IMX93_CLK_LPI2C2_GATE>, 397 <&clk IMX93_CLK_BUS_AON>; 398 clock-names = "per", "ipg"; 399 dmas = <&edma1 9 0 0>, <&edma1 10 0 FSL_EDMA_RX>; 400 dma-names = "tx", "rx"; 401 status = "disabled"; 402 }; 403 404 lpspi1: spi@44360000 { 405 #address-cells = <1>; 406 #size-cells = <0>; 407 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 408 reg = <0x44360000 0x10000>; 409 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 410 clocks = <&clk IMX93_CLK_LPSPI1_GATE>, 411 <&clk IMX93_CLK_BUS_AON>; 412 clock-names = "per", "ipg"; 413 dmas = <&edma1 11 0 0>, <&edma1 12 0 FSL_EDMA_RX>; 414 dma-names = "tx", "rx"; 415 status = "disabled"; 416 }; 417 418 lpspi2: spi@44370000 { 419 #address-cells = <1>; 420 #size-cells = <0>; 421 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 422 reg = <0x44370000 0x10000>; 423 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 424 clocks = <&clk IMX93_CLK_LPSPI2_GATE>, 425 <&clk IMX93_CLK_BUS_AON>; 426 clock-names = "per", "ipg"; 427 dmas = <&edma1 13 0 0>, <&edma1 14 0 FSL_EDMA_RX>; 428 dma-names = "tx", "rx"; 429 status = "disabled"; 430 }; 431 432 lpuart1: serial@44380000 { 433 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 434 reg = <0x44380000 0x1000>; 435 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 436 clocks = <&clk IMX93_CLK_LPUART1_GATE>; 437 clock-names = "ipg"; 438 dmas = <&edma1 17 0 FSL_EDMA_RX>, <&edma1 16 0 0>; 439 dma-names = "rx", "tx"; 440 status = "disabled"; 441 }; 442 443 lpuart2: serial@44390000 { 444 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 445 reg = <0x44390000 0x1000>; 446 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 447 clocks = <&clk IMX93_CLK_LPUART2_GATE>; 448 clock-names = "ipg"; 449 dmas = <&edma1 19 0 FSL_EDMA_RX>, <&edma1 18 0 0>; 450 dma-names = "rx", "tx"; 451 status = "disabled"; 452 }; 453 454 flexcan1: can@443a0000 { 455 compatible = "fsl,imx93-flexcan"; 456 reg = <0x443a0000 0x10000>; 457 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 458 clocks = <&clk IMX93_CLK_BUS_AON>, 459 <&clk IMX93_CLK_CAN1_GATE>; 460 clock-names = "ipg", "per"; 461 assigned-clocks = <&clk IMX93_CLK_CAN1>; 462 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; 463 assigned-clock-rates = <40000000>; 464 fsl,clk-source = /bits/ 8 <0>; 465 fsl,stop-mode = <&aonmix_ns_gpr 0x14 0>; 466 status = "disabled"; 467 }; 468 469 sai1: sai@443b0000 { 470 compatible = "fsl,imx93-sai"; 471 reg = <0x443b0000 0x10000>; 472 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 473 clocks = <&clk IMX93_CLK_SAI1_IPG>, <&clk IMX93_CLK_DUMMY>, 474 <&clk IMX93_CLK_SAI1_GATE>, <&clk IMX93_CLK_DUMMY>, 475 <&clk IMX93_CLK_DUMMY>; 476 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 477 dmas = <&edma1 22 0 FSL_EDMA_RX>, <&edma1 21 0 0>; 478 dma-names = "rx", "tx"; 479 #sound-dai-cells = <0>; 480 status = "disabled"; 481 }; 482 483 iomuxc: pinctrl@443c0000 { 484 compatible = "fsl,imx93-iomuxc"; 485 reg = <0x443c0000 0x10000>; 486 status = "okay"; 487 }; 488 489 bbnsm: bbnsm@44440000 { 490 compatible = "nxp,imx93-bbnsm", "syscon", "simple-mfd"; 491 reg = <0x44440000 0x10000>; 492 493 bbnsm_rtc: rtc { 494 compatible = "nxp,imx93-bbnsm-rtc"; 495 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 496 }; 497 498 bbnsm_pwrkey: pwrkey { 499 compatible = "nxp,imx93-bbnsm-pwrkey"; 500 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 501 linux,code = <KEY_POWER>; 502 }; 503 }; 504 505 clk: clock-controller@44450000 { 506 compatible = "fsl,imx93-ccm"; 507 reg = <0x44450000 0x10000>; 508 #clock-cells = <1>; 509 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>; 510 clock-names = "osc_32k", "osc_24m", "clk_ext1"; 511 assigned-clocks = <&clk IMX93_CLK_AUDIO_PLL>; 512 assigned-clock-rates = <393216000>; 513 status = "okay"; 514 }; 515 516 src: system-controller@44460000 { 517 compatible = "fsl,imx93-src", "syscon"; 518 reg = <0x44460000 0x10000>; 519 #address-cells = <1>; 520 #size-cells = <1>; 521 ranges; 522 523 mlmix: power-domain@44461800 { 524 compatible = "fsl,imx93-src-slice"; 525 reg = <0x44461800 0x400>, <0x44464800 0x400>; 526 #power-domain-cells = <0>; 527 clocks = <&clk IMX93_CLK_ML_APB>, 528 <&clk IMX93_CLK_ML>; 529 }; 530 531 mediamix: power-domain@44462400 { 532 compatible = "fsl,imx93-src-slice"; 533 reg = <0x44462400 0x400>, <0x44465800 0x400>; 534 #power-domain-cells = <0>; 535 clocks = <&clk IMX93_CLK_NIC_MEDIA_GATE>, 536 <&clk IMX93_CLK_MEDIA_APB>; 537 }; 538 }; 539 540 clock-controller@44480000 { 541 compatible = "fsl,imx93-anatop"; 542 reg = <0x44480000 0x2000>; 543 #clock-cells = <1>; 544 }; 545 546 tmu: tmu@44482000 { 547 compatible = "fsl,qoriq-tmu"; 548 reg = <0x44482000 0x1000>; 549 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 550 clocks = <&clk IMX93_CLK_TMC_GATE>; 551 little-endian; 552 fsl,tmu-range = <0x800000da 0x800000e9 553 0x80000102 0x8000012a 554 0x80000166 0x800001a7 555 0x800001b6>; 556 fsl,tmu-calibration = <0x00000000 0x0000000e 557 0x00000001 0x00000029 558 0x00000002 0x00000056 559 0x00000003 0x000000a2 560 0x00000004 0x00000116 561 0x00000005 0x00000195 562 0x00000006 0x000001b2>; 563 #thermal-sensor-cells = <1>; 564 }; 565 566 micfil: micfil@44520000 { 567 compatible = "fsl,imx93-micfil"; 568 reg = <0x44520000 0x10000>; 569 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 573 clocks = <&clk IMX93_CLK_PDM_IPG>, 574 <&clk IMX93_CLK_PDM_GATE>, 575 <&clk IMX93_CLK_AUDIO_PLL>; 576 clock-names = "ipg_clk", "ipg_clk_app", "pll8k"; 577 dmas = <&edma1 29 0 5>; 578 dma-names = "rx"; 579 #sound-dai-cells = <0>; 580 status = "disabled"; 581 }; 582 583 adc1: adc@44530000 { 584 compatible = "nxp,imx93-adc"; 585 reg = <0x44530000 0x10000>; 586 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 588 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; 589 clocks = <&clk IMX93_CLK_ADC1_GATE>; 590 clock-names = "ipg"; 591 #io-channel-cells = <1>; 592 status = "disabled"; 593 }; 594 }; 595 596 aips2: bus@42000000 { 597 compatible = "fsl,aips-bus", "simple-bus"; 598 reg = <0x42000000 0x800000>; 599 #address-cells = <1>; 600 #size-cells = <1>; 601 ranges; 602 603 edma2: dma-controller@42000000 { 604 compatible = "fsl,imx93-edma4"; 605 reg = <0x42000000 0x210000>; 606 #dma-cells = <3>; 607 dma-channels = <64>; 608 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 611 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 619 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 620 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 621 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 622 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 623 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 624 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 625 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 626 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 628 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 629 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 630 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 631 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 632 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 633 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 634 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 635 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 636 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 638 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 639 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 640 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 641 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 642 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 644 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 645 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 646 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 647 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 648 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 649 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 650 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 651 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 652 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 653 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 654 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 655 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 656 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 657 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 658 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 659 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 660 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 661 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 662 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 663 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 664 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 665 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 666 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 667 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 668 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 669 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 670 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 671 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 672 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 673 clocks = <&clk IMX93_CLK_EDMA2_GATE>; 674 clock-names = "dma"; 675 }; 676 677 wakeupmix_gpr: syscon@42420000 { 678 compatible = "fsl,imx93-wakeupmix-syscfg", "syscon"; 679 reg = <0x42420000 0x1000>; 680 }; 681 682 mu2: mailbox@42440000 { 683 compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; 684 reg = <0x42440000 0x10000>; 685 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 686 clocks = <&clk IMX93_CLK_MU2_B_GATE>; 687 #mbox-cells = <2>; 688 status = "disabled"; 689 }; 690 691 wdog3: watchdog@42490000 { 692 compatible = "fsl,imx93-wdt"; 693 reg = <0x42490000 0x10000>; 694 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 695 clocks = <&clk IMX93_CLK_WDOG3_GATE>; 696 timeout-sec = <40>; 697 status = "disabled"; 698 }; 699 700 wdog4: watchdog@424a0000 { 701 compatible = "fsl,imx93-wdt"; 702 reg = <0x424a0000 0x10000>; 703 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 704 clocks = <&clk IMX93_CLK_WDOG4_GATE>; 705 timeout-sec = <40>; 706 status = "disabled"; 707 }; 708 709 wdog5: watchdog@424b0000 { 710 compatible = "fsl,imx93-wdt"; 711 reg = <0x424b0000 0x10000>; 712 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 713 clocks = <&clk IMX93_CLK_WDOG5_GATE>; 714 timeout-sec = <40>; 715 status = "disabled"; 716 }; 717 718 tpm3: pwm@424e0000 { 719 compatible = "fsl,imx7ulp-pwm"; 720 reg = <0x424e0000 0x1000>; 721 clocks = <&clk IMX93_CLK_TPM3_GATE>; 722 #pwm-cells = <3>; 723 status = "disabled"; 724 }; 725 726 tpm4: pwm@424f0000 { 727 compatible = "fsl,imx7ulp-pwm"; 728 reg = <0x424f0000 0x10000>; 729 clocks = <&clk IMX93_CLK_TPM4_GATE>; 730 #pwm-cells = <3>; 731 status = "disabled"; 732 }; 733 734 tpm5: pwm@42500000 { 735 compatible = "fsl,imx7ulp-pwm"; 736 reg = <0x42500000 0x10000>; 737 clocks = <&clk IMX93_CLK_TPM5_GATE>; 738 #pwm-cells = <3>; 739 status = "disabled"; 740 }; 741 742 tpm6: pwm@42510000 { 743 compatible = "fsl,imx7ulp-pwm"; 744 reg = <0x42510000 0x10000>; 745 clocks = <&clk IMX93_CLK_TPM6_GATE>; 746 #pwm-cells = <3>; 747 status = "disabled"; 748 }; 749 750 i3c2: i3c@42520000 { 751 compatible = "silvaco,i3c-master-v1"; 752 reg = <0x42520000 0x10000>; 753 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 754 #address-cells = <3>; 755 #size-cells = <0>; 756 clocks = <&clk IMX93_CLK_BUS_WAKEUP>, 757 <&clk IMX93_CLK_I3C2_GATE>, 758 <&clk IMX93_CLK_I3C2_SLOW>; 759 clock-names = "pclk", "fast_clk", "slow_clk"; 760 status = "disabled"; 761 }; 762 763 lpi2c3: i2c@42530000 { 764 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 765 reg = <0x42530000 0x10000>; 766 #address-cells = <1>; 767 #size-cells = <0>; 768 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 769 clocks = <&clk IMX93_CLK_LPI2C3_GATE>, 770 <&clk IMX93_CLK_BUS_WAKEUP>; 771 clock-names = "per", "ipg"; 772 dmas = <&edma2 8 0 0>, <&edma2 9 0 FSL_EDMA_RX>; 773 dma-names = "tx", "rx"; 774 status = "disabled"; 775 }; 776 777 lpi2c4: i2c@42540000 { 778 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 779 reg = <0x42540000 0x10000>; 780 #address-cells = <1>; 781 #size-cells = <0>; 782 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 783 clocks = <&clk IMX93_CLK_LPI2C4_GATE>, 784 <&clk IMX93_CLK_BUS_WAKEUP>; 785 clock-names = "per", "ipg"; 786 dmas = <&edma2 10 0 0>, <&edma2 11 0 FSL_EDMA_RX>; 787 dma-names = "tx", "rx"; 788 status = "disabled"; 789 }; 790 791 lpspi3: spi@42550000 { 792 #address-cells = <1>; 793 #size-cells = <0>; 794 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 795 reg = <0x42550000 0x10000>; 796 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 797 clocks = <&clk IMX93_CLK_LPSPI3_GATE>, 798 <&clk IMX93_CLK_BUS_WAKEUP>; 799 clock-names = "per", "ipg"; 800 dmas = <&edma2 12 0 0>, <&edma2 13 0 FSL_EDMA_RX>; 801 dma-names = "tx", "rx"; 802 status = "disabled"; 803 }; 804 805 lpspi4: spi@42560000 { 806 #address-cells = <1>; 807 #size-cells = <0>; 808 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 809 reg = <0x42560000 0x10000>; 810 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 811 clocks = <&clk IMX93_CLK_LPSPI4_GATE>, 812 <&clk IMX93_CLK_BUS_WAKEUP>; 813 clock-names = "per", "ipg"; 814 dmas = <&edma2 14 0 0>, <&edma2 15 0 FSL_EDMA_RX>; 815 dma-names = "tx", "rx"; 816 status = "disabled"; 817 }; 818 819 lpuart3: serial@42570000 { 820 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 821 reg = <0x42570000 0x1000>; 822 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 823 clocks = <&clk IMX93_CLK_LPUART3_GATE>; 824 clock-names = "ipg"; 825 dmas = <&edma2 18 0 FSL_EDMA_RX>, <&edma2 17 0 0>; 826 dma-names = "rx", "tx"; 827 status = "disabled"; 828 }; 829 830 lpuart4: serial@42580000 { 831 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 832 reg = <0x42580000 0x1000>; 833 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 834 clocks = <&clk IMX93_CLK_LPUART4_GATE>; 835 clock-names = "ipg"; 836 dmas = <&edma2 20 0 FSL_EDMA_RX>, <&edma2 19 0 0>; 837 dma-names = "rx", "tx"; 838 status = "disabled"; 839 }; 840 841 lpuart5: serial@42590000 { 842 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 843 reg = <0x42590000 0x1000>; 844 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 845 clocks = <&clk IMX93_CLK_LPUART5_GATE>; 846 clock-names = "ipg"; 847 dmas = <&edma2 22 0 FSL_EDMA_RX>, <&edma2 21 0 0>; 848 dma-names = "rx", "tx"; 849 status = "disabled"; 850 }; 851 852 lpuart6: serial@425a0000 { 853 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 854 reg = <0x425a0000 0x1000>; 855 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 856 clocks = <&clk IMX93_CLK_LPUART6_GATE>; 857 clock-names = "ipg"; 858 dmas = <&edma2 24 0 FSL_EDMA_RX>, <&edma2 23 0 0>; 859 dma-names = "rx", "tx"; 860 status = "disabled"; 861 }; 862 863 flexcan2: can@425b0000 { 864 compatible = "fsl,imx93-flexcan"; 865 reg = <0x425b0000 0x10000>; 866 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 867 clocks = <&clk IMX93_CLK_BUS_WAKEUP>, 868 <&clk IMX93_CLK_CAN2_GATE>; 869 clock-names = "ipg", "per"; 870 assigned-clocks = <&clk IMX93_CLK_CAN2>; 871 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; 872 assigned-clock-rates = <40000000>; 873 fsl,clk-source = /bits/ 8 <0>; 874 fsl,stop-mode = <&wakeupmix_gpr 0x0c 2>; 875 status = "disabled"; 876 }; 877 878 flexspi1: spi@425e0000 { 879 compatible = "nxp,imx8mm-fspi"; 880 reg = <0x425e0000 0x10000>, <0x28000000 0x10000000>; 881 reg-names = "fspi_base", "fspi_mmap"; 882 #address-cells = <1>; 883 #size-cells = <0>; 884 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 885 clocks = <&clk IMX93_CLK_FLEXSPI1_GATE>, 886 <&clk IMX93_CLK_FLEXSPI1_GATE>; 887 clock-names = "fspi_en", "fspi"; 888 assigned-clocks = <&clk IMX93_CLK_FLEXSPI1>; 889 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; 890 status = "disabled"; 891 }; 892 893 sai2: sai@42650000 { 894 compatible = "fsl,imx93-sai"; 895 reg = <0x42650000 0x10000>; 896 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 897 clocks = <&clk IMX93_CLK_SAI2_IPG>, <&clk IMX93_CLK_DUMMY>, 898 <&clk IMX93_CLK_SAI2_GATE>, <&clk IMX93_CLK_DUMMY>, 899 <&clk IMX93_CLK_DUMMY>; 900 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 901 dmas = <&edma2 59 0 FSL_EDMA_RX>, <&edma2 58 0 0>; 902 dma-names = "rx", "tx"; 903 #sound-dai-cells = <0>; 904 status = "disabled"; 905 }; 906 907 sai3: sai@42660000 { 908 compatible = "fsl,imx93-sai"; 909 reg = <0x42660000 0x10000>; 910 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 911 clocks = <&clk IMX93_CLK_SAI3_IPG>, <&clk IMX93_CLK_DUMMY>, 912 <&clk IMX93_CLK_SAI3_GATE>, <&clk IMX93_CLK_DUMMY>, 913 <&clk IMX93_CLK_DUMMY>; 914 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 915 dmas = <&edma2 61 0 FSL_EDMA_RX>, <&edma2 60 0 0>; 916 dma-names = "rx", "tx"; 917 #sound-dai-cells = <0>; 918 status = "disabled"; 919 }; 920 921 xcvr: xcvr@42680000 { 922 compatible = "fsl,imx93-xcvr"; 923 reg = <0x42680000 0x800>, 924 <0x42680800 0x400>, 925 <0x42680c00 0x080>, 926 <0x42680e00 0x080>; 927 reg-names = "ram", "regs", "rxfifo", "txfifo"; 928 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 930 clocks = <&clk IMX93_CLK_SPDIF_IPG>, 931 <&clk IMX93_CLK_SPDIF_GATE>, 932 <&clk IMX93_CLK_DUMMY>, 933 <&clk IMX93_CLK_AUD_XCVR_GATE>; 934 clock-names = "ipg", "phy", "spba", "pll_ipg"; 935 dmas = <&edma2 65 0 FSL_EDMA_RX>, <&edma2 66 0 0>; 936 dma-names = "rx", "tx"; 937 #sound-dai-cells = <0>; 938 status = "disabled"; 939 }; 940 941 lpuart7: serial@42690000 { 942 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 943 reg = <0x42690000 0x1000>; 944 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; 945 clocks = <&clk IMX93_CLK_LPUART7_GATE>; 946 clock-names = "ipg"; 947 dmas = <&edma2 88 0 FSL_EDMA_RX>, <&edma2 87 0 0>; 948 dma-names = "rx", "tx"; 949 status = "disabled"; 950 }; 951 952 lpuart8: serial@426a0000 { 953 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 954 reg = <0x426a0000 0x1000>; 955 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; 956 clocks = <&clk IMX93_CLK_LPUART8_GATE>; 957 clock-names = "ipg"; 958 dmas = <&edma2 90 0 FSL_EDMA_RX>, <&edma2 89 0 0>; 959 dma-names = "rx", "tx"; 960 status = "disabled"; 961 }; 962 963 lpi2c5: i2c@426b0000 { 964 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 965 reg = <0x426b0000 0x10000>; 966 #address-cells = <1>; 967 #size-cells = <0>; 968 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 969 clocks = <&clk IMX93_CLK_LPI2C5_GATE>, 970 <&clk IMX93_CLK_BUS_WAKEUP>; 971 clock-names = "per", "ipg"; 972 dmas = <&edma2 71 0 0>, <&edma2 72 0 FSL_EDMA_RX>; 973 dma-names = "tx", "rx"; 974 status = "disabled"; 975 }; 976 977 lpi2c6: i2c@426c0000 { 978 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 979 reg = <0x426c0000 0x10000>; 980 #address-cells = <1>; 981 #size-cells = <0>; 982 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 983 clocks = <&clk IMX93_CLK_LPI2C6_GATE>, 984 <&clk IMX93_CLK_BUS_WAKEUP>; 985 clock-names = "per", "ipg"; 986 dmas = <&edma2 73 0 0>, <&edma2 74 0 FSL_EDMA_RX>; 987 dma-names = "tx", "rx"; 988 status = "disabled"; 989 }; 990 991 lpi2c7: i2c@426d0000 { 992 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 993 reg = <0x426d0000 0x10000>; 994 #address-cells = <1>; 995 #size-cells = <0>; 996 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 997 clocks = <&clk IMX93_CLK_LPI2C7_GATE>, 998 <&clk IMX93_CLK_BUS_WAKEUP>; 999 clock-names = "per", "ipg"; 1000 dmas = <&edma2 75 0 0>, <&edma2 76 0 FSL_EDMA_RX>; 1001 dma-names = "tx", "rx"; 1002 status = "disabled"; 1003 }; 1004 1005 lpi2c8: i2c@426e0000 { 1006 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 1007 reg = <0x426e0000 0x10000>; 1008 #address-cells = <1>; 1009 #size-cells = <0>; 1010 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 1011 clocks = <&clk IMX93_CLK_LPI2C8_GATE>, 1012 <&clk IMX93_CLK_BUS_WAKEUP>; 1013 clock-names = "per", "ipg"; 1014 dmas = <&edma2 77 0 0>, <&edma2 78 0 FSL_EDMA_RX>; 1015 dma-names = "tx", "rx"; 1016 status = "disabled"; 1017 }; 1018 1019 lpspi5: spi@426f0000 { 1020 #address-cells = <1>; 1021 #size-cells = <0>; 1022 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 1023 reg = <0x426f0000 0x10000>; 1024 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 1025 clocks = <&clk IMX93_CLK_LPSPI5_GATE>, 1026 <&clk IMX93_CLK_BUS_WAKEUP>; 1027 clock-names = "per", "ipg"; 1028 dmas = <&edma2 79 0 0>, <&edma2 80 0 FSL_EDMA_RX>; 1029 dma-names = "tx", "rx"; 1030 status = "disabled"; 1031 }; 1032 1033 lpspi6: spi@42700000 { 1034 #address-cells = <1>; 1035 #size-cells = <0>; 1036 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 1037 reg = <0x42700000 0x10000>; 1038 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 1039 clocks = <&clk IMX93_CLK_LPSPI6_GATE>, 1040 <&clk IMX93_CLK_BUS_WAKEUP>; 1041 clock-names = "per", "ipg"; 1042 dmas = <&edma2 81 0 0>, <&edma2 82 0 FSL_EDMA_RX>; 1043 dma-names = "tx", "rx"; 1044 status = "disabled"; 1045 }; 1046 1047 lpspi7: spi@42710000 { 1048 #address-cells = <1>; 1049 #size-cells = <0>; 1050 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 1051 reg = <0x42710000 0x10000>; 1052 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 1053 clocks = <&clk IMX93_CLK_LPSPI7_GATE>, 1054 <&clk IMX93_CLK_BUS_WAKEUP>; 1055 clock-names = "per", "ipg"; 1056 dmas = <&edma2 83 0 0>, <&edma2 84 0 FSL_EDMA_RX>; 1057 dma-names = "tx", "rx"; 1058 status = "disabled"; 1059 }; 1060 1061 lpspi8: spi@42720000 { 1062 #address-cells = <1>; 1063 #size-cells = <0>; 1064 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 1065 reg = <0x42720000 0x10000>; 1066 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 1067 clocks = <&clk IMX93_CLK_LPSPI8_GATE>, 1068 <&clk IMX93_CLK_BUS_WAKEUP>; 1069 clock-names = "per", "ipg"; 1070 dmas = <&edma2 85 0 0>, <&edma2 86 0 FSL_EDMA_RX>; 1071 dma-names = "tx", "rx"; 1072 status = "disabled"; 1073 }; 1074 1075 }; 1076 1077 aips3: bus@42800000 { 1078 compatible = "fsl,aips-bus", "simple-bus"; 1079 reg = <0x42800000 0x800000>; 1080 #address-cells = <1>; 1081 #size-cells = <1>; 1082 ranges; 1083 1084 usdhc1: mmc@42850000 { 1085 compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; 1086 reg = <0x42850000 0x10000>; 1087 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1088 clocks = <&clk IMX93_CLK_BUS_WAKEUP>, 1089 <&clk IMX93_CLK_WAKEUP_AXI>, 1090 <&clk IMX93_CLK_USDHC1_GATE>; 1091 clock-names = "ipg", "ahb", "per"; 1092 assigned-clocks = <&clk IMX93_CLK_USDHC1>; 1093 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; 1094 assigned-clock-rates = <400000000>; 1095 bus-width = <8>; 1096 fsl,tuning-start-tap = <1>; 1097 fsl,tuning-step = <2>; 1098 status = "disabled"; 1099 }; 1100 1101 usdhc2: mmc@42860000 { 1102 compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; 1103 reg = <0x42860000 0x10000>; 1104 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1105 clocks = <&clk IMX93_CLK_BUS_WAKEUP>, 1106 <&clk IMX93_CLK_WAKEUP_AXI>, 1107 <&clk IMX93_CLK_USDHC2_GATE>; 1108 clock-names = "ipg", "ahb", "per"; 1109 assigned-clocks = <&clk IMX93_CLK_USDHC2>; 1110 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; 1111 assigned-clock-rates = <400000000>; 1112 bus-width = <4>; 1113 fsl,tuning-start-tap = <1>; 1114 fsl,tuning-step = <2>; 1115 status = "disabled"; 1116 }; 1117 1118 fec: ethernet@42890000 { 1119 compatible = "fsl,imx93-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; 1120 reg = <0x42890000 0x10000>; 1121 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 1122 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 1123 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1124 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 1125 clocks = <&clk IMX93_CLK_ENET1_GATE>, 1126 <&clk IMX93_CLK_ENET1_GATE>, 1127 <&clk IMX93_CLK_ENET_TIMER1>, 1128 <&clk IMX93_CLK_ENET_REF>, 1129 <&clk IMX93_CLK_ENET_REF_PHY>; 1130 clock-names = "ipg", "ahb", "ptp", 1131 "enet_clk_ref", "enet_out"; 1132 assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>, 1133 <&clk IMX93_CLK_ENET_REF>, 1134 <&clk IMX93_CLK_ENET_REF_PHY>; 1135 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, 1136 <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>, 1137 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; 1138 assigned-clock-rates = <100000000>, <250000000>, <50000000>; 1139 fsl,num-tx-queues = <3>; 1140 fsl,num-rx-queues = <3>; 1141 fsl,stop-mode = <&wakeupmix_gpr 0x0c 1>; 1142 nvmem-cells = <ð_mac1>; 1143 nvmem-cell-names = "mac-address"; 1144 status = "disabled"; 1145 }; 1146 1147 eqos: ethernet@428a0000 { 1148 compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a"; 1149 reg = <0x428a0000 0x10000>; 1150 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1151 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 1152 interrupt-names = "macirq", "eth_wake_irq"; 1153 clocks = <&clk IMX93_CLK_ENET_QOS_GATE>, 1154 <&clk IMX93_CLK_ENET_QOS_GATE>, 1155 <&clk IMX93_CLK_ENET_TIMER2>, 1156 <&clk IMX93_CLK_ENET>, 1157 <&clk IMX93_CLK_ENET_QOS_GATE>; 1158 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem"; 1159 assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>, 1160 <&clk IMX93_CLK_ENET>; 1161 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, 1162 <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>; 1163 assigned-clock-rates = <100000000>, <250000000>; 1164 intf_mode = <&wakeupmix_gpr 0x28>; 1165 snps,clk-csr = <6>; 1166 nvmem-cells = <ð_mac2>; 1167 nvmem-cell-names = "mac-address"; 1168 status = "disabled"; 1169 }; 1170 1171 usdhc3: mmc@428b0000 { 1172 compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; 1173 reg = <0x428b0000 0x10000>; 1174 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 1175 clocks = <&clk IMX93_CLK_BUS_WAKEUP>, 1176 <&clk IMX93_CLK_WAKEUP_AXI>, 1177 <&clk IMX93_CLK_USDHC3_GATE>; 1178 clock-names = "ipg", "ahb", "per"; 1179 assigned-clocks = <&clk IMX93_CLK_USDHC3>; 1180 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; 1181 assigned-clock-rates = <400000000>; 1182 bus-width = <4>; 1183 fsl,tuning-start-tap = <1>; 1184 fsl,tuning-step = <2>; 1185 status = "disabled"; 1186 }; 1187 }; 1188 1189 gpio2: gpio@43810000 { 1190 compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio"; 1191 reg = <0x43810000 0x1000>; 1192 gpio-controller; 1193 #gpio-cells = <2>; 1194 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1195 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 1196 interrupt-controller; 1197 #interrupt-cells = <2>; 1198 clocks = <&clk IMX93_CLK_GPIO2_GATE>, 1199 <&clk IMX93_CLK_GPIO2_GATE>; 1200 clock-names = "gpio", "port"; 1201 gpio-ranges = <&iomuxc 0 4 30>; 1202 ngpios = <30>; 1203 }; 1204 1205 gpio3: gpio@43820000 { 1206 compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio"; 1207 reg = <0x43820000 0x1000>; 1208 gpio-controller; 1209 #gpio-cells = <2>; 1210 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 1211 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1212 interrupt-controller; 1213 #interrupt-cells = <2>; 1214 clocks = <&clk IMX93_CLK_GPIO3_GATE>, 1215 <&clk IMX93_CLK_GPIO3_GATE>; 1216 clock-names = "gpio", "port"; 1217 gpio-ranges = <&iomuxc 0 84 8>, <&iomuxc 8 66 18>, 1218 <&iomuxc 26 34 2>, <&iomuxc 28 0 4>; 1219 ngpios = <32>; 1220 }; 1221 1222 gpio4: gpio@43830000 { 1223 compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio"; 1224 reg = <0x43830000 0x1000>; 1225 gpio-controller; 1226 #gpio-cells = <2>; 1227 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1229 interrupt-controller; 1230 #interrupt-cells = <2>; 1231 clocks = <&clk IMX93_CLK_GPIO4_GATE>, 1232 <&clk IMX93_CLK_GPIO4_GATE>; 1233 clock-names = "gpio", "port"; 1234 gpio-ranges = <&iomuxc 0 38 28>, <&iomuxc 28 36 2>; 1235 ngpios = <30>; 1236 }; 1237 1238 gpio1: gpio@47400000 { 1239 compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio"; 1240 reg = <0x47400000 0x1000>; 1241 gpio-controller; 1242 #gpio-cells = <2>; 1243 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 1244 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1245 interrupt-controller; 1246 #interrupt-cells = <2>; 1247 clocks = <&clk IMX93_CLK_GPIO1_GATE>, 1248 <&clk IMX93_CLK_GPIO1_GATE>; 1249 clock-names = "gpio", "port"; 1250 gpio-ranges = <&iomuxc 0 92 16>; 1251 ngpios = <16>; 1252 }; 1253 1254 ocotp: efuse@47510000 { 1255 compatible = "fsl,imx93-ocotp", "syscon"; 1256 reg = <0x47510000 0x10000>; 1257 #address-cells = <1>; 1258 #size-cells = <1>; 1259 1260 eth_mac1: mac-address@4ec { 1261 reg = <0x4ec 0x6>; 1262 }; 1263 1264 eth_mac2: mac-address@4f2 { 1265 reg = <0x4f2 0x6>; 1266 }; 1267 1268 }; 1269 1270 s4muap: mailbox@47520000 { 1271 compatible = "fsl,imx93-mu-s4"; 1272 reg = <0x47520000 0x10000>; 1273 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 1274 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1275 interrupt-names = "tx", "rx"; 1276 #mbox-cells = <2>; 1277 }; 1278 1279 media_blk_ctrl: system-controller@4ac10000 { 1280 compatible = "fsl,imx93-media-blk-ctrl", "syscon"; 1281 reg = <0x4ac10000 0x10000>; 1282 power-domains = <&mediamix>; 1283 clocks = <&clk IMX93_CLK_MEDIA_APB>, 1284 <&clk IMX93_CLK_MEDIA_AXI>, 1285 <&clk IMX93_CLK_NIC_MEDIA_GATE>, 1286 <&clk IMX93_CLK_MEDIA_DISP_PIX>, 1287 <&clk IMX93_CLK_CAM_PIX>, 1288 <&clk IMX93_CLK_PXP_GATE>, 1289 <&clk IMX93_CLK_LCDIF_GATE>, 1290 <&clk IMX93_CLK_ISI_GATE>, 1291 <&clk IMX93_CLK_MIPI_CSI_GATE>, 1292 <&clk IMX93_CLK_MIPI_DSI_GATE>; 1293 clock-names = "apb", "axi", "nic", "disp", "cam", 1294 "pxp", "lcdif", "isi", "csi", "dsi"; 1295 #power-domain-cells = <1>; 1296 status = "disabled"; 1297 }; 1298 1299 usbotg1: usb@4c100000 { 1300 compatible = "fsl,imx93-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; 1301 reg = <0x4c100000 0x200>; 1302 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 1303 clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>, 1304 <&clk IMX93_CLK_HSIO_32K_GATE>; 1305 clock-names = "usb_ctrl_root", "usb_wakeup"; 1306 assigned-clocks = <&clk IMX93_CLK_HSIO>; 1307 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; 1308 assigned-clock-rates = <133000000>; 1309 phys = <&usbphynop1>; 1310 fsl,usbmisc = <&usbmisc1 0>; 1311 status = "disabled"; 1312 }; 1313 1314 usbmisc1: usbmisc@4c100200 { 1315 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc", 1316 "fsl,imx6q-usbmisc"; 1317 reg = <0x4c100200 0x200>; 1318 #index-cells = <1>; 1319 }; 1320 1321 usbotg2: usb@4c200000 { 1322 compatible = "fsl,imx93-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; 1323 reg = <0x4c200000 0x200>; 1324 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 1325 clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>, 1326 <&clk IMX93_CLK_HSIO_32K_GATE>; 1327 clock-names = "usb_ctrl_root", "usb_wakeup"; 1328 assigned-clocks = <&clk IMX93_CLK_HSIO>; 1329 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; 1330 assigned-clock-rates = <133000000>; 1331 phys = <&usbphynop2>; 1332 fsl,usbmisc = <&usbmisc2 0>; 1333 status = "disabled"; 1334 }; 1335 1336 usbmisc2: usbmisc@4c200200 { 1337 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc", 1338 "fsl,imx6q-usbmisc"; 1339 reg = <0x4c200200 0x200>; 1340 #index-cells = <1>; 1341 }; 1342 1343 memory-controller@4e300000 { 1344 compatible = "nxp,imx9-memory-controller"; 1345 reg = <0x4e300000 0x800>, <0x4e301000 0x1000>; 1346 reg-names = "ctrl", "inject"; 1347 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1348 little-endian; 1349 }; 1350 1351 ddr-pmu@4e300dc0 { 1352 compatible = "fsl,imx93-ddr-pmu"; 1353 reg = <0x4e300dc0 0x200>; 1354 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1355 }; 1356 }; 1357}; 1358