1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2023 Gateworks Corporation 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/input/linux-event-codes.h> 8#include <dt-bindings/leds/common.h> 9#include <dt-bindings/net/ti-dp83867.h> 10 11/ { 12 aliases { 13 ethernet0 = &eqos; 14 }; 15 16 memory@40000000 { 17 device_type = "memory"; 18 reg = <0x0 0x40000000 0 0x80000000>; 19 }; 20 21 gpio-keys { 22 compatible = "gpio-keys"; 23 24 key-user-pb { 25 label = "user_pb"; 26 gpios = <&gpio 2 GPIO_ACTIVE_LOW>; 27 linux,code = <BTN_0>; 28 }; 29 30 key-user-pb1x { 31 label = "user_pb1x"; 32 linux,code = <BTN_1>; 33 interrupt-parent = <&gsc>; 34 interrupts = <0>; 35 }; 36 37 key-erased { 38 label = "key_erased"; 39 linux,code = <BTN_2>; 40 interrupt-parent = <&gsc>; 41 interrupts = <1>; 42 }; 43 44 key-eeprom-wp { 45 label = "eeprom_wp"; 46 linux,code = <BTN_3>; 47 interrupt-parent = <&gsc>; 48 interrupts = <2>; 49 }; 50 51 key-tamper { 52 label = "tamper"; 53 linux,code = <BTN_4>; 54 interrupt-parent = <&gsc>; 55 interrupts = <5>; 56 }; 57 58 switch-hold { 59 label = "switch_hold"; 60 linux,code = <BTN_5>; 61 interrupt-parent = <&gsc>; 62 interrupts = <7>; 63 }; 64 }; 65}; 66 67&A53_0 { 68 cpu-supply = <&buck3_reg>; 69}; 70 71&A53_1 { 72 cpu-supply = <&buck3_reg>; 73}; 74 75&A53_2 { 76 cpu-supply = <&buck3_reg>; 77}; 78 79&A53_3 { 80 cpu-supply = <&buck3_reg>; 81}; 82 83&eqos { 84 pinctrl-names = "default"; 85 pinctrl-0 = <&pinctrl_eqos>; 86 phy-mode = "rgmii-id"; 87 phy-handle = <ðphy0>; 88 status = "okay"; 89 90 mdio { 91 compatible = "snps,dwmac-mdio"; 92 #address-cells = <1>; 93 #size-cells = <0>; 94 95 ethphy0: ethernet-phy@0 { 96 compatible = "ethernet-phy-ieee802.3-c22"; 97 pinctrl-0 = <&pinctrl_ethphy0>; 98 pinctrl-names = "default"; 99 reg = <0x0>; 100 interrupt-parent = <&gpio3>; 101 interrupts = <16 IRQ_TYPE_EDGE_FALLING>; 102 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 103 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 104 tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 105 rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 106 107 leds { 108 #address-cells = <1>; 109 #size-cells = <0>; 110 111 led@1 { 112 reg = <1>; 113 color = <LED_COLOR_ID_AMBER>; 114 function = LED_FUNCTION_LAN; 115 default-state = "keep"; 116 }; 117 118 led@2 { 119 reg = <2>; 120 color = <LED_COLOR_ID_GREEN>; 121 function = LED_FUNCTION_LAN; 122 default-state = "keep"; 123 }; 124 }; 125 }; 126 }; 127}; 128 129&i2c1 { 130 clock-frequency = <100000>; 131 pinctrl-names = "default", "gpio"; 132 pinctrl-0 = <&pinctrl_i2c1>; 133 pinctrl-1 = <&pinctrl_i2c1_gpio>; 134 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 135 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 136 status = "okay"; 137 138 gsc: gsc@20 { 139 compatible = "gw,gsc"; 140 reg = <0x20>; 141 pinctrl-0 = <&pinctrl_gsc>; 142 interrupt-parent = <&gpio2>; 143 interrupts = <6 IRQ_TYPE_EDGE_FALLING>; 144 interrupt-controller; 145 #interrupt-cells = <1>; 146 #address-cells = <1>; 147 #size-cells = <0>; 148 149 adc { 150 compatible = "gw,gsc-adc"; 151 #address-cells = <1>; 152 #size-cells = <0>; 153 154 channel@6 { 155 gw,mode = <0>; 156 reg = <0x06>; 157 label = "temp"; 158 }; 159 160 channel@8 { 161 gw,mode = <3>; 162 reg = <0x08>; 163 label = "vdd_bat"; 164 }; 165 166 channel@16 { 167 gw,mode = <4>; 168 reg = <0x16>; 169 label = "fan_tach"; 170 }; 171 172 channel@82 { 173 gw,mode = <2>; 174 reg = <0x82>; 175 label = "vdd_vin"; 176 gw,voltage-divider-ohms = <22100 1000>; 177 }; 178 179 channel@84 { 180 gw,mode = <2>; 181 reg = <0x84>; 182 label = "vdd_adc1"; 183 gw,voltage-divider-ohms = <10000 10000>; 184 }; 185 186 channel@86 { 187 gw,mode = <2>; 188 reg = <0x86>; 189 label = "vdd_adc2"; 190 gw,voltage-divider-ohms = <10000 10000>; 191 }; 192 193 channel@88 { 194 gw,mode = <2>; 195 reg = <0x88>; 196 label = "vdd_1p0"; 197 }; 198 199 channel@8c { 200 gw,mode = <2>; 201 reg = <0x8c>; 202 label = "vdd_1p8"; 203 }; 204 205 channel@8e { 206 gw,mode = <2>; 207 reg = <0x8e>; 208 label = "vdd_2p5"; 209 }; 210 211 channel@90 { 212 gw,mode = <2>; 213 reg = <0x90>; 214 label = "vdd_3p3"; 215 gw,voltage-divider-ohms = <10000 10000>; 216 }; 217 218 channel@92 { 219 gw,mode = <2>; 220 reg = <0x92>; 221 label = "vdd_dram"; 222 }; 223 224 channel@98 { 225 gw,mode = <2>; 226 reg = <0x98>; 227 label = "vdd_soc"; 228 }; 229 230 channel@9a { 231 gw,mode = <2>; 232 reg = <0x9a>; 233 label = "vdd_arm"; 234 }; 235 236 channel@a2 { 237 gw,mode = <2>; 238 reg = <0xa2>; 239 label = "vdd_gsc"; 240 gw,voltage-divider-ohms = <10000 10000>; 241 }; 242 }; 243 244 fan-controller@0 { 245 compatible = "gw,gsc-fan"; 246 reg = <0x0a>; 247 }; 248 }; 249 250 gpio: gpio@23 { 251 compatible = "nxp,pca9555"; 252 reg = <0x23>; 253 gpio-controller; 254 #gpio-cells = <2>; 255 interrupt-parent = <&gsc>; 256 interrupts = <4>; 257 }; 258 259 eeprom@50 { 260 compatible = "atmel,24c02"; 261 reg = <0x50>; 262 pagesize = <16>; 263 }; 264 265 eeprom@51 { 266 compatible = "atmel,24c02"; 267 reg = <0x51>; 268 pagesize = <16>; 269 }; 270 271 eeprom@52 { 272 compatible = "atmel,24c02"; 273 reg = <0x52>; 274 pagesize = <16>; 275 }; 276 277 eeprom@53 { 278 compatible = "atmel,24c02"; 279 reg = <0x53>; 280 pagesize = <16>; 281 }; 282 283 rtc@68 { 284 compatible = "dallas,ds1672"; 285 reg = <0x68>; 286 }; 287 288 pmic@69 { 289 compatible = "mps,mp5416"; 290 reg = <0x69>; 291 292 regulators { 293 /* vdd_soc */ 294 buck1 { 295 regulator-name = "buck1"; 296 regulator-min-microvolt = <850000>; 297 regulator-max-microvolt = <1000000>; 298 regulator-always-on; 299 regulator-boot-on; 300 }; 301 302 /* vdd_dram */ 303 buck2 { 304 regulator-name = "buck2"; 305 regulator-min-microvolt = <1100000>; 306 regulator-max-microvolt = <1100000>; 307 regulator-always-on; 308 regulator-boot-on; 309 }; 310 311 /* vdd_arm */ 312 buck3_reg: buck3 { 313 regulator-name = "buck3"; 314 regulator-min-microvolt = <850000>; 315 regulator-max-microvolt = <1000000>; 316 regulator-always-on; 317 regulator-boot-on; 318 }; 319 320 /* vdd_1p8 */ 321 buck4 { 322 regulator-name = "buck4"; 323 regulator-min-microvolt = <1800000>; 324 regulator-max-microvolt = <1800000>; 325 regulator-always-on; 326 regulator-boot-on; 327 }; 328 329 /* OUT2: nvcc_snvs_1p8 */ 330 ldo1 { 331 regulator-name = "ldo1"; 332 regulator-min-microvolt = <1800000>; 333 regulator-max-microvolt = <1800000>; 334 regulator-always-on; 335 regulator-boot-on; 336 }; 337 338 /* OUT3: vdd_1p0 */ 339 ldo2 { 340 regulator-name = "ldo2"; 341 regulator-min-microvolt = <1000000>; 342 regulator-max-microvolt = <1000000>; 343 regulator-always-on; 344 regulator-boot-on; 345 }; 346 347 /* OUT4: vdd_2p5 */ 348 ldo3 { 349 regulator-name = "ldo3"; 350 regulator-min-microvolt = <2500000>; 351 regulator-max-microvolt = <2500000>; 352 regulator-always-on; 353 regulator-boot-on; 354 }; 355 356 /* OUT5: vdd_3p3 */ 357 ldo4 { 358 regulator-name = "ldo4"; 359 regulator-min-microvolt = <3300000>; 360 regulator-max-microvolt = <3300000>; 361 regulator-always-on; 362 regulator-boot-on; 363 }; 364 }; 365 }; 366}; 367 368/* off-board header */ 369&i2c2 { 370 clock-frequency = <400000>; 371 pinctrl-names = "default", "gpio"; 372 pinctrl-0 = <&pinctrl_i2c2>; 373 pinctrl-1 = <&pinctrl_i2c2_gpio>; 374 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 375 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 376 status = "okay"; 377 378 eeprom@52 { 379 compatible = "atmel,24c32"; 380 reg = <0x52>; 381 pagesize = <32>; 382 }; 383}; 384 385/* off-board header */ 386&i2c3 { 387 clock-frequency = <400000>; 388 pinctrl-names = "default", "gpio"; 389 pinctrl-0 = <&pinctrl_i2c3>; 390 pinctrl-1 = <&pinctrl_i2c3_gpio>; 391 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 392 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 393 status = "okay"; 394}; 395 396/* off-board header */ 397&uart1 { 398 pinctrl-names = "default"; 399 pinctrl-0 = <&pinctrl_uart1>; 400 status = "okay"; 401}; 402 403/* console */ 404&uart2 { 405 pinctrl-names = "default"; 406 pinctrl-0 = <&pinctrl_uart2>; 407 status = "okay"; 408}; 409 410/* off-board header */ 411&uart3 { 412 pinctrl-names = "default"; 413 pinctrl-0 = <&pinctrl_uart3>; 414 status = "okay"; 415}; 416 417/* off-board */ 418&usdhc1 { 419 pinctrl-names = "default"; 420 pinctrl-0 = <&pinctrl_usdhc1>; 421 bus-width = <4>; 422 non-removable; 423 status = "okay"; 424 bus-width = <4>; 425 non-removable; 426 status = "okay"; 427}; 428 429/* eMMC */ 430&usdhc3 { 431 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 432 pinctrl-0 = <&pinctrl_usdhc3>; 433 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 434 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 435 bus-width = <8>; 436 non-removable; 437 status = "okay"; 438}; 439 440&wdog1 { 441 pinctrl-names = "default"; 442 pinctrl-0 = <&pinctrl_wdog>; 443 fsl,ext-reset-output; 444 status = "okay"; 445}; 446 447&iomuxc { 448 pinctrl_eqos: eqosgrp { 449 fsl,pins = < 450 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 451 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 452 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 453 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 454 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 455 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 456 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 457 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 458 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 459 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 460 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 461 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 462 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 463 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 464 >; 465 }; 466 467 pinctrl_ethphy0: ethphy0grp { 468 fsl,pins = < 469 MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x140 /* RST# */ 470 MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x150 /* IRQ# */ 471 >; 472 }; 473 474 pinctrl_gsc: gscgrp { 475 fsl,pins = < 476 MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x150 /* IRQ# */ 477 >; 478 }; 479 480 pinctrl_i2c1: i2c1grp { 481 fsl,pins = < 482 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 483 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 484 >; 485 }; 486 487 pinctrl_i2c1_gpio: i2c1gpiogrp { 488 fsl,pins = < 489 MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c2 490 MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c2 491 >; 492 }; 493 494 pinctrl_i2c2: i2c2grp { 495 fsl,pins = < 496 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 497 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 498 >; 499 }; 500 501 pinctrl_i2c2_gpio: i2c2gpiogrp { 502 fsl,pins = < 503 MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c2 504 MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c2 505 >; 506 }; 507 508 pinctrl_i2c3: i2c3grp { 509 fsl,pins = < 510 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 511 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 512 >; 513 }; 514 515 pinctrl_i2c3_gpio: i2c3gpiogrp { 516 fsl,pins = < 517 MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c2 518 MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c2 519 >; 520 }; 521 522 pinctrl_uart1: uart1grp { 523 fsl,pins = < 524 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 525 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 526 >; 527 }; 528 529 pinctrl_uart2: uart2grp { 530 fsl,pins = < 531 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 532 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 533 >; 534 }; 535 536 pinctrl_uart3: uart3grp { 537 fsl,pins = < 538 MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140 539 MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140 540 >; 541 }; 542 543 pinctrl_usdhc1: usdhc1grp { 544 fsl,pins = < 545 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 546 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 547 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 548 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 549 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 550 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 551 >; 552 }; 553 554 pinctrl_usdhc3: usdhc3grp { 555 fsl,pins = < 556 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 557 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 558 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 559 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 560 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 561 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 562 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 563 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 564 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 565 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 566 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 567 >; 568 }; 569 570 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 571 fsl,pins = < 572 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 573 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 574 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 575 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 576 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 577 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 578 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 579 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 580 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 581 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 582 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 583 >; 584 }; 585 586 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 587 fsl,pins = < 588 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 589 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 590 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 591 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 592 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 593 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 594 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 595 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 596 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 597 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 598 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 599 >; 600 }; 601 602 pinctrl_wdog: wdoggrp { 603 fsl,pins = < 604 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 605 >; 606 }; 607}; 608