xref: /freebsd/sys/contrib/device-tree/src/arm/nxp/imx/imx6ull-dhcor-som.dtsi (revision f126890ac5386406dadf7c4cfa9566cbb56537c5) 
1// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2/*
3 * Copyright (C) 2023 DH electronics GmbH
4 */
5
6#include <dt-bindings/clock/imx6ul-clock.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/input/input.h>
9#include <dt-bindings/leds/common.h>
10#include <dt-bindings/pwm/pwm.h>
11#include <dt-bindings/regulator/dlg,da9063-regulator.h>
12#include "imx6ull.dtsi"
13
14/ {
15	aliases {
16		/delete-property/ mmc0;
17		/delete-property/ mmc1;
18	};
19
20	memory@80000000 {
21		/* Appropriate memory size will be filled by U-Boot */
22		reg = <0x80000000 0>;
23		device_type = "memory";
24	};
25};
26
27&cpu0 {
28	/*
29	 * Due to the design as a solderable SOM, there are no capacitors
30	 * below the SoC, therefore higher voltages are required.
31	 */
32	operating-points = <
33		/* kHz	uV */
34		900000	1275000
35		792000	1250000 /* Voltage increased */
36		528000	1175000
37		396000	1025000
38		198000	950000
39	>;
40	fsl,soc-operating-points = <
41		/* KHz	uV */
42		900000	1250000
43		792000	1250000 /* Voltage increased */
44		528000	1175000
45		396000	1175000
46		198000	1175000
47	>;
48};
49
50&gpio1 {
51	pinctrl-0 = <&pinctrl_spi1_switch>;
52	pinctrl-names = "default";
53	/*
54	 * Pin SPI_BOOT_FLASH_EN (GPIO 1.9) is a switch for either using the
55	 * DHCOM SPI1 interface or accessing the SPI bootflash. Both using
56	 * ecspi1, but muxed to different pins. The DHCOM SPI1 interface uses
57	 * the pins PAD_LCD_DATA21..23 and the SPI bootflash uses the pins
58	 * PAD_CSI_DATA04..07. If the SPI bootflash is enabled the pins for
59	 * DHCOM GPIOs N/O/P/Q/R/S/T/U aren't usable anymore, because they
60	 * are used for the bus interface to the SPI bootflash. The GPIOs are
61	 * disconnected by a buffer which is also controlled via the pin
62	 * SPI_BOOT_FLASH_EN. Therefore the access to the bootflash is a
63	 * special case and is disabled by setting GPIO 1.9 to high.
64	 */
65	spi1-switch-hog {
66		gpio-hog;
67		gpios = <9 0>;
68		output-high;
69		line-name = "spi1-switch";
70	};
71};
72
73&i2c1 {
74	clock-frequency = <100000>;
75	pinctrl-0 = <&pinctrl_i2c1>;
76	pinctrl-1 = <&pinctrl_i2c1_gpio>;
77	pinctrl-names = "default", "gpio";
78	scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
79	sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
80	status = "okay";
81
82	pmic@58 {
83		compatible = "dlg,da9061";
84		reg = <0x58>;
85
86		onkey {
87			compatible = "dlg,da9061-onkey", "dlg,da9062-onkey";
88			status = "disabled";
89		};
90
91		regulators {
92			vdd_soc_in_1v4: buck1 {
93				regulator-allowed-modes = <DA9063_BUCK_MODE_SLEEP>; /* PFM */
94				regulator-always-on;
95				regulator-boot-on;
96				regulator-initial-mode = <DA9063_BUCK_MODE_SLEEP>;
97				regulator-max-microvolt = <1400000>;
98				regulator-min-microvolt = <1400000>;
99				regulator-name = "vdd_soc_in_1v4";
100			};
101
102			vcc_3v3: buck2 {
103				regulator-allowed-modes = <DA9063_BUCK_MODE_SYNC>; /* PWM */
104				regulator-always-on;
105				regulator-boot-on;
106				regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>;
107				regulator-max-microvolt = <3300000>;
108				regulator-min-microvolt = <3300000>;
109				regulator-name = "vcc_3v3";
110			};
111
112			/*
113			 * The current DRR3 memory can be supplied with a
114			 * voltage of either 1.35V or 1.5V. For reasons of
115			 * backward compatibility to only 1.5V DDR3 memory,
116			 * the voltage is set to 1.5V.
117			 */
118			vcc_ddr_1v35: buck3 {
119				regulator-allowed-modes = <DA9063_BUCK_MODE_SYNC>; /* PWM */
120				regulator-always-on;
121				regulator-boot-on;
122				regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>;
123				regulator-max-microvolt = <1500000>;
124				regulator-min-microvolt = <1500000>;
125				regulator-name = "vcc_ddr_1v35";
126			};
127
128			vcc_2v5: ldo1 {
129				regulator-always-on;
130				regulator-boot-on;
131				regulator-max-microvolt = <2500000>;
132				regulator-min-microvolt = <2500000>;
133				regulator-name = "vcc_2v5";
134			};
135
136			vdd_snvs_in_3v3: ldo2 {
137				regulator-always-on;
138				regulator-boot-on;
139				regulator-max-microvolt = <3300000>;
140				regulator-min-microvolt = <3300000>;
141				regulator-name = "vdd_snvs_in_3v3";
142			};
143
144			vcc_1v8: ldo3 {
145				regulator-always-on;
146				regulator-boot-on;
147				regulator-max-microvolt = <1800000>;
148				regulator-min-microvolt = <1800000>;
149				regulator-name = "vcc_1v8";
150			};
151
152			vcc_1v2: ldo4 {
153				regulator-always-on;
154				regulator-boot-on;
155				regulator-max-microvolt = <1200000>;
156				regulator-min-microvolt = <1200000>;
157				regulator-name = "vcc_1v2";
158			};
159		};
160
161		thermal {
162			compatible = "dlg,da9061-thermal", "dlg,da9062-thermal";
163			status = "disabled";
164		};
165
166		watchdog {
167			compatible = "dlg,da9061-watchdog", "dlg,da9062-watchdog";
168			status = "disabled";
169		};
170	};
171};
172
173&ocotp {
174	/* Don't get write access by default */
175	read-only;
176};
177
178&reg_arm {
179	vin-supply = <&vdd_soc_in_1v4>;
180};
181
182&reg_soc {
183	vin-supply = <&vdd_soc_in_1v4>;
184};
185
186/* BT on LGA (BT_REG_ON is connected to LGA pin E1) */
187&uart2 {
188	pinctrl-0 = <&pinctrl_uart2>;
189	pinctrl-names = "default";
190	uart-has-rtscts;
191	status = "okay";
192
193	/*
194	 * Actually, the maximum speed of the chip is 4MBdps, but there are
195	 * limitations that prevent this speed. It hasn't yet been figured out
196	 * what the reason for this is. Currently, the maximum speed of 3MBdps
197	 * can be used without any problems. If the limitation can be overcome,
198	 * the speed can be increased accordingly.
199	 */
200	bluetooth: bluetooth {
201		compatible = "brcm,bcm43430a1-bt"; /* muRata 1DX */
202		max-speed = <3000000>;
203		vbat-supply = <&vcc_3v3>;
204		vddio-supply = <&vcc_3v3>;
205	};
206};
207
208/* WiFi on LGA (WL_REG_ON is connected to LGA pin E3) */
209&usdhc1 {
210	#address-cells = <1>;
211	#size-cells = <0>;
212	bus-width = <4>;
213	no-1-8-v;
214	non-removable;
215	keep-power-in-suspend;
216	pinctrl-0 = <&pinctrl_usdhc1_wifi>;
217	pinctrl-names = "default";
218	wakeup-source;
219	status = "okay";
220
221	brcmf: wifi@1 {
222		compatible = "brcm,bcm43430a1-fmac", "brcm,bcm4329-fmac"; /* muRata 1DX */
223		reg = <1>;
224	};
225};
226
227&iomuxc {
228	pinctrl_i2c1: i2c1-grp {
229		fsl,pins = <
230			MX6UL_PAD_UART4_TX_DATA__I2C1_SCL	0x4001b8b0
231			MX6UL_PAD_UART4_RX_DATA__I2C1_SDA	0x4001b8b0
232		>;
233	};
234
235	pinctrl_i2c1_gpio: i2c1-gpio-grp {
236		fsl,pins = <
237			MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28	0x4001b8b0
238			MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29	0x4001b8b0
239		>;
240	};
241
242	pinctrl_spi1_switch: spi1-switch-grp {
243		fsl,pins = <
244			MX6UL_PAD_GPIO1_IO09__GPIO1_IO09	0x120b0 /* SPI_BOOT_FLASH_EN */
245		>;
246	};
247
248	pinctrl_uart2: uart2-grp {
249		fsl,pins = <
250			MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX	0x1b0b1
251			MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX	0x1b0b1
252			MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS	0x1b0b1
253			MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS	0x1b0b1
254		>;
255	};
256
257	pinctrl_usdhc1_wifi: usdhc1-wifi-grp {
258		fsl,pins = <
259			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x1b0b0
260			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x10010
261			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x1b0b0
262			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x1b0b0
263			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x1b0b0
264			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x1b0b0
265		>;
266	};
267};
268