1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * Copyright 2014-2022 Toradex 4 * Copyright 2012 Freescale Semiconductor, Inc. 5 * Copyright 2011 Linaro Ltd. 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/pwm/pwm.h> 10 11/ { 12 model = "Toradex Apalis iMX6Q/D Module"; 13 14 aliases { 15 mmc0 = &usdhc3; /* eMMC */ 16 mmc1 = &usdhc1; /* MMC1 slot */ 17 mmc2 = &usdhc2; /* SD1 slot */ 18 /delete-property/ mmc3; 19 }; 20 21 /* Will be filled by the bootloader */ 22 memory@10000000 { 23 device_type = "memory"; 24 reg = <0x10000000 0>; 25 }; 26 27 backlight: backlight { 28 compatible = "pwm-backlight"; 29 brightness-levels = <0 45 63 88 119 158 203 255>; 30 default-brightness-level = <4>; 31 enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; 32 pinctrl-names = "default"; 33 pinctrl-0 = <&pinctrl_gpio_bl_on>; 34 power-supply = <®_module_3v3>; 35 pwms = <&pwm4 0 5000000 PWM_POLARITY_INVERTED>; 36 status = "disabled"; 37 }; 38 39 clk_ov5640_osc: clk-ov5640-osc { 40 compatible = "fixed-clock"; 41 #clock-cells = <0>; 42 clock-frequency = <24000000>; 43 }; 44 45 gpio-keys { 46 compatible = "gpio-keys"; 47 pinctrl-names = "default"; 48 pinctrl-0 = <&pinctrl_gpio_keys>; 49 50 key-wakeup { 51 debounce-interval = <10>; 52 gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; 53 label = "Wake-Up"; 54 linux,code = <KEY_WAKEUP>; 55 wakeup-source; 56 }; 57 }; 58 59 lcd_display: disp0 { 60 compatible = "fsl,imx-parallel-display"; 61 #address-cells = <1>; 62 #size-cells = <0>; 63 interface-pix-fmt = "rgb24"; 64 pinctrl-names = "default"; 65 pinctrl-0 = <&pinctrl_ipu1_lcdif>; 66 status = "disabled"; 67 68 port@0 { 69 reg = <0>; 70 71 lcd_display_in: endpoint { 72 remote-endpoint = <&ipu1_di1_disp1>; 73 }; 74 }; 75 76 port@1 { 77 reg = <1>; 78 79 lcd_display_out: endpoint { 80 remote-endpoint = <&lcd_panel_in>; 81 }; 82 }; 83 }; 84 85 panel_dpi: panel-dpi { 86 compatible = "edt,et057090dhu"; 87 backlight = <&backlight>; 88 89 status = "disabled"; 90 91 port { 92 lcd_panel_in: endpoint { 93 remote-endpoint = <&lcd_display_out>; 94 }; 95 }; 96 }; 97 98 panel_lvds: panel-lvds { 99 compatible = "panel-lvds"; 100 backlight = <&backlight>; 101 status = "disabled"; 102 103 port { 104 lvds_panel_in: endpoint { 105 remote-endpoint = <&lvds0_out>; 106 }; 107 }; 108 }; 109 110 poweroff { 111 compatible = "regulator-poweroff"; 112 cpu-supply = <&vgen2_reg>; 113 }; 114 115 reg_module_3v3: regulator-module-3v3 { 116 compatible = "regulator-fixed"; 117 regulator-always-on; 118 regulator-max-microvolt = <3300000>; 119 regulator-min-microvolt = <3300000>; 120 regulator-name = "+V3.3"; 121 }; 122 123 reg_module_3v3_audio: regulator-module-3v3-audio { 124 compatible = "regulator-fixed"; 125 regulator-always-on; 126 regulator-max-microvolt = <3300000>; 127 regulator-min-microvolt = <3300000>; 128 regulator-name = "+V3.3_AUDIO"; 129 }; 130 131 reg_ov5640_1v8_d_o_vdd: regulator-ov5640-1v8-d-o-vdd { 132 compatible = "regulator-fixed"; 133 regulator-always-on; 134 regulator-max-microvolt = <1800000>; 135 regulator-min-microvolt = <1800000>; 136 regulator-name = "DOVDD/DVDD_1.8V"; 137 /* Note: The CSI module uses on-board 3.3V_SW supply */ 138 vin-supply = <®_module_3v3>; 139 }; 140 141 reg_ov5640_2v8_a_vdd: regulator-ov5640-2v8-a-vdd { 142 compatible = "regulator-fixed"; 143 regulator-always-on; 144 regulator-max-microvolt = <2800000>; 145 regulator-min-microvolt = <2800000>; 146 regulator-name = "AVDD/AFVDD_2.8V"; 147 /* Note: The CSI module uses on-board 3.3V_SW supply */ 148 vin-supply = <®_module_3v3>; 149 }; 150 151 reg_usb_otg_vbus: regulator-usb-otg-vbus { 152 compatible = "regulator-fixed"; 153 enable-active-high; 154 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 155 pinctrl-names = "default"; 156 pinctrl-0 = <&pinctrl_regulator_usbotg_pwr>; 157 regulator-max-microvolt = <5000000>; 158 regulator-min-microvolt = <5000000>; 159 regulator-name = "usb_otg_vbus"; 160 status = "disabled"; 161 }; 162 163 /* on module USB hub */ 164 reg_usb_host_vbus_hub: regulator-usb-host-vbus-hub { 165 compatible = "regulator-fixed"; 166 enable-active-high; 167 gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>; 168 pinctrl-names = "default"; 169 pinctrl-0 = <&pinctrl_regulator_usbhub_pwr>; 170 regulator-max-microvolt = <5000000>; 171 regulator-min-microvolt = <5000000>; 172 regulator-name = "usb_host_vbus_hub"; 173 startup-delay-us = <2000>; 174 status = "okay"; 175 }; 176 177 reg_usb_host_vbus: regulator-usb-host-vbus { 178 compatible = "regulator-fixed"; 179 enable-active-high; 180 gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; 181 pinctrl-names = "default"; 182 pinctrl-0 = <&pinctrl_regulator_usbh_pwr>; 183 regulator-max-microvolt = <5000000>; 184 regulator-min-microvolt = <5000000>; 185 regulator-name = "usb_host_vbus"; 186 vin-supply = <®_usb_host_vbus_hub>; 187 status = "disabled"; 188 }; 189 190 sound { 191 compatible = "fsl,imx-audio-sgtl5000"; 192 audio-codec = <&codec>; 193 audio-routing = 194 "LINE_IN", "Line In Jack", 195 "MIC_IN", "Mic Jack", 196 "Mic Jack", "Mic Bias", 197 "Headphone Jack", "HP_OUT"; 198 model = "apalis-imx6"; 199 mux-ext-port = <4>; 200 mux-int-port = <1>; 201 ssi-controller = <&ssi1>; 202 }; 203 204 spdif_out: spdif-out { 205 compatible = "linux,spdif-dit"; 206 #sound-dai-cells = <0>; 207 }; 208 209 spdif_in: spdif-in { 210 compatible = "linux,spdif-dir"; 211 #sound-dai-cells = <0>; 212 }; 213 214 sound_spdif: sound-spdif { 215 compatible = "fsl,imx-audio-spdif"; 216 audio-cpu = <&spdif>; 217 audio-codec = <&spdif_out>, <&spdif_in>; 218 model = "imx-spdif"; 219 status = "disabled"; 220 }; 221}; 222 223&audmux { 224 pinctrl-names = "default"; 225 pinctrl-0 = <&pinctrl_audmux>; 226 status = "okay"; 227}; 228 229&can1 { 230 pinctrl-names = "default", "sleep"; 231 pinctrl-0 = <&pinctrl_flexcan1_default>; 232 pinctrl-1 = <&pinctrl_flexcan1_sleep>; 233 status = "disabled"; 234}; 235 236&can2 { 237 pinctrl-names = "default", "sleep"; 238 pinctrl-0 = <&pinctrl_flexcan2_default>; 239 pinctrl-1 = <&pinctrl_flexcan2_sleep>; 240 status = "disabled"; 241}; 242 243/* Apalis SPI1 */ 244&ecspi1 { 245 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; 246 pinctrl-names = "default"; 247 pinctrl-0 = <&pinctrl_ecspi1>; 248 status = "disabled"; 249}; 250 251/* Apalis SPI2 */ 252&ecspi2 { 253 cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; 254 pinctrl-names = "default"; 255 pinctrl-0 = <&pinctrl_ecspi2>; 256 status = "disabled"; 257}; 258 259&gpio1 { 260 gpio-line-names = "MXM3_84", 261 "MXM3_4", 262 "MXM3_15/GPIO7", 263 "MXM3_96", 264 "MXM3_37", 265 "", 266 "MXM3_17/GPIO8", 267 "MXM3_14", 268 "MXM3_12", 269 "MXM3_2", 270 "MXM3_184", 271 "MXM3_180", 272 "MXM3_178", 273 "MXM3_176", 274 "MXM3_188", 275 "MXM3_186", 276 "MXM3_160", 277 "MXM3_162", 278 "MXM3_150", 279 "MXM3_144", 280 "MXM3_154", 281 "MXM3_146", 282 "", 283 "", 284 "MXM3_72"; 285}; 286 287&gpio2 { 288 gpio-line-names = "MXM3_148", 289 "MXM3_152", 290 "MXM3_156", 291 "MXM3_158", 292 "MXM3_1/GPIO1", 293 "MXM3_3/GPIO2", 294 "MXM3_5/GPIO3", 295 "MXM3_7/GPIO4", 296 "MXM3_95", 297 "MXM3_6", 298 "MXM3_8", 299 "MXM3_123", 300 "MXM3_126", 301 "MXM3_128", 302 "MXM3_130", 303 "MXM3_132", 304 "MXM3_253", 305 "MXM3_251", 306 "MXM3_283", 307 "MXM3_281", 308 "MXM3_279", 309 "MXM3_277", 310 "MXM3_243", 311 "MXM3_235", 312 "MXM3_231", 313 "MXM3_229", 314 "MXM3_233", 315 "MXM3_198", 316 "MXM3_275", 317 "MXM3_273", 318 "MXM3_207", 319 "MXM3_122"; 320}; 321 322&gpio3 { 323 gpio-line-names = "MXM3_271", 324 "MXM3_269", 325 "MXM3_301", 326 "MXM3_299", 327 "MXM3_297", 328 "MXM3_295", 329 "MXM3_293", 330 "MXM3_291", 331 "MXM3_289", 332 "MXM3_287", 333 "MXM3_249", 334 "MXM3_247", 335 "MXM3_245", 336 "MXM3_286", 337 "MXM3_239", 338 "MXM3_35", 339 "MXM3_205", 340 "MXM3_203", 341 "MXM3_201", 342 "MXM3_116", 343 "MXM3_114", 344 "MXM3_262", 345 "MXM3_274", 346 "MXM3_124", 347 "MXM3_110", 348 "MXM3_120", 349 "MXM3_263", 350 "MXM3_265", 351 "", 352 "MXM3_135", 353 "MXM3_261", 354 "MXM3_259"; 355}; 356 357&gpio4 { 358 gpio-line-names = "", 359 "", 360 "", 361 "", 362 "", 363 "MXM3_194", 364 "MXM3_136", 365 "MXM3_134", 366 "MXM3_140", 367 "MXM3_138", 368 "", 369 "MXM3_220", 370 "", 371 "", 372 "MXM3_18", 373 "MXM3_16", 374 "", 375 "", 376 "MXM3_214", 377 "MXM3_216", 378 "MXM3_164"; 379}; 380 381&gpio5 { 382 gpio-line-names = "MXM3_159", 383 "", 384 "", 385 "", 386 "MXM3_257", 387 "", 388 "", 389 "", 390 "", 391 "", 392 "MXM3_200", 393 "MXM3_196", 394 "MXM3_204", 395 "MXM3_202", 396 "", 397 "", 398 "", 399 "", 400 "MXM3_191", 401 "MXM3_197", 402 "MXM3_77", 403 "MXM3_195", 404 "MXM3_221", 405 "MXM3_225", 406 "MXM3_223", 407 "MXM3_227", 408 "MXM3_209", 409 "MXM3_211", 410 "MXM3_118", 411 "MXM3_112", 412 "MXM3_187", 413 "MXM3_185"; 414}; 415 416&gpio6 { 417 gpio-line-names = "MXM3_183", 418 "MXM3_181", 419 "MXM3_179", 420 "MXM3_177", 421 "MXM3_175", 422 "MXM3_173", 423 "MXM3_255", 424 "MXM3_83", 425 "MXM3_91", 426 "MXM3_13/GPIO6", 427 "MXM3_11/GPIO5", 428 "MXM3_79", 429 "", 430 "", 431 "MXM3_190", 432 "MXM3_193", 433 "MXM3_89"; 434}; 435 436&gpio7 { 437 gpio-line-names = "", 438 "", 439 "", 440 "", 441 "", 442 "", 443 "", 444 "", 445 "", 446 "MXM3_99", 447 "MXM3_85", 448 "MXM3_217", 449 "MXM3_215"; 450}; 451 452&gpr { 453 ipu1_csi0_mux { 454 #address-cells = <1>; 455 #size-cells = <0>; 456 status = "disabled"; 457 458 port@1 { 459 reg = <1>; 460 ipu1_csi0_mux_from_parallel_sensor: endpoint { 461 remote-endpoint = <&adv7280_to_ipu1_csi0_mux>; 462 }; 463 }; 464 }; 465}; 466 467&fec { 468 pinctrl-names = "default"; 469 pinctrl-0 = <&pinctrl_enet>; 470 phy-mode = "rgmii-id"; 471 phy-handle = <ðphy>; 472 phy-reset-duration = <10>; 473 phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; 474 status = "okay"; 475 476 mdio { 477 #address-cells = <1>; 478 #size-cells = <0>; 479 480 ethphy: ethernet-phy@7 { 481 interrupt-parent = <&gpio1>; 482 interrupts = <30 IRQ_TYPE_LEVEL_LOW>; 483 reg = <7>; 484 }; 485 }; 486}; 487 488&hdmi { 489 pinctrl-names = "default"; 490 pinctrl-0 = <&pinctrl_hdmi_ddc &pinctrl_hdmi_cec>; 491 status = "disabled"; 492}; 493 494/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */ 495&i2c1 { 496 clock-frequency = <100000>; 497 pinctrl-names = "default", "gpio"; 498 pinctrl-0 = <&pinctrl_i2c1>; 499 pinctrl-1 = <&pinctrl_i2c1_gpio>; 500 scl-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 501 sda-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 502 status = "disabled"; 503 504 atmel_mxt_ts: touchscreen@4a { 505 compatible = "atmel,maxtouch"; 506 /* These GPIOs are muxed with the iomuxc node */ 507 interrupt-parent = <&gpio6>; 508 interrupts = <10 IRQ_TYPE_EDGE_FALLING>; /* MXM3_11 */ 509 reg = <0x4a>; 510 reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; /* MXM3_13 */ 511 status = "disabled"; 512 }; 513}; 514 515/* 516 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and 517 * touch screen controller 518 */ 519&i2c2 { 520 clock-frequency = <100000>; 521 pinctrl-names = "default", "gpio"; 522 pinctrl-0 = <&pinctrl_i2c2>; 523 pinctrl-1 = <&pinctrl_i2c2_gpio>; 524 scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 525 sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 526 status = "okay"; 527 528 pmic: pmic@8 { 529 compatible = "fsl,pfuze100"; 530 reg = <0x08>; 531 532 regulators { 533 sw1a_reg: sw1ab { 534 regulator-always-on; 535 regulator-boot-on; 536 regulator-max-microvolt = <1875000>; 537 regulator-min-microvolt = <300000>; 538 regulator-ramp-delay = <6250>; 539 }; 540 541 sw1c_reg: sw1c { 542 regulator-always-on; 543 regulator-boot-on; 544 regulator-max-microvolt = <1875000>; 545 regulator-min-microvolt = <300000>; 546 regulator-ramp-delay = <6250>; 547 }; 548 549 sw3a_reg: sw3a { 550 regulator-always-on; 551 regulator-boot-on; 552 regulator-max-microvolt = <1975000>; 553 regulator-min-microvolt = <400000>; 554 }; 555 556 swbst_reg: swbst { 557 regulator-always-on; 558 regulator-boot-on; 559 regulator-max-microvolt = <5150000>; 560 regulator-min-microvolt = <5000000>; 561 }; 562 563 snvs_reg: vsnvs { 564 regulator-always-on; 565 regulator-boot-on; 566 regulator-max-microvolt = <3000000>; 567 regulator-min-microvolt = <1000000>; 568 }; 569 570 vref_reg: vrefddr { 571 regulator-always-on; 572 regulator-boot-on; 573 }; 574 575 vgen1_reg: vgen1 { 576 regulator-always-on; 577 regulator-boot-on; 578 regulator-max-microvolt = <1550000>; 579 regulator-min-microvolt = <800000>; 580 }; 581 582 vgen2_reg: vgen2 { 583 regulator-always-on; 584 regulator-boot-on; 585 regulator-max-microvolt = <1550000>; 586 regulator-min-microvolt = <800000>; 587 }; 588 589 vgen3_reg: vgen3 { 590 regulator-always-on; 591 regulator-boot-on; 592 regulator-max-microvolt = <3300000>; 593 regulator-min-microvolt = <1800000>; 594 }; 595 596 vgen4_reg: vgen4 { 597 regulator-always-on; 598 regulator-boot-on; 599 regulator-max-microvolt = <1800000>; 600 regulator-min-microvolt = <1800000>; 601 }; 602 603 vgen5_reg: vgen5 { 604 regulator-always-on; 605 regulator-boot-on; 606 regulator-max-microvolt = <3300000>; 607 regulator-min-microvolt = <1800000>; 608 }; 609 610 vgen6_reg: vgen6 { 611 regulator-always-on; 612 regulator-boot-on; 613 regulator-max-microvolt = <3300000>; 614 regulator-min-microvolt = <1800000>; 615 }; 616 }; 617 }; 618 619 codec: sgtl5000@a { 620 compatible = "fsl,sgtl5000"; 621 #sound-dai-cells = <0>; 622 clocks = <&clks IMX6QDL_CLK_CKO>; 623 pinctrl-names = "default"; 624 pinctrl-0 = <&pinctrl_sgtl5000>; 625 reg = <0x0a>; 626 VDDA-supply = <®_module_3v3_audio>; 627 VDDIO-supply = <®_module_3v3>; 628 VDDD-supply = <&vgen4_reg>; 629 }; 630 631 /* STMPE811 touch screen controller */ 632 stmpe811@41 { 633 compatible = "st,stmpe811"; 634 blocks = <0x5>; 635 id = <0>; 636 interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 637 interrupt-parent = <&gpio4>; 638 irq-trigger = <0x1>; 639 pinctrl-names = "default"; 640 pinctrl-0 = <&pinctrl_touch_int>; 641 reg = <0x41>; 642 /* 3.25 MHz ADC clock speed */ 643 st,adc-freq = <1>; 644 /* 12-bit ADC */ 645 st,mod-12b = <1>; 646 /* internal ADC reference */ 647 st,ref-sel = <0>; 648 /* ADC conversion time: 80 clocks */ 649 st,sample-time = <4>; 650 651 stmpe_ts: stmpe_touchscreen { 652 compatible = "st,stmpe-ts"; 653 /* 8 sample average control */ 654 st,ave-ctrl = <3>; 655 /* 7 length fractional part in z */ 656 st,fraction-z = <7>; 657 /* 658 * 50 mA typical 80 mA max touchscreen drivers 659 * current limit value 660 */ 661 st,i-drive = <1>; 662 /* 1 ms panel driver settling time */ 663 st,settling = <3>; 664 /* 5 ms touch detect interrupt delay */ 665 st,touch-det-delay = <5>; 666 }; 667 668 stmpe_adc: stmpe_adc { 669 compatible = "st,stmpe-adc"; 670 #io-channel-cells = <1>; 671 /* forbid to use ADC channels 3-0 (touch) */ 672 st,norequest-mask = <0x0F>; 673 }; 674 }; 675}; 676 677/* 678 * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier 679 * board) 680 */ 681&i2c3 { 682 clock-frequency = <100000>; 683 pinctrl-names = "default", "gpio"; 684 pinctrl-0 = <&pinctrl_i2c3>; 685 pinctrl-1 = <&pinctrl_i2c3_gpio>; 686 scl-gpios = <&gpio3 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 687 sda-gpios = <&gpio3 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 688 status = "disabled"; 689 690 adv_7280: adv7280@21 { 691 compatible = "adi,adv7280"; 692 adi,force-bt656-4; 693 pinctrl-names = "default"; 694 pinctrl-0 = <&pinctrl_ipu1_csi0>; 695 reg = <0x21>; 696 status = "disabled"; 697 698 port { 699 adv7280_to_ipu1_csi0_mux: endpoint { 700 bus-width = <8>; 701 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; 702 }; 703 }; 704 }; 705 706 ov5640_csi_cam: ov5640_mipi@3c { 707 compatible = "ovti,ov5640"; 708 AVDD-supply = <®_ov5640_2v8_a_vdd>; 709 DOVDD-supply = <®_ov5640_1v8_d_o_vdd>; 710 DVDD-supply = <®_ov5640_1v8_d_o_vdd>; 711 clock-names = "xclk"; 712 clocks = <&clks IMX6QDL_CLK_CKO2>; 713 pinctrl-names = "default"; 714 pinctrl-0 = <&pinctrl_cam_mclk>; 715 /* These GPIOs are muxed with the iomuxc node */ 716 powerdown-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; 717 reg = <0x3c>; 718 reset-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; 719 status = "disabled"; 720 721 port { 722 ov5640_to_mipi_csi2: endpoint { 723 clock-lanes = <0>; 724 data-lanes = <1 2>; 725 remote-endpoint = <&mipi_csi_from_ov5640>; 726 }; 727 }; 728 }; 729}; 730 731&ipu1_di1_disp1 { 732 remote-endpoint = <&lcd_display_in>; 733}; 734 735&ldb { 736 lvds-channel@0 { 737 port@4 { 738 reg = <4>; 739 740 lvds0_out: endpoint { 741 remote-endpoint = <&lvds_panel_in>; 742 }; 743 }; 744 }; 745 746 lvds-channel@1 { 747 fsl,data-mapping = "spwg"; 748 fsl,data-width = <18>; 749 750 port@4 { 751 reg = <4>; 752 753 lvds1_out: endpoint { 754 }; 755 }; 756 }; 757}; 758 759&mipi_csi { 760 #address-cells = <1>; 761 #size-cells = <0>; 762 status = "disabled"; 763 764 port@0 { 765 reg = <0>; 766 767 mipi_csi_from_ov5640: endpoint { 768 clock-lanes = <0>; 769 data-lanes = <1 2>; 770 remote-endpoint = <&ov5640_to_mipi_csi2>; 771 }; 772 }; 773}; 774 775&pwm1 { 776 pinctrl-names = "default"; 777 pinctrl-0 = <&pinctrl_pwm1>; 778 status = "disabled"; 779}; 780 781&pwm2 { 782 pinctrl-names = "default"; 783 pinctrl-0 = <&pinctrl_pwm2>; 784 status = "disabled"; 785}; 786 787&pwm3 { 788 pinctrl-names = "default"; 789 pinctrl-0 = <&pinctrl_pwm3>; 790 status = "disabled"; 791}; 792 793&pwm4 { 794 pinctrl-names = "default"; 795 pinctrl-0 = <&pinctrl_pwm4>; 796 status = "disabled"; 797}; 798 799&spdif { 800 pinctrl-names = "default"; 801 pinctrl-0 = <&pinctrl_spdif>; 802 status = "disabled"; 803}; 804 805&ssi1 { 806 status = "okay"; 807}; 808 809&uart1 { 810 fsl,dte-mode; 811 pinctrl-names = "default"; 812 pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>; 813 uart-has-rtscts; 814 status = "disabled"; 815}; 816 817&uart2 { 818 fsl,dte-mode; 819 pinctrl-names = "default"; 820 pinctrl-0 = <&pinctrl_uart2_dte>; 821 uart-has-rtscts; 822 status = "disabled"; 823}; 824 825&uart4 { 826 fsl,dte-mode; 827 pinctrl-names = "default"; 828 pinctrl-0 = <&pinctrl_uart4_dte>; 829 status = "disabled"; 830}; 831 832&uart5 { 833 fsl,dte-mode; 834 pinctrl-names = "default"; 835 pinctrl-0 = <&pinctrl_uart5_dte>; 836 status = "disabled"; 837}; 838 839&usbotg { 840 pinctrl-names = "default"; 841 pinctrl-0 = <&pinctrl_usbotg>; 842 status = "disabled"; 843}; 844 845/* MMC1 */ 846&usdhc1 { 847 bus-width = <8>; 848 cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; 849 disable-wp; 850 no-1-8-v; 851 pinctrl-names = "default"; 852 pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit &pinctrl_mmc_cd>; 853 vqmmc-supply = <®_module_3v3>; 854 status = "disabled"; 855}; 856 857/* SD1 */ 858&usdhc2 { 859 bus-width = <4>; 860 disable-wp; 861 no-1-8-v; 862 pinctrl-names = "default"; 863 pinctrl-0 = <&pinctrl_usdhc2>; 864 vqmmc-supply = <®_module_3v3>; 865 status = "disabled"; 866}; 867 868/* eMMC */ 869&usdhc3 { 870 bus-width = <8>; 871 no-1-8-v; 872 non-removable; 873 pinctrl-names = "default"; 874 pinctrl-0 = <&pinctrl_usdhc3>; 875 vqmmc-supply = <®_module_3v3>; 876 status = "okay"; 877}; 878 879&weim { 880 status = "disabled"; 881}; 882 883&iomuxc { 884 /* Mux the Apalis GPIOs */ 885 pinctrl-names = "default"; 886 pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2 887 &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4 888 &pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6 889 &pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8 890 >; 891 892 pinctrl_apalis_gpio1: apalisgpio1grp { 893 fsl,pins = < 894 MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x130b0 895 >; 896 }; 897 898 pinctrl_apalis_gpio2: apalisgpio2grp { 899 fsl,pins = < 900 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x130b0 901 >; 902 }; 903 904 pinctrl_apalis_gpio3: apalisgpio3grp { 905 fsl,pins = < 906 MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x130b0 907 >; 908 }; 909 910 pinctrl_apalis_gpio4: apalisgpio4grp { 911 fsl,pins = < 912 MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x130b0 913 >; 914 }; 915 916 pinctrl_apalis_gpio5: apalisgpio5grp { 917 fsl,pins = < 918 MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x130b0 919 >; 920 }; 921 922 pinctrl_apalis_gpio6: apalisgpio6grp { 923 fsl,pins = < 924 MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x130b0 925 >; 926 }; 927 928 pinctrl_apalis_gpio7: apalisgpio7grp { 929 fsl,pins = < 930 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b0 931 >; 932 }; 933 934 pinctrl_apalis_gpio8: apalisgpio8grp { 935 fsl,pins = < 936 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x130b0 937 >; 938 }; 939 940 pinctrl_audmux: audmuxgrp { 941 fsl,pins = < 942 MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 943 MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0 944 MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 945 MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 946 >; 947 }; 948 949 pinctrl_cam_mclk: cammclkgrp { 950 fsl,pins = < 951 /* CAM sys_mclk */ 952 MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0 953 >; 954 }; 955 956 pinctrl_ecspi1: ecspi1grp { 957 fsl,pins = < 958 MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x100b1 959 MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x100b1 960 MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x100b1 961 /* SPI1 cs */ 962 MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x000b1 963 >; 964 }; 965 966 pinctrl_ecspi2: ecspi2grp { 967 fsl,pins = < 968 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 969 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 970 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 971 /* SPI2 cs */ 972 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1 973 >; 974 }; 975 976 pinctrl_enet: enetgrp { 977 fsl,pins = < 978 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 979 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 980 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 981 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 982 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 983 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 984 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 985 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 986 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 987 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 988 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 989 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 990 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 991 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 992 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 993 /* Ethernet PHY reset */ 994 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x000b0 995 /* Ethernet PHY interrupt */ 996 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x000b1 997 >; 998 }; 999 1000 pinctrl_flexcan1_default: flexcan1defgrp { 1001 fsl,pins = < 1002 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 1003 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 1004 >; 1005 }; 1006 1007 pinctrl_flexcan1_sleep: flexcan1slpgrp { 1008 fsl,pins = < 1009 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0 1010 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0 1011 >; 1012 }; 1013 1014 pinctrl_flexcan2_default: flexcan2defgrp { 1015 fsl,pins = < 1016 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 1017 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 1018 >; 1019 }; 1020 pinctrl_flexcan2_sleep: flexcan2slpgrp { 1021 fsl,pins = < 1022 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x0 1023 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x0 1024 >; 1025 }; 1026 1027 pinctrl_gpio_bl_on: gpioblongrp { 1028 fsl,pins = < 1029 MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0 1030 >; 1031 }; 1032 1033 pinctrl_gpio_keys: gpio1io04grp { 1034 fsl,pins = < 1035 /* Power button */ 1036 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 1037 >; 1038 }; 1039 1040 pinctrl_hdmi_cec: hdmicecgrp { 1041 fsl,pins = < 1042 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 1043 >; 1044 }; 1045 1046 pinctrl_hdmi_ddc: hdmiddcgrp { 1047 fsl,pins = < 1048 MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1 1049 MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1 1050 >; 1051 }; 1052 1053 pinctrl_i2c1: i2c1grp { 1054 fsl,pins = < 1055 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 1056 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 1057 >; 1058 }; 1059 1060 pinctrl_i2c1_gpio: i2c1gpiogrp { 1061 fsl,pins = < 1062 MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x4001b8b1 1063 MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x4001b8b1 1064 >; 1065 }; 1066 1067 pinctrl_i2c2: i2c2grp { 1068 fsl,pins = < 1069 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 1070 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 1071 >; 1072 }; 1073 1074 pinctrl_i2c2_gpio: i2c2gpiogrp { 1075 fsl,pins = < 1076 MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 1077 MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 1078 >; 1079 }; 1080 1081 pinctrl_i2c3: i2c3grp { 1082 fsl,pins = < 1083 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 1084 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 1085 >; 1086 }; 1087 1088 pinctrl_i2c3_gpio: i2c3gpiogrp { 1089 fsl,pins = < 1090 MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x4001b8b1 1091 MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x4001b8b1 1092 >; 1093 }; 1094 1095 pinctrl_ipu1_csi0: ipu1csi0grp { /* parallel camera */ 1096 fsl,pins = < 1097 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0xb0b1 1098 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0xb0b1 1099 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0xb0b1 1100 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0xb0b1 1101 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0xb0b1 1102 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0xb0b1 1103 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0xb0b1 1104 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0xb0b1 1105 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1 1106 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0xb0b1 1107 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0xb0b1 1108 >; 1109 }; 1110 1111 pinctrl_ipu1_lcdif: ipu1lcdifgrp { 1112 fsl,pins = < 1113 MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x61 1114 /* DE */ 1115 MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x61 1116 /* HSync */ 1117 MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x61 1118 /* VSync */ 1119 MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x61 1120 MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x61 1121 MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x61 1122 MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x61 1123 MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x61 1124 MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x61 1125 MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x61 1126 MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x61 1127 MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x61 1128 MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x61 1129 MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x61 1130 MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x61 1131 MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x61 1132 MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x61 1133 MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x61 1134 MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x61 1135 MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x61 1136 MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x61 1137 MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x61 1138 MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x61 1139 MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x61 1140 MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x61 1141 MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x61 1142 MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x61 1143 MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x61 1144 >; 1145 }; 1146 1147 pinctrl_ipu2_vdac: ipu2vdacgrp { 1148 fsl,pins = < 1149 MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0xd1 1150 MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0xd1 1151 MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0xd1 1152 MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0xd1 1153 MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0xf9 1154 MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0xf9 1155 MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0xf9 1156 MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0xf9 1157 MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0xf9 1158 MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0xf9 1159 MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0xf9 1160 MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0xf9 1161 MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0xf9 1162 MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0xf9 1163 MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0xf9 1164 MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0xf9 1165 MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0xf9 1166 MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0xf9 1167 MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0xf9 1168 MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0xf9 1169 >; 1170 }; 1171 1172 pinctrl_mmc_cd: mmccdgrp { 1173 fsl,pins = < 1174 /* MMC1 CD */ 1175 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x000b0 1176 >; 1177 }; 1178 1179 pinctrl_pwm1: pwm1grp { 1180 fsl,pins = < 1181 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 1182 >; 1183 }; 1184 1185 pinctrl_pwm2: pwm2grp { 1186 fsl,pins = < 1187 MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 1188 >; 1189 }; 1190 1191 pinctrl_pwm3: pwm3grp { 1192 fsl,pins = < 1193 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 1194 >; 1195 }; 1196 1197 pinctrl_pwm4: pwm4grp { 1198 fsl,pins = < 1199 MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 1200 >; 1201 }; 1202 1203 pinctrl_regulator_usbh_pwr: regusbhpwrgrp { 1204 fsl,pins = < 1205 /* USBH_EN */ 1206 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x0f058 1207 >; 1208 }; 1209 1210 pinctrl_regulator_usbhub_pwr: regusbhubpwrgrp { 1211 fsl,pins = < 1212 /* USBH_HUB_EN */ 1213 MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0f058 1214 >; 1215 }; 1216 1217 pinctrl_regulator_usbotg_pwr: regusbotgpwrgrp { 1218 fsl,pins = < 1219 /* USBO1 power en */ 1220 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0f058 1221 >; 1222 }; 1223 1224 pinctrl_reset_moci: resetmocigrp { 1225 fsl,pins = < 1226 /* RESET_MOCI control */ 1227 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x0f058 1228 >; 1229 }; 1230 1231 pinctrl_sd_cd: sdcdgrp { 1232 fsl,pins = < 1233 /* SD1 CD */ 1234 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x000b0 1235 >; 1236 }; 1237 1238 pinctrl_sgtl5000: sgtl5000grp { 1239 fsl,pins = < 1240 MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0 1241 >; 1242 }; 1243 1244 pinctrl_spdif: spdifgrp { 1245 fsl,pins = < 1246 MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 1247 MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0 1248 >; 1249 }; 1250 1251 pinctrl_touch_int: touchintgrp { 1252 fsl,pins = < 1253 /* STMPE811 interrupt */ 1254 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 1255 >; 1256 }; 1257 1258 /* Additional DTR, DSR, DCD */ 1259 pinctrl_uart1_ctrl: uart1ctrlgrp { 1260 fsl,pins = < 1261 MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0 1262 MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0 1263 MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0 1264 >; 1265 }; 1266 1267 pinctrl_uart1_dce: uart1dcegrp { 1268 fsl,pins = < 1269 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 1270 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 1271 >; 1272 }; 1273 1274 /* DTE mode */ 1275 pinctrl_uart1_dte: uart1dtegrp { 1276 fsl,pins = < 1277 MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1 1278 MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1 1279 MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1 1280 MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1 1281 >; 1282 }; 1283 1284 pinctrl_uart2_dce: uart2dcegrp { 1285 fsl,pins = < 1286 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 1287 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 1288 >; 1289 }; 1290 1291 /* DTE mode */ 1292 pinctrl_uart2_dte: uart2dtegrp { 1293 fsl,pins = < 1294 MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1 1295 MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1 1296 MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1 1297 MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1 1298 >; 1299 }; 1300 1301 pinctrl_uart4_dce: uart4dcegrp { 1302 fsl,pins = < 1303 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 1304 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 1305 >; 1306 }; 1307 1308 /* DTE mode */ 1309 pinctrl_uart4_dte: uart4dtegrp { 1310 fsl,pins = < 1311 MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x1b0b1 1312 MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x1b0b1 1313 >; 1314 }; 1315 1316 pinctrl_uart5_dce: uart5dcegrp { 1317 fsl,pins = < 1318 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 1319 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 1320 >; 1321 }; 1322 1323 /* DTE mode */ 1324 pinctrl_uart5_dte: uart5dtegrp { 1325 fsl,pins = < 1326 MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x1b0b1 1327 MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x1b0b1 1328 >; 1329 }; 1330 1331 pinctrl_usbotg: usbotggrp { 1332 fsl,pins = < 1333 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 1334 >; 1335 }; 1336 1337 pinctrl_usdhc1_4bit: usdhc1-4bitgrp { 1338 fsl,pins = < 1339 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 1340 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 1341 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 1342 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 1343 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 1344 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 1345 >; 1346 }; 1347 1348 pinctrl_usdhc1_8bit: usdhc1-8bitgrp { 1349 fsl,pins = < 1350 MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17071 1351 MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17071 1352 MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17071 1353 MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17071 1354 >; 1355 }; 1356 1357 pinctrl_usdhc2: usdhc2grp { 1358 fsl,pins = < 1359 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 1360 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 1361 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 1362 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 1363 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 1364 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 1365 >; 1366 }; 1367 1368 pinctrl_usdhc3: usdhc3grp { 1369 fsl,pins = < 1370 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 1371 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 1372 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 1373 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 1374 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 1375 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 1376 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 1377 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 1378 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 1379 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 1380 /* eMMC reset */ 1381 MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 1382 >; 1383 }; 1384}; 1385