1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2019, 2020, 2025 Kevin Lo <kevlo@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* $OpenBSD: if_rgereg.h,v 1.15 2025/09/19 00:41:14 kevlo Exp $ */ 20 21 #ifndef __IF_RGEVAR_H__ 22 #define __IF_RGEVAR_H__ 23 24 #define RGE_LOCK(sc) (mtx_lock(&sc->sc_mtx)) 25 #define RGE_UNLOCK(sc) (mtx_unlock(&sc->sc_mtx)) 26 #define RGE_ASSERT_LOCKED(sc) (mtx_assert(&sc->sc_mtx, MA_OWNED)) 27 #define RGE_ASSERT_UNLOCKED(sc) (mtx_assert(&sc->sc_mtx, MA_NOTOWNED)) 28 29 enum rge_mac_type { 30 MAC_UNKNOWN = 1, 31 MAC_R25, 32 MAC_R25B, 33 MAC_R25D, 34 MAC_R26, 35 MAC_R27 36 }; 37 38 struct rge_drv_stats { 39 /* How many times if_transmit() was called */ 40 uint64_t transmit_call_cnt; 41 /* Transmitted frame failed because the interface was stopped */ 42 uint64_t transmit_stopped_cnt; 43 /* Transmitted frame failed because the TX queue is full */ 44 uint64_t transmit_full_cnt; 45 /* How many transmit frames were queued for transmit */ 46 uint64_t transmit_queued_cnt; 47 48 /* How many times the interrupt routine was called */ 49 uint64_t intr_cnt; 50 /* How many times SYSTEM_ERR was set, requiring a hardware reset */ 51 uint64_t intr_system_err_cnt; 52 /* How many times rge_rxeof was called */ 53 uint64_t rxeof_cnt; 54 /* How many times rge_txeof was called */ 55 uint64_t txeof_cnt; 56 57 /* How many times the link state changed */ 58 uint64_t link_state_change_cnt; 59 60 /* How many times tx_task was run */ 61 uint64_t tx_task_cnt; 62 63 /* Count of frames passed up into if_input() */ 64 uint64_t recv_input_cnt; 65 66 /* 67 * For now - driver doesn't support multi descriptor 68 * RX frames; so count if it happens so it'll be noticed. 69 */ 70 uint64_t rx_desc_err_multidesc; 71 72 /* 73 * Number of TX watchdog timeouts. 74 */ 75 uint64_t tx_watchdog_timeout_cnt; 76 77 uint64_t tx_encap_cnt; 78 uint64_t tx_encap_refrag_cnt; 79 uint64_t tx_encap_err_toofrag; 80 uint64_t tx_offload_ip_csum_set; 81 uint64_t tx_offload_tcp_csum_set; 82 uint64_t tx_offload_udp_csum_set; 83 uint64_t tx_offload_vlan_tag_set; 84 85 uint64_t rx_ether_csum_err; 86 uint64_t rx_desc_jumbo_frag; 87 uint64_t rx_offload_vlan_tag; 88 uint64_t rx_offload_csum_ipv4_exists; 89 uint64_t rx_offload_csum_ipv4_valid; 90 91 uint64_t rx_offload_csum_tcp_exists; 92 uint64_t rx_offload_csum_tcp_valid; 93 94 uint64_t rx_offload_csum_udp_exists; 95 uint64_t rx_offload_csum_udp_valid; 96 }; 97 98 struct rge_txq { 99 struct mbuf *txq_mbuf; 100 bus_dmamap_t txq_dmamap; 101 int txq_descidx; 102 }; 103 104 struct rge_rxq { 105 struct mbuf *rxq_mbuf; 106 bus_dmamap_t rxq_dmamap; 107 }; 108 109 struct rge_tx { 110 struct rge_txq rge_txq[RGE_TX_LIST_CNT]; 111 int rge_txq_prodidx; 112 int rge_txq_considx; 113 114 bus_addr_t rge_tx_list_paddr; 115 bus_dmamap_t rge_tx_list_map; 116 struct rge_tx_desc *rge_tx_list; 117 }; 118 119 struct rge_rx { 120 struct rge_rxq rge_rxq[RGE_RX_LIST_CNT]; 121 int rge_rxq_prodidx; 122 int rge_rxq_considx; 123 124 // struct if_rxring rge_rx_ring; 125 bus_addr_t rge_rx_list_paddr; 126 bus_dmamap_t rge_rx_list_map; 127 struct rge_rx_desc *rge_rx_list; 128 129 struct mbuf *rge_head; 130 struct mbuf **rge_tail; 131 }; 132 133 struct rge_queues { 134 struct rge_softc *q_sc; 135 void *q_ihc; 136 int q_index; 137 char q_name[16]; 138 // pci_intr_handle_t q_ih; 139 struct rge_tx q_tx; 140 struct rge_rx q_rx; 141 }; 142 143 struct rge_mac_stats { 144 bus_addr_t paddr; 145 bus_dmamap_t map; 146 /* NIC dma buffer, NIC order */ 147 struct rge_hw_mac_stats *stats; 148 149 /* Local copy for retrieval, host order */ 150 struct rge_hw_mac_stats lcl_stats; 151 }; 152 153 struct rge_softc { 154 device_t sc_dev; 155 if_t sc_ifp; /* Ethernet common data */ 156 bool sc_ether_attached; 157 struct mtx sc_mtx; 158 struct resource *sc_irq[RGE_MSI_MESSAGES]; 159 void *sc_ih[RGE_MSI_MESSAGES]; 160 uint32_t sc_expcap; /* PCe exp cap */ 161 struct resource *sc_bres; /* bus space MMIO/IOPORT resource */ 162 bus_space_handle_t rge_bhandle; /* bus space handle */ 163 bus_space_tag_t rge_btag; /* bus space tag */ 164 bus_size_t rge_bsize; 165 bus_dma_tag_t sc_dmat; 166 bus_dma_tag_t sc_dmat_tx_desc; 167 bus_dma_tag_t sc_dmat_tx_buf; 168 bus_dma_tag_t sc_dmat_rx_desc; 169 bus_dma_tag_t sc_dmat_rx_buf; 170 bus_dma_tag_t sc_dmat_stats_buf; 171 172 // pci_chipset_tag_t sc_pc; 173 // pcitag_t sc_tag; 174 struct ifmedia sc_media; /* media info */ 175 enum rge_mac_type rge_type; 176 177 struct rge_queues *sc_queues; 178 unsigned int sc_nqueues; 179 180 bool sc_detaching; 181 bool sc_stopped; 182 bool sc_suspended; 183 184 /* Note: these likely should be per-TXQ */ 185 struct mbufq sc_txq; 186 struct taskqueue * sc_tq; 187 char sc_tq_name[32]; 188 char sc_tq_thr_name[32]; 189 struct task sc_tx_task; 190 191 struct callout sc_timeout; /* 1 second tick */ 192 193 uint64_t rge_mcodever; 194 uint16_t rge_rcodever; 195 uint32_t rge_flags; 196 #define RGE_FLAG_MSI 0x00000001 197 #define RGE_FLAG_PCIE 0x00000002 198 199 uint32_t rge_intrs; 200 int rge_timerintr; 201 #define RGE_IMTYPE_NONE 0 202 #define RGE_IMTYPE_SIM 1 203 int sc_watchdog; 204 205 uint32_t sc_debug; 206 207 struct rge_drv_stats sc_drv_stats; 208 209 struct rge_mac_stats sc_mac_stats; 210 }; 211 212 /* 213 * Register space access macros. 214 */ 215 #define RGE_WRITE_4(sc, reg, val) \ 216 bus_space_write_4(sc->rge_btag, sc->rge_bhandle, reg, val) 217 #define RGE_WRITE_2(sc, reg, val) \ 218 bus_space_write_2(sc->rge_btag, sc->rge_bhandle, reg, val) 219 #define RGE_WRITE_1(sc, reg, val) \ 220 bus_space_write_1(sc->rge_btag, sc->rge_bhandle, reg, val) 221 222 #define RGE_WRITE_BARRIER_4(sc, reg) \ 223 bus_space_barrier(sc->rge_btag, sc->rge_bhandle, reg, 4, \ 224 BUS_SPACE_BARRIER_WRITE) 225 #define RGE_READ_BARRIER_4(sc, reg) \ 226 bus_space_barrier(sc->rge_btag, sc->rge_bhandle, reg, 4, \ 227 BUS_SPACE_BARRIER_READ) 228 229 230 #define RGE_READ_4(sc, reg) \ 231 bus_space_read_4(sc->rge_btag, sc->rge_bhandle, reg) 232 #define RGE_READ_2(sc, reg) \ 233 bus_space_read_2(sc->rge_btag, sc->rge_bhandle, reg) 234 #define RGE_READ_1(sc, reg) \ 235 bus_space_read_1(sc->rge_btag, sc->rge_bhandle, reg) 236 237 #define RGE_SETBIT_4(sc, reg, val) \ 238 RGE_WRITE_4(sc, reg, RGE_READ_4(sc, reg) | (val)) 239 #define RGE_SETBIT_2(sc, reg, val) \ 240 RGE_WRITE_2(sc, reg, RGE_READ_2(sc, reg) | (val)) 241 #define RGE_SETBIT_1(sc, reg, val) \ 242 RGE_WRITE_1(sc, reg, RGE_READ_1(sc, reg) | (val)) 243 244 #define RGE_CLRBIT_4(sc, reg, val) \ 245 RGE_WRITE_4(sc, reg, RGE_READ_4(sc, reg) & ~(val)) 246 #define RGE_CLRBIT_2(sc, reg, val) \ 247 RGE_WRITE_2(sc, reg, RGE_READ_2(sc, reg) & ~(val)) 248 #define RGE_CLRBIT_1(sc, reg, val) \ 249 RGE_WRITE_1(sc, reg, RGE_READ_1(sc, reg) & ~(val)) 250 251 #define RGE_EPHY_SETBIT(sc, reg, val) \ 252 rge_write_ephy(sc, reg, rge_read_ephy(sc, reg) | (val)) 253 254 #define RGE_EPHY_CLRBIT(sc, reg, val) \ 255 rge_write_ephy(sc, reg, rge_read_ephy(sc, reg) & ~(val)) 256 257 #define RGE_PHY_SETBIT(sc, reg, val) \ 258 rge_write_phy_ocp(sc, reg, rge_read_phy_ocp(sc, reg) | (val)) 259 260 #define RGE_PHY_CLRBIT(sc, reg, val) \ 261 rge_write_phy_ocp(sc, reg, rge_read_phy_ocp(sc, reg) & ~(val)) 262 263 #define RGE_MAC_SETBIT(sc, reg, val) \ 264 rge_write_mac_ocp(sc, reg, rge_read_mac_ocp(sc, reg) | (val)) 265 266 #define RGE_MAC_CLRBIT(sc, reg, val) \ 267 rge_write_mac_ocp(sc, reg, rge_read_mac_ocp(sc, reg) & ~(val)) 268 269 #endif /* __IF_RGEVAR_H__ */ 270