1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright(c) 2007-2025 Intel Corporation */ 3 #ifndef _ICP_QAT_FW_INIT_ADMIN_H_ 4 #define _ICP_QAT_FW_INIT_ADMIN_H_ 5 6 #include "icp_qat_fw.h" 7 8 enum icp_qat_fw_init_admin_cmd_id { 9 ICP_QAT_FW_INIT_ME = 0, 10 ICP_QAT_FW_TRNG_ENABLE = 1, 11 ICP_QAT_FW_TRNG_DISABLE = 2, 12 ICP_QAT_FW_CONSTANTS_CFG = 3, 13 ICP_QAT_FW_STATUS_GET = 4, 14 ICP_QAT_FW_COUNTERS_GET = 5, 15 ICP_QAT_FW_LOOPBACK = 6, 16 ICP_QAT_FW_HEARTBEAT_SYNC = 7, 17 ICP_QAT_FW_HEARTBEAT_GET = 8, 18 ICP_QAT_FW_COMP_CAPABILITY_GET = 9, 19 ICP_QAT_FW_CRYPTO_CAPABILITY_GET = 10, 20 ICP_QAT_FW_HEARTBEAT_TIMER_SET = 13, 21 ICP_QAT_FW_RL_SLA_CONFIG = 14, 22 ICP_QAT_FW_RL_INIT = 15, 23 ICP_QAT_FW_RL_DU_START = 16, 24 ICP_QAT_FW_RL_DU_STOP = 17, 25 ICP_QAT_FW_TIMER_GET = 19, 26 ICP_QAT_FW_CNV_STATS_GET = 20, 27 ICP_QAT_FW_PKE_REPLAY_STATS_GET = 21 28 }; 29 30 enum icp_qat_fw_init_admin_resp_status { 31 ICP_QAT_FW_INIT_RESP_STATUS_SUCCESS = 0, 32 ICP_QAT_FW_INIT_RESP_STATUS_FAIL = 1, 33 ICP_QAT_FW_INIT_RESP_STATUS_UNSUPPORTED = 4 34 }; 35 36 enum icp_qat_fw_cnv_error_type { 37 CNV_ERR_TYPE_NO_ERROR = 0, 38 CNV_ERR_TYPE_CHECKSUM_ERROR, 39 CNV_ERR_TYPE_DECOMP_PRODUCED_LENGTH_ERROR, 40 CNV_ERR_TYPE_DECOMPRESSION_ERROR, 41 CNV_ERR_TYPE_TRANSLATION_ERROR, 42 CNV_ERR_TYPE_DECOMP_CONSUMED_LENGTH_ERROR, 43 CNV_ERR_TYPE_UNKNOWN_ERROR 44 }; 45 46 #define ICP_QAT_FW_INIT_DISABLE_SAFE_DC_MODE_FLAG 0x02 47 48 #define CNV_ERROR_TYPE_GET(latest_error) \ 49 ({ \ 50 __typeof__(latest_error) _lerror = latest_error; \ 51 (_lerror >> 12) > CNV_ERR_TYPE_UNKNOWN_ERROR ? \ 52 CNV_ERR_TYPE_UNKNOWN_ERROR : \ 53 (enum icp_qat_fw_cnv_error_type)(_lerror >> 12); \ 54 }) 55 #define CNV_ERROR_LENGTH_DELTA_GET(latest_error) \ 56 ({ \ 57 __typeof__(latest_error) _lerror = latest_error; \ 58 ((s16)((_lerror & 0x0FFF) | (_lerror & 0x0800 ? 0xF000 : 0))); \ 59 }) 60 #define CNV_ERROR_DECOMP_STATUS_GET(latest_error) ((s8)(latest_error & 0xFF)) 61 62 struct icp_qat_fw_init_admin_req { 63 u16 init_cfg_sz; 64 u8 resrvd1; 65 u8 cmd_id; 66 u32 max_req_duration; 67 u64 opaque_data; 68 69 union { 70 /* ICP_QAT_FW_INIT_ME */ 71 struct { 72 u64 resrvd2; 73 u16 ibuf_size_in_kb; 74 u8 fw_flags; 75 u8 resrvd3; 76 u32 resrvd4; 77 }; 78 /* ICP_QAT_FW_CONSTANTS_CFG */ 79 struct { 80 u64 init_cfg_ptr; 81 u64 resrvd5; 82 }; 83 /* ICP_QAT_FW_HEARTBEAT_TIMER_SET */ 84 struct { 85 u64 hb_cfg_ptr; 86 u32 heartbeat_ticks; 87 u32 resrvd6; 88 }; 89 /* ICP_QAT_FW_RL_SLA_CONFIG */ 90 struct { 91 u32 credit_per_sla; 92 u8 service_id; 93 u8 vf_id; 94 u8 resrvd7; 95 u8 resrvd8; 96 u32 resrvd9; 97 u32 resrvd10; 98 }; 99 /* ICP_QAT_FW_RL_INIT */ 100 struct { 101 u32 rl_period; 102 u8 config; 103 u8 resrvd11; 104 u8 num_me; 105 u8 resrvd12; 106 u8 pke_svc_arb_map; 107 u8 bulk_crypto_svc_arb_map; 108 u8 compression_svc_arb_map; 109 u8 resrvd13; 110 u32 resrvd14; 111 }; 112 /* ICP_QAT_FW_RL_DU_STOP */ 113 struct { 114 u64 cfg_ptr; 115 u32 resrvd15; 116 u32 resrvd16; 117 }; 118 }; 119 } __packed; 120 121 struct icp_qat_fw_init_admin_resp { 122 u8 flags; 123 u8 resrvd1; 124 u8 status; 125 u8 cmd_id; 126 union { 127 u32 resrvd2; 128 u32 ras_event_count; 129 /* ICP_QAT_FW_STATUS_GET */ 130 struct { 131 u16 version_minor_num; 132 u16 version_major_num; 133 }; 134 /* ICP_QAT_FW_COMP_CAPABILITY_GET */ 135 u32 extended_features; 136 /* ICP_QAT_FW_CNV_STATS_GET */ 137 struct { 138 u16 error_count; 139 u16 latest_error; 140 }; 141 }; 142 u64 opaque_data; 143 union { 144 u32 resrvd3[4]; 145 /* ICP_QAT_FW_STATUS_GET */ 146 struct { 147 u32 version_patch_num; 148 u8 context_id; 149 u8 ae_id; 150 u16 resrvd4; 151 u64 resrvd5; 152 }; 153 /* ICP_QAT_FW_COMP_CAPABILITY_GET */ 154 struct { 155 u16 compression_algos; 156 u16 checksum_algos; 157 u32 deflate_capabilities; 158 u32 resrvd6; 159 u32 deprecated; 160 }; 161 /* ICP_QAT_FW_CRYPTO_CAPABILITY_GET */ 162 struct { 163 u32 cipher_algos; 164 u32 hash_algos; 165 u16 keygen_algos; 166 u16 other; 167 u16 public_key_algos; 168 u16 prime_algos; 169 }; 170 /* ICP_QAT_FW_RL_DU_STOP */ 171 struct { 172 u32 resrvd7; 173 u8 granularity; 174 u8 resrvd8; 175 u16 resrvd9; 176 u32 total_du_time; 177 u32 resrvd10; 178 }; 179 /* ICP_QAT_FW_TIMER_GET */ 180 struct { 181 u64 timestamp; 182 u64 resrvd11; 183 }; 184 /* ICP_QAT_FW_COUNTERS_GET */ 185 struct { 186 u64 req_rec_count; 187 u64 resp_sent_count; 188 }; 189 /* ICP_QAT_FW_PKE_REPLAY_STATS_GET */ 190 struct { 191 u32 successful_count; 192 u32 unsuccessful_count; 193 u64 resrvd12; 194 }; 195 }; 196 } __packed; 197 198 enum icp_qat_fw_init_admin_init_flag { ICP_QAT_FW_INIT_FLAG_PKE_DISABLED = 0 }; 199 200 struct icp_qat_fw_init_admin_hb_cnt { 201 u16 req_heartbeat_cnt; 202 u16 resp_heartbeat_cnt; 203 }; 204 205 #define ICP_QAT_FW_COMN_HEARTBEAT_OK 0 206 #define ICP_QAT_FW_COMN_HEARTBEAT_BLOCKED 1 207 #define ICP_QAT_FW_COMN_HEARTBEAT_FLAG_BITPOS 0 208 #define ICP_QAT_FW_COMN_HEARTBEAT_FLAG_MASK 0x1 209 #define ICP_QAT_FW_COMN_STATUS_RESRVD_FLD_MASK 0xFE 210 #define ICP_QAT_FW_COMN_HEARTBEAT_HDR_FLAG_GET(hdr_t) \ 211 ICP_QAT_FW_COMN_HEARTBEAT_FLAG_GET(hdr_t.flags) 212 213 #define ICP_QAT_FW_COMN_HEARTBEAT_HDR_FLAG_SET(hdr_t, val) \ 214 ICP_QAT_FW_COMN_HEARTBEAT_FLAG_SET(hdr_t, val) 215 216 #define ICP_QAT_FW_COMN_HEARTBEAT_FLAG_GET(flags) \ 217 QAT_FIELD_GET(flags, \ 218 ICP_QAT_FW_COMN_HEARTBEAT_FLAG_BITPOS, \ 219 ICP_QAT_FW_COMN_HEARTBEAT_FLAG_MASK) 220 #endif 221