xref: /illumos-gate/usr/src/uts/common/io/hxge/hxge_rdc_hw.h (revision 2d6eb4a5e0a47d30189497241345dc5466bb68ab)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef	_HXGE_RDC_HW_H
27 #define	_HXGE_RDC_HW_H
28 
29 #ifdef	__cplusplus
30 extern "C" {
31 #endif
32 
33 #define	RDC_BASE_ADDR				0X00300000
34 
35 #define	RDC_PAGE_HANDLE				(RDC_BASE_ADDR + 0x8)
36 #define	RDC_RX_CFG1				(RDC_BASE_ADDR + 0x20)
37 #define	RDC_RX_CFG2				(RDC_BASE_ADDR + 0x28)
38 #define	RDC_RBR_CFG_A				(RDC_BASE_ADDR + 0x40)
39 #define	RDC_RBR_CFG_B				(RDC_BASE_ADDR + 0x48)
40 #define	RDC_RBR_KICK				(RDC_BASE_ADDR + 0x50)
41 #define	RDC_RBR_QLEN				(RDC_BASE_ADDR + 0x58)
42 #define	RDC_RBR_HEAD				(RDC_BASE_ADDR + 0x68)
43 #define	RDC_RCR_CFG_A				(RDC_BASE_ADDR + 0x80)
44 #define	RDC_RCR_CFG_B				(RDC_BASE_ADDR + 0x88)
45 #define	RDC_RCR_QLEN				(RDC_BASE_ADDR + 0x90)
46 #define	RDC_RCR_TAIL				(RDC_BASE_ADDR + 0xA0)
47 #define	RDC_RCR_FLUSH				(RDC_BASE_ADDR + 0xA8)
48 #define	RDC_CLOCK_DIV				(RDC_BASE_ADDR + 0xB0)
49 #define	RDC_INT_MASK				(RDC_BASE_ADDR + 0xB8)
50 #define	RDC_STAT				(RDC_BASE_ADDR + 0xC0)
51 #define	RDC_PKT_COUNT				(RDC_BASE_ADDR + 0xD0)
52 #define	RDC_DROP_COUNT				(RDC_BASE_ADDR + 0xD8)
53 #define	RDC_BYTE_COUNT				(RDC_BASE_ADDR + 0xE0)
54 #define	RDC_PREF_CMD				(RDC_BASE_ADDR + 0x100)
55 #define	RDC_PREF_DATA				(RDC_BASE_ADDR + 0x108)
56 #define	RDC_SHADOW_CMD				(RDC_BASE_ADDR + 0x110)
57 #define	RDC_SHADOW_DATA				(RDC_BASE_ADDR + 0x118)
58 #define	RDC_SHADOW_PAR_DATA			(RDC_BASE_ADDR + 0x120)
59 #define	RDC_CTRL_FIFO_CMD			(RDC_BASE_ADDR + 0x128)
60 #define	RDC_CTRL_FIFO_DATA_LO			(RDC_BASE_ADDR + 0x130)
61 #define	RDC_CTRL_FIFO_DATA_HI			(RDC_BASE_ADDR + 0x138)
62 #define	RDC_CTRL_FIFO_DATA_ECC			(RDC_BASE_ADDR + 0x140)
63 #define	RDC_DATA_FIFO_CMD			(RDC_BASE_ADDR + 0x148)
64 #define	RDC_DATA_FIFO_DATA_LO			(RDC_BASE_ADDR + 0x150)
65 #define	RDC_DATA_FIFO_DATA_HI			(RDC_BASE_ADDR + 0x158)
66 #define	RDC_DATA_FIFO_DATA_ECC			(RDC_BASE_ADDR + 0x160)
67 #define	RDC_STAT_INT_DBG			(RDC_BASE_ADDR + 0x200)
68 #define	RDC_PREF_PAR_LOG			(RDC_BASE_ADDR + 0x210)
69 #define	RDC_SHADOW_PAR_LOG			(RDC_BASE_ADDR + 0x218)
70 #define	RDC_CTRL_FIFO_ECC_LOG			(RDC_BASE_ADDR + 0x220)
71 #define	RDC_DATA_FIFO_ECC_LOG			(RDC_BASE_ADDR + 0x228)
72 #define	RDC_FIFO_ERR_INT_MASK			(RDC_BASE_ADDR + 0x230)
73 #define	RDC_FIFO_ERR_STAT			(RDC_BASE_ADDR + 0x238)
74 #define	RDC_FIFO_ERR_INT_DBG			(RDC_BASE_ADDR + 0x240)
75 #define	RDC_PEU_TXN_LOG				(RDC_BASE_ADDR + 0x250)
76 #define	RDC_DBG_TRAINING_VEC			(RDC_BASE_ADDR + 0x300)
77 #define	RDC_DBG_GRP_SEL				(RDC_BASE_ADDR + 0x308)
78 
79 
80 /*
81  * Register: RdcPageHandle
82  * Logical Page Handle
83  * Description: Logical page handle specifying upper bits of 64-bit
84  * PCIE addresses. Fields in this register are part of the dma
85  * configuration and cannot be changed once the dma is enabled.
86  * Fields:
87  *     Bits [63:44] of a 64-bit address, used to concatenate to a
88  *     44-bit address when generating 64-bit addresses on the PCIE
89  *     bus.
90  */
91 typedef union {
92 	uint64_t value;
93 	struct {
94 #if defined(_BIG_ENDIAN)
95 		uint32_t	rsrvd:32;
96 		uint32_t	rsrvd_l:12;
97 		uint32_t	handle:20;
98 #else
99 		uint32_t	handle:20;
100 		uint32_t	rsrvd_l:12;
101 		uint32_t	rsrvd:32;
102 #endif
103 	} bits;
104 } rdc_page_handle_t;
105 
106 
107 /*
108  * Register: RdcRxCfg1
109  * DMA Configuration 1
110  * Description: Configuration parameters for receive DMA block.
111  * Fields in this register are part of the dma configuration and
112  * cannot be changed once the dma is enabled.
113  * The usage of enable, reset, and qst is as follows. Software
114  * should use the following sequence to reset a DMA channel. First,
115  * set DMA.enable to 0, wait for DMA.qst=1 and then, set DMA.reset to
116  * 1. After DMA.reset is cleared by hardware and the DMA.qst is set
117  * to 1, software may then start configuring the DMA channel. The
118  * DMA.enable can be set or cleared while the DMA is in operation.
119  * The state machines of the DMA may not have returned to its initial
120  * states yet after the DMA.enable bit is cleared. This condition is
121  * indicated by the value of the DMA.qst. An example of DMA.enable
122  * being cleared during operation is when a fatal error occurs.
123  * Fields:
124  *     Set to 1 to enable the Receive DMA. If set to 0, packets
125  *     selecting this DMA will be discarded. On fatal errors, this
126  *     bit will be cleared by hardware. This bit cannot be set if sw
127  *     has not resolved any pending fatal error condition: i.e. any
128  *     RdcStat ldf1 error bits remain set.
129  *     Set to 1 to reset the DMA. Hardware will clear this bit after
130  *     reset is completed. A reset will bring the sepecific DMA back
131  *     to the power on state (including the DMA.en in this register).
132  *     When set to 1, it indicates all state associated with the DMA
133  *     are in its initial state following either dma reset or
134  *     disable. Thus, once this is set to 1, sw could start to
135  *     configure the DMA if needed.
136  *     Bits [43:32] of the Mailbox address.
137  */
138 typedef union {
139 	uint64_t value;
140 	struct {
141 #if defined(_BIG_ENDIAN)
142 		uint32_t	rsrvd:32;
143 		uint32_t	enable:1;
144 		uint32_t	reset:1;
145 		uint32_t	qst:1;
146 		uint32_t	rsrvd1:17;
147 		uint32_t	mbaddr_h:12;
148 #else
149 		uint32_t	mbaddr_h:12;
150 		uint32_t	rsrvd1:17;
151 		uint32_t	qst:1;
152 		uint32_t	reset:1;
153 		uint32_t	enable:1;
154 		uint32_t	rsrvd:32;
155 #endif
156 	} bits;
157 } rdc_rx_cfg1_t;
158 
159 
160 /*
161  * Register: RdcRxCfg2
162  * DMA Configuration 2
163  * Description: Configuration parameters for receive DMA block.
164  * Fields in this register are part of the dma configuration and
165  * cannot be changed once the dma is enabled.
166  * Fields:
167  *     Bits [31:6] of the Mailbox address. Bits [5:0] are assumed to
168  *     be zero, or 64B aligned.
169  *     Multiple of 64Bs, 0 means no offset, b01 means 64B, b10 means
170  *     128B. b11 is invalid, hardware behavior not specified.
171  *     Set to 1 to select the entire header of 6B.
172  */
173 typedef union {
174 	uint64_t value;
175 	struct {
176 #if defined(_BIG_ENDIAN)
177 		uint32_t	rsrvd:32;
178 		uint32_t	mbaddr_l:26;
179 		uint32_t	rsrvd1:3;
180 		uint32_t	offset:2;
181 		uint32_t	full_hdr:1;
182 #else
183 		uint32_t	full_hdr:1;
184 		uint32_t	offset:2;
185 		uint32_t	rsrvd1:3;
186 		uint32_t	mbaddr_l:26;
187 		uint32_t	rsrvd:32;
188 #endif
189 	} bits;
190 } rdc_rx_cfg2_t;
191 
192 
193 /*
194  * Register: RdcRbrCfgA
195  * RBR Configuration A
196  * Description: The following registers are used to configure and
197  * manage the RBR. Note that the entire RBR must stay within the
198  * 'page' defined by staddrBase. The behavior of the hardware is
199  * undefined if the last entry is outside of the page (if bits 43:18
200  * of the address of the last entry are different from bits 43:18 of
201  * the base address). Hardware will support wrapping around at the
202  * end of the ring buffer defined by LEN. LEN must be a multiple of
203  * 64. Fields in this register are part of the dma configuration and
204  * cannot be changed once the dma is enabled.
205  * HW does not check for all configuration errors across different
206  * fields.
207  *
208  * Fields:
209  *     Bits 15:6 of the maximum number of RBBs in the buffer ring.
210  *     Bits 5:0 are hardcoded to zero. The maximum is (2^16 - 64) and
211  *     is limited by the staddr value. (len + staddr) should not
212  *     exceed (2^16 - 64).
213  *     Bits [43:18] of the address for the RBR. This value remains
214  *     fixed, and is used as the base address of the ring. All
215  *     entries in the ring have this as their upper address bits.
216  *     Bits [17:6] of the address of the RBR. staddrBase concatinated
217  *     with staddr is the starting address of the RBR. (len + staddr)
218  *     should not exceed (2^16 - 64).
219  */
220 typedef union {
221 	uint64_t value;
222 	struct {
223 #if defined(_BIG_ENDIAN)
224 		uint32_t	len:10;
225 		uint32_t	len_lo:6;
226 		uint32_t	rsrvd:4;
227 		uint32_t	staddr_base:12;
228 		uint32_t	staddr_base_l:14;
229 		uint32_t	staddr:12;
230 		uint32_t	rsrvd1:6;
231 #else
232 		uint32_t	rsrvd1:6;
233 		uint32_t	staddr:12;
234 		uint32_t	staddr_base_l:14;
235 		uint32_t	staddr_base:12;
236 		uint32_t	rsrvd:4;
237 		uint32_t	len_lo:6;
238 		uint32_t	len:10;
239 #endif
240 	} bits;
241 } rdc_rbr_cfg_a_t;
242 
243 
244 /*
245  * Register: RdcRbrCfgB
246  * RBR Configuration B
247  * Description: This register configures the block size, and the
248  * individual packet buffer sizes. The VLD bits of the three block
249  * sizes have to be set to 1 in normal operations. These bits may be
250  * turned off for debug purpose only. Fields in this register are
251  * part of the dma configuration and cannot be changed once the dma
252  * is enabled.
253  * Fields:
254  *     Buffer Block Size. b0 - 4K; b1 - 8K.
255  *     Set to 1 to indicate SIZE2 is valid, and enable hardware to
256  *     allocate buffers of size 2. Always set to 1 in normal
257  *     operation.
258  *     Size 2 of packet buffer. b0 - 2K; b1 - 4K.
259  *     Set to 1 to indicate SIZE1 is valid, and enable hardware to
260  *     allocate buffers of size 1. Always set to 1 in normal
261  *     operation.
262  *     Size 1 of packet buffer. b0 - 1K; b1 - 2K.
263  *     Set to 1 to indicate SIZE0 is valid, and enable hardware to
264  *     allocate buffers of size 0. Always set to 1 in normal
265  *     operation.
266  *     Size 0 of packet buffer. b00 - 256; b01 - 512; b10 - 1K; b11 -
267  *     reserved.
268  */
269 typedef union {
270 	uint64_t value;
271 	struct {
272 #if defined(_BIG_ENDIAN)
273 		uint32_t	rsrvd:32;
274 		uint32_t	rsrvd_l:7;
275 		uint32_t	bksize:1;
276 		uint32_t	vld2:1;
277 		uint32_t	rsrvd1:6;
278 		uint32_t	bufsz2:1;
279 		uint32_t	vld1:1;
280 		uint32_t	rsrvd2:6;
281 		uint32_t	bufsz1:1;
282 		uint32_t	vld0:1;
283 		uint32_t	rsrvd3:5;
284 		uint32_t	bufsz0:2;
285 #else
286 		uint32_t	bufsz0:2;
287 		uint32_t	rsrvd3:5;
288 		uint32_t	vld0:1;
289 		uint32_t	bufsz1:1;
290 		uint32_t	rsrvd2:6;
291 		uint32_t	vld1:1;
292 		uint32_t	bufsz2:1;
293 		uint32_t	rsrvd1:6;
294 		uint32_t	vld2:1;
295 		uint32_t	bksize:1;
296 		uint32_t	rsrvd_l:7;
297 		uint32_t	rsrvd:32;
298 #endif
299 	} bits;
300 } rdc_rbr_cfg_b_t;
301 
302 
303 /*
304  * Register: RdcRbrKick
305  * RBR Kick
306  * Description: Block buffer addresses are added to the ring buffer
307  * by software. When software writes to the Kick register, indicating
308  * the number of descriptors added, hardware will update the internal
309  * state of the corresponding buffer pool.
310  * HW does not check for all configuration errors across different
311  * fields.
312  *
313  * Fields:
314  *     Number of Block Buffers added by software. Hardware effect
315  *     will be triggered when the register is written to.
316  */
317 typedef union {
318 	uint64_t value;
319 	struct {
320 #if defined(_BIG_ENDIAN)
321 		uint32_t	rsrvd:32;
322 		uint32_t	rsrvd_l:16;
323 		uint32_t	bkadd:16;
324 #else
325 		uint32_t	bkadd:16;
326 		uint32_t	rsrvd_l:16;
327 		uint32_t	rsrvd:32;
328 #endif
329 	} bits;
330 } rdc_rbr_kick_t;
331 
332 
333 /*
334  * Register: RdcRbrQlen
335  * RBR Queue Length
336  * Description: The current number of entries in the RBR.
337  * Fields:
338  *     Number of block addresses in the ring buffer.
339  */
340 typedef union {
341 	uint64_t value;
342 	struct {
343 #if defined(_BIG_ENDIAN)
344 		uint32_t	rsrvd:32;
345 		uint32_t	rsrvd_l:16;
346 		uint32_t	qlen:16;
347 #else
348 		uint32_t	qlen:16;
349 		uint32_t	rsrvd_l:16;
350 		uint32_t	rsrvd:32;
351 #endif
352 	} bits;
353 } rdc_rbr_qlen_t;
354 
355 
356 /*
357  * Register: RdcRbrHead
358  * RBR Head
359  * Description: Lower bits of the RBR head pointer. Software programs
360  * the upper bits, specified in rdcRbrConfigA.staddrBase.
361  * Fields:
362  *     Bits [17:2] of the software posted address, 4B aligned. This
363  *     pointer is updated by hardware after each block buffer is
364  *     consumed.
365  */
366 typedef union {
367 	uint64_t value;
368 	struct {
369 #if defined(_BIG_ENDIAN)
370 		uint32_t	rsrvd:32;
371 		uint32_t	rsrvd_l:14;
372 		uint32_t	head:16;
373 		uint32_t	rsrvd1:2;
374 #else
375 		uint32_t	rsrvd1:2;
376 		uint32_t	head:16;
377 		uint32_t	rsrvd_l:14;
378 		uint32_t	rsrvd:32;
379 #endif
380 	} bits;
381 } rdc_rbr_head_t;
382 
383 
384 /*
385  * Register: RdcRcrCfgA
386  * RCR Configuration A
387  * Description: The RCR should be within the 'page' defined by the
388  * staddrBase, i.e. staddrBase concatenate with STADDR plus 8 x LEN
389  * should be within the last address of the 'page' defined by
390  * staddrBase. The length must be a multiple of 32. Fields in this
391  * register are part of the dma configuration and cannot be changed
392  * once the dma is enabled.
393  * HW does not check for all configuration errors across different
394  * fields.
395  *
396  * Fields:
397  *     Bits 15:5 of the maximum number of 8B entries in RCR. Bits 4:0
398  *     are hard-coded to zero. The maximum size is (2^16 - 32) and is
399  *     limited by staddr value. (len + staddr) should not exceed
400  *     (2^16 - 32).
401  *     Bits [43:19] of the Start address for the RCR.
402  *     Bits [18:6] of start address for the RCR. (len + staddr)
403  *     should not exceed (2^16 - 32).
404  */
405 typedef union {
406 	uint64_t value;
407 	struct {
408 #if defined(_BIG_ENDIAN)
409 		uint32_t	len:11;
410 		uint32_t	len_lo:5;
411 		uint32_t	rsrvd:4;
412 		uint32_t	staddr_base:12;
413 		uint32_t	staddr_base_l:13;
414 		uint32_t	staddr:13;
415 		uint32_t	rsrvd1:6;
416 #else
417 		uint32_t	rsrvd1:6;
418 		uint32_t	staddr:13;
419 		uint32_t	staddr_base_l:13;
420 		uint32_t	staddr_base:12;
421 		uint32_t	rsrvd:4;
422 		uint32_t	len_lo:5;
423 		uint32_t	len:11;
424 #endif
425 	} bits;
426 } rdc_rcr_cfg_a_t;
427 
428 
429 /*
430  * Register: RdcRcrCfgB
431  * RCR Configuration B
432  * Description: RCR configuration settings.
433  * Fields:
434  *     Packet Threshold; when the number of packets enqueued in RCR
435  *     is strictly larger than PTHRES, the DMA MAY issue an interrupt
436  *     if enabled.
437  *     Enable timeout. If set to one, enable the timeout. A timeout
438  *     will initiate an update of the software visible states. If
439  *     interrupt is armed, in addition to the update, an interrupt to
440  *     CPU will be generated, and the interrupt disarmed.
441  *     Time out value. The system clock is divided down by the value
442  *     programmed in the Receive DMA Clock Divider register.
443  */
444 typedef union {
445 	uint64_t value;
446 	struct {
447 #if defined(_BIG_ENDIAN)
448 		uint32_t	rsrvd:32;
449 		uint32_t	pthres:16;
450 		uint32_t	entout:1;
451 		uint32_t	rsrvd1:9;
452 		uint32_t	timeout:6;
453 #else
454 		uint32_t	timeout:6;
455 		uint32_t	rsrvd1:9;
456 		uint32_t	entout:1;
457 		uint32_t	pthres:16;
458 		uint32_t	rsrvd:32;
459 #endif
460 	} bits;
461 } rdc_rcr_cfg_b_t;
462 
463 
464 /*
465  * Register: RdcRcrQlen
466  * RCR Queue Length
467  * Description: The number of entries in the RCR.
468  * Fields:
469  *     Number of packets queued. Initialize to zero after the RCR
470  *     Configuration A register is written to.
471  */
472 typedef union {
473 	uint64_t value;
474 	struct {
475 #if defined(_BIG_ENDIAN)
476 		uint32_t	rsrvd:32;
477 		uint32_t	rsrvd_l:16;
478 		uint32_t	qlen:16;
479 #else
480 		uint32_t	qlen:16;
481 		uint32_t	rsrvd_l:16;
482 		uint32_t	rsrvd:32;
483 #endif
484 	} bits;
485 } rdc_rcr_qlen_t;
486 
487 
488 /*
489  * Register: RdcRcrTail
490  * RCR Tail
491  * Description: Lower bits of the RCR tail pointer. Software programs
492  * the upper bits, specified in rdcRcrConfigA.staddrBase.
493  * Fields:
494  *     Address of the RCR Tail Pointer [18:3] (points to the next
495  *     available location.) Initialized after the RCR Configuration A
496  *     register is written to.
497  */
498 typedef union {
499 	uint64_t value;
500 	struct {
501 #if defined(_BIG_ENDIAN)
502 		uint32_t	rsrvd:32;
503 		uint32_t	rsrvd_l:13;
504 		uint32_t	tail:16;
505 		uint32_t	rsrvd1:3;
506 #else
507 		uint32_t	rsrvd1:3;
508 		uint32_t	tail:16;
509 		uint32_t	rsrvd_l:13;
510 		uint32_t	rsrvd:32;
511 #endif
512 	} bits;
513 } rdc_rcr_tail_t;
514 
515 
516 /*
517  * Register: RdcRcrFlush
518  * RCR Flush
519  * Description: This register will force an update to the RCR in
520  * system memory.
521  * Fields:
522  *     Set to 1 to force the hardware to store the shadow tail block
523  *     to DRAM if the hardware state (queue length and pointers) is
524  *     different from the software visible state. Reset to 0 by
525  *     hardware when done.
526  */
527 typedef union {
528 	uint64_t value;
529 	struct {
530 #if defined(_BIG_ENDIAN)
531 		uint32_t	rsrvd:32;
532 		uint32_t	rsrvd_l:31;
533 		uint32_t	flush:1;
534 #else
535 		uint32_t	flush:1;
536 		uint32_t	rsrvd_l:31;
537 		uint32_t	rsrvd:32;
538 #endif
539 	} bits;
540 } rdc_rcr_flush_t;
541 
542 
543 /*
544  * Register: RdcClockDiv
545  * Receive DMA Clock Divider
546  * Description: The granularity of the DMA timers is determined by
547  * the following counter. This is used to drive the DMA timeout
548  * counters. For a 250MHz system clock, a value of 25000 (decimal)
549  * will yield a granularity of 100 usec.
550  * Fields:
551  *     System clock divider, determines the granularity of the DMA
552  *     timeout count-down. The hardware count down is count+1.
553  */
554 typedef union {
555 	uint64_t value;
556 	struct {
557 #if defined(_BIG_ENDIAN)
558 		uint32_t	rsrvd:32;
559 		uint32_t	rsrvd_l:16;
560 		uint32_t	count:16;
561 #else
562 		uint32_t	count:16;
563 		uint32_t	rsrvd_l:16;
564 		uint32_t	rsrvd:32;
565 #endif
566 	} bits;
567 } rdc_clock_div_t;
568 
569 
570 /*
571  * Register: RdcIntMask
572  * RDC Interrupt Mask
573  * Description: RDC interrupt status register. RCRTHRES and RCRTO
574  * bits are used to keep track of normal DMA operations, while the
575  * remaining bits are primarily used to detect error conditions.
576  * Fields:
577  *     Set to 0 to enable flagging when rdc receives a response
578  *     completion timeout from peu. Part of LDF 1.
579  *     Set to 1 to enable flagging when rdc receives a poisoned
580  *     completion or non-zero (unsuccessful) completion status
581  *     received from PEU. Part of LDF 1.
582  *     Set to 0 to enable flagging when RCR threshold crossed. Part
583  *     of LDF 0.
584  *     Set to 0 to enable flagging when RCR timeout. Part of LDF 0.
585  *     Set to 0 to enable flagging when read from rcr shadow ram
586  *     generates a parity error Part of LDF 1.
587  *     Set to 0 to enable flagging when read from rbr prefetch ram
588  *     generates a parity error Part of LDF 1.
589  *     Set to 0 to enable flagging when Receive Block Ring prefetch
590  *     is empty (not enough buffer blocks available depending on
591  *     incoming pkt size) when hardware tries to queue a packet.
592  *     Incoming packets will be discarded. Non-fatal error. Part of
593  *     LDF 1.
594  *     Set to 0 to enable flagging when packet discard because of RCR
595  *     shadow full.
596  *     Set to 0 to enable flagging when Receive Completion Ring full
597  *     when hardware tries to enqueue the completion status of a
598  *     packet. Part of LDF 1.
599  *     Set to 0 to enable flagging when RBR empty when hardware
600  *     attempts to prefetch. Part of LDF 1.
601  *     Set to 0 to enable flagging when Receive Block Ring full when
602  *     software tries to post more blocks. Part of LDF 1.
603  */
604 typedef union {
605 	uint64_t value;
606 	struct {
607 #if defined(_BIG_ENDIAN)
608 		uint32_t	rsrvd:10;
609 		uint32_t	rbr_cpl_to:1;
610 		uint32_t	peu_resp_err:1;
611 		uint32_t	rsrvd1:5;
612 		uint32_t	rcr_thres:1;
613 		uint32_t	rcr_to:1;
614 		uint32_t	rcr_shadow_par_err:1;
615 		uint32_t	rbr_prefetch_par_err:1;
616 		uint32_t	rsrvd2:2;
617 		uint32_t	rbr_pre_empty:1;
618 		uint32_t	rcr_shadow_full:1;
619 		uint32_t	rsrvd3:2;
620 		uint32_t	rcr_full:1;
621 		uint32_t	rbr_empty:1;
622 		uint32_t	rbr_full:1;
623 		uint32_t	rsrvd4:2;
624 		uint32_t	rsrvd5:32;
625 #else
626 		uint32_t	rsrvd5:32;
627 		uint32_t	rsrvd4:2;
628 		uint32_t	rbr_full:1;
629 		uint32_t	rbr_empty:1;
630 		uint32_t	rcr_full:1;
631 		uint32_t	rsrvd3:2;
632 		uint32_t	rcr_shadow_full:1;
633 		uint32_t	rbr_pre_empty:1;
634 		uint32_t	rsrvd2:2;
635 		uint32_t	rbr_prefetch_par_err:1;
636 		uint32_t	rcr_shadow_par_err:1;
637 		uint32_t	rcr_to:1;
638 		uint32_t	rcr_thres:1;
639 		uint32_t	rsrvd1:5;
640 		uint32_t	peu_resp_err:1;
641 		uint32_t	rbr_cpl_to:1;
642 		uint32_t	rsrvd:10;
643 #endif
644 	} bits;
645 } rdc_int_mask_t;
646 
647 
648 /*
649  * Register: RdcStat
650  * RDC Control And Status
651  * Description: The DMA channels are controlled using this register.
652  * Fields:
653  *     Set to 1 to indicate rdc received a response completion
654  *     timeout from peu. Fatal error. Part of LDF 1.
655  *     Set to 1 to indicate poisoned completion or non-zero
656  *     (unsuccessful) completion status received from PEU. Part of
657  *     LDF 1.
658  *     Set to 1 to enable mailbox update. Hardware will reset to 0
659  *     after one update. Software needs to set to 1 for each update.
660  *     Write 0 has no effect. Note that once set by software, only
661  *     hardware can reset the value. This bit is also used to keep
662  *     track of the exclusivity between threshold triggered or
663  *     timeout triggered interrupt. If this bit is not set, there
664  *     will be no timer based interrupt, and threshold based
665  *     interrupt will not issue a mailbox update. It is recommended
666  *     that software should set this bit to one when arming the
667  *     device for interrupt.
668  *     Set to 1 to indicate RCR threshold crossed. This is a level
669  *     event. Part of LDF 0.
670  *     Set to 1 to indicate RCR time-outed if MEX bit is set and the
671  *     queue length is non-zero when timeout occurs. When software
672  *     writes 1 to this bit, RCRTO will be reset to 0. Part of LDF 0.
673  *     Set to 1 to indicate read from rcr shadow ram generates a
674  *     parity error Writing a 1 to this register also clears the
675  *     rdcshadowParLog register Fatal error. Part of LDF 1.
676  *     Set to 1 to indicate read from rbr prefetch ram generates
677  *     parity error Writing a 1 to this register also clears the
678  *     rdcPrefParLog register Fatal error. Part of LDF 1.
679  *     Set to 1 to indicate Receive Block Ring prefetch is empty (not
680  *     enough buffer blocks available depending on incoming pkt size)
681  *     when hardware tries to queue a packet. Incoming packets will
682  *     be discarded. Non-fatal error. Part of LDF 1.
683  *     Set to 1 to indicate packet discard because of RCR shadow
684  *     full. RCR Shadow full cannot be set to 1 in a normal
685  *     operation. When set to 1, it indicates a fatal error. Part of
686  *     LDF 1.
687  *     Set to 1 to indicate Receive Completion Ring full when
688  *     hardware tries to enqueue the completion status of a packet.
689  *     Incoming packets will be discarded. No buffer consumed. Fatal
690  *     error. Part of LDF 1.
691  *     Set to 1 to indicate RBR empty when hardware attempts to
692  *     prefetch. Part of LDF 1.
693  *     Set to 1 to indicate Receive Buffer Ring full when software
694  *     writes the kick register with a value greater than the length
695  *     of the RBR length. Incoming packets will be discarded. Fatal
696  *     error. Part of LDF 1.
697  *     Number of buffer pointers read. Used to advance the RCR head
698  *     pointer.
699  *     Number of packets read; when written to, decrement the QLEN
700  *     counter by PKTREAD. QLEN is lower bounded to zero.
701  */
702 typedef union {
703 	uint64_t value;
704 	struct {
705 #if defined(_BIG_ENDIAN)
706 		uint32_t	rsrvd:10;
707 		uint32_t	rbr_cpl_to:1;
708 		uint32_t	peu_resp_err:1;
709 		uint32_t	rsrvd1:4;
710 		uint32_t	mex:1;
711 		uint32_t	rcr_thres:1;
712 		uint32_t	rcr_to:1;
713 		uint32_t	rcr_shadow_par_err:1;
714 		uint32_t	rbr_prefetch_par_err:1;
715 		uint32_t	rsrvd2:2;
716 		uint32_t	rbr_pre_empty:1;
717 		uint32_t	rcr_shadow_full:1;
718 		uint32_t	rsrvd3:2;
719 		uint32_t	rcr_full:1;
720 		uint32_t	rbr_empty:1;
721 		uint32_t	rbr_full:1;
722 		uint32_t	rsrvd4:2;
723 		uint32_t	ptrread:16;
724 		uint32_t	pktread:16;
725 #else
726 		uint32_t	pktread:16;
727 		uint32_t	ptrread:16;
728 		uint32_t	rsrvd4:2;
729 		uint32_t	rbr_full:1;
730 		uint32_t	rbr_empty:1;
731 		uint32_t	rcr_full:1;
732 		uint32_t	rsrvd3:2;
733 		uint32_t	rcr_shadow_full:1;
734 		uint32_t	rbr_pre_empty:1;
735 		uint32_t	rsrvd2:2;
736 		uint32_t	rbr_prefetch_par_err:1;
737 		uint32_t	rcr_shadow_par_err:1;
738 		uint32_t	rcr_to:1;
739 		uint32_t	rcr_thres:1;
740 		uint32_t	mex:1;
741 		uint32_t	rsrvd1:4;
742 		uint32_t	peu_resp_err:1;
743 		uint32_t	rbr_cpl_to:1;
744 		uint32_t	rsrvd:10;
745 #endif
746 	} bits;
747 } rdc_stat_t;
748 
749 
750 /*
751  * Register: RdcPktCount
752  * Rx DMA Packet Counter
753  * Description: Counts the number of packets received from the Rx
754  * Virtual MAC for this DMA channel.
755  * Fields:
756  *     Count of SYN packets received from RVM. This counter
757  *     saturates.
758  *     Count of packets received from RVM. This counter saturates.
759  */
760 typedef union {
761 	uint64_t value;
762 	struct {
763 #if defined(_BIG_ENDIAN)
764 		uint32_t	syn_pkt_count:32;
765 		uint32_t	pkt_count:32;
766 #else
767 		uint32_t	pkt_count:32;
768 		uint32_t	syn_pkt_count:32;
769 #endif
770 	} bits;
771 } rdc_pkt_count_t;
772 
773 
774 /*
775  * Register: RdcDropCount
776  * Rx DMA Dropped Packet Counters
777  * Description: Counts the number of packets dropped due to different
778  * types of errors.
779  * Fields:
780  *     Count of packets dropped because they were longer than the
781  *     maximum length. This counter saturates.
782  *     Count of packets dropped because there was no block available
783  *     in the RBR Prefetch Buffer. This counter saturates.
784  *     Count of packets dropped because the RVM marked the packet as
785  *     errored. This counter saturates.
786  *     Count of packets dropped because there was a framing error
787  *     from the RVM. This counter saturates.
788  *     Count of packets dropped because the packet did not fit in the
789  *     rx ram. This counter saturates.
790  */
791 typedef union {
792 	uint64_t value;
793 	struct {
794 #if defined(_BIG_ENDIAN)
795 		uint32_t	rsrvd:16;
796 		uint32_t	too_long:8;
797 		uint32_t	no_rbr_avail:8;
798 		uint32_t	rvm_error:8;
799 		uint32_t	frame_error:8;
800 		uint32_t	rxram_error:8;
801 		uint32_t	rsrvd1:8;
802 #else
803 		uint32_t	rsrvd1:8;
804 		uint32_t	rxram_error:8;
805 		uint32_t	frame_error:8;
806 		uint32_t	rvm_error:8;
807 		uint32_t	no_rbr_avail:8;
808 		uint32_t	too_long:8;
809 		uint32_t	rsrvd:16;
810 #endif
811 	} bits;
812 } rdc_drop_count_t;
813 
814 
815 /*
816  * Register: RdcByteCount
817  * Rx DMA Byte Counter
818  * Description: Counts the number of bytes transferred by dma for all
819  * channels.
820  * Fields:
821  *     Count of bytes transferred by dma. This counter saturates.
822  */
823 typedef union {
824 	uint64_t value;
825 	struct {
826 #if defined(_BIG_ENDIAN)
827 		uint32_t	rsrvd:32;
828 		uint32_t	count:32;
829 #else
830 		uint32_t	count:32;
831 		uint32_t	rsrvd:32;
832 #endif
833 	} bits;
834 } rdc_byte_count_t;
835 
836 
837 /*
838  * Register: RdcPrefCmd
839  * Rx DMA Prefetch Buffer Command
840  * Description: Allows debug access to the entire prefetch buffer,
841  * along with the rdcPrefData register. Writing the rdcPrefCmd
842  * triggers the access. For writes, software writes the 32 bits of
843  * data to the rdcPrefData register before writing the write command
844  * to this register. For reads, software first writes the the read
845  * command to this register, then reads the 32-bit value from the
846  * rdcPrefData register. The status field should be polled by
847  * software until it goes low, indicating the read or write has
848  * completed.
849  * Fields:
850  *     status of indirect access 0=busy 1=done
851  *     Command type. 1 indicates a read command, 0 a write command.
852  *     enable writing of parity bits 1=enabled, 0=disabled
853  *     DMA channel of entry to read or write
854  *     Entry in the prefetch buffer to read or write
855  */
856 typedef union {
857 	uint64_t value;
858 	struct {
859 #if defined(_BIG_ENDIAN)
860 		uint32_t	rsrvd:32;
861 		uint32_t	status:1;
862 		uint32_t	cmd:1;
863 		uint32_t	par_en:1;
864 		uint32_t	rsrvd1:22;
865 		uint32_t	dmc:2;
866 		uint32_t	entry:5;
867 #else
868 		uint32_t	entry:5;
869 		uint32_t	dmc:2;
870 		uint32_t	rsrvd1:22;
871 		uint32_t	par_en:1;
872 		uint32_t	cmd:1;
873 		uint32_t	status:1;
874 		uint32_t	rsrvd:32;
875 #endif
876 	} bits;
877 } rdc_pref_cmd_t;
878 
879 
880 /*
881  * Register: RdcPrefData
882  * Rx DMA Prefetch Buffer Data
883  * Description: See rdcPrefCmd register.
884  * Fields:
885  *     For writes, parity bits is written into prefetch buffer. For
886  *     reads, parity bits read from the prefetch buffer.
887  *     For writes, data which is written into prefetch buffer. For
888  *     reads, data read from the prefetch buffer.
889  */
890 typedef union {
891 	uint64_t value;
892 	struct {
893 #if defined(_BIG_ENDIAN)
894 		uint32_t	rsrvd:28;
895 		uint32_t	par:4;
896 		uint32_t	data:32;
897 #else
898 		uint32_t	data:32;
899 		uint32_t	par:4;
900 		uint32_t	rsrvd:28;
901 #endif
902 	} bits;
903 } rdc_pref_data_t;
904 
905 
906 /*
907  * Register: RdcShadowCmd
908  * Rx DMA Shadow Tail Command
909  * Description: Allows debug access to the entire shadow tail, along
910  * with the rdcShadowData register. Writing the rdcShadowCmd triggers
911  * the access. For writes, software writes the 64 bits of data to the
912  * rdcShadowData register before writing the write command to this
913  * register. For reads, software first writes the the read command to
914  * this register, then reads the 64-bit value from the rdcShadowData
915  * register. The valid field should be polled by software until it
916  * goes low, indicating the read or write has completed.
917  * Fields:
918  *     status of indirect access 0=busy 1=done
919  *     Command type. 1 indicates a read command, 0 a write command.
920  *     enable writing of parity bits 1=enabled, 0=disabled
921  *     DMA channel of entry to read or write
922  *     Entry in the shadow tail to read or write
923  */
924 typedef union {
925 	uint64_t value;
926 	struct {
927 #if defined(_BIG_ENDIAN)
928 		uint32_t	rsrvd:32;
929 		uint32_t	status:1;
930 		uint32_t	cmd:1;
931 		uint32_t	par_en:1;
932 		uint32_t	rsrvd1:23;
933 		uint32_t	dmc:2;
934 		uint32_t	entry:4;
935 #else
936 		uint32_t	entry:4;
937 		uint32_t	dmc:2;
938 		uint32_t	rsrvd1:23;
939 		uint32_t	par_en:1;
940 		uint32_t	cmd:1;
941 		uint32_t	status:1;
942 		uint32_t	rsrvd:32;
943 #endif
944 	} bits;
945 } rdc_shadow_cmd_t;
946 
947 
948 /*
949  * Register: RdcShadowData
950  * Rx DMA Shadow Tail Data
951  * Description: See rdcShadowCmd register.
952  * Fields:
953  *     For writes, data which is written into shadow tail. For reads,
954  *     data read from the shadow tail.
955  */
956 typedef union {
957 	uint64_t value;
958 	struct {
959 #if defined(_BIG_ENDIAN)
960 		uint32_t	data:32;
961 		uint32_t	data_l:32;
962 #else
963 		uint32_t	data_l:32;
964 		uint32_t	data:32;
965 #endif
966 	} bits;
967 } rdc_shadow_data_t;
968 
969 
970 /*
971  * Register: RdcShadowParData
972  * Rx DMA Shadow Tail Parity Data
973  * Description: See rdcShadowCmd register.
974  * Fields:
975  *     For writes, parity data is written into shadow tail. For
976  *     reads, parity data read from the shadow tail.
977  */
978 typedef union {
979 	uint64_t value;
980 	struct {
981 #if defined(_BIG_ENDIAN)
982 		uint32_t	rsrvd:32;
983 		uint32_t	rsrvd1:24;
984 		uint32_t	parity_data:8;
985 #else
986 		uint32_t	parity_data:8;
987 		uint32_t	rsrvd1:24;
988 		uint32_t	rsrvd:32;
989 #endif
990 	} bits;
991 } rdc_shadow_par_data_t;
992 
993 
994 /*
995  * Register: RdcCtrlFifoCmd
996  * Rx DMA Control Fifo Command
997  * Description: Allows debug access to the entire Rx Ctl FIFO, along
998  * with the rdcCtrlFifoData register. Writing the rdcCtrlFifoCmd
999  * triggers the access. For writes, software writes the 128 bits of
1000  * data to the rdcCtrlFifoData registers before writing the write
1001  * command to this register. For reads, software first writes the the
1002  * read command to this register, then reads the 128-bit value from
1003  * the rdcCtrlFifoData registers. The valid field should be polled by
1004  * software until it goes low, indicating the read or write has
1005  * completed.
1006  * Fields:
1007  *     status of indirect access 0=busy 1=done
1008  *     Command type. 1 indicates a read command, 0 a write command.
1009  *     enable writing of ECC bits 1=enabled, 0=disabled
1010  *     Entry in the rx control ram to read or write
1011  */
1012 typedef union {
1013 	uint64_t value;
1014 	struct {
1015 #if defined(_BIG_ENDIAN)
1016 		uint32_t	rsrvd:32;
1017 		uint32_t	status:1;
1018 		uint32_t	cmd:1;
1019 		uint32_t	ecc_en:1;
1020 		uint32_t	rsrvd1:20;
1021 		uint32_t	entry:9;
1022 #else
1023 		uint32_t	entry:9;
1024 		uint32_t	rsrvd1:20;
1025 		uint32_t	ecc_en:1;
1026 		uint32_t	cmd:1;
1027 		uint32_t	status:1;
1028 		uint32_t	rsrvd:32;
1029 #endif
1030 	} bits;
1031 } rdc_ctrl_fifo_cmd_t;
1032 
1033 
1034 /*
1035  * Register: RdcCtrlFifoDataLo
1036  * Rx DMA Control Fifo Data Lo
1037  * Description: Lower 64 bits read or written to the Rx Ctl FIFO. See
1038  * rdcCtrlFifoCmd register.
1039  * Fields:
1040  *     For writes, data which is written into rx control ram. For
1041  *     reads, data read from the rx control ram.
1042  */
1043 typedef union {
1044 	uint64_t value;
1045 	struct {
1046 #if defined(_BIG_ENDIAN)
1047 		uint32_t	data:32;
1048 		uint32_t	data_l:32;
1049 #else
1050 		uint32_t	data_l:32;
1051 		uint32_t	data:32;
1052 #endif
1053 	} bits;
1054 } rdc_ctrl_fifo_data_lo_t;
1055 
1056 
1057 /*
1058  * Register: RdcCtrlFifoDataHi
1059  * Rx DMA Control Fifo Data Hi
1060  * Description: Upper 64 bits read or written to the Rx Ctl FIFO. See
1061  * rdcCtrlFifoCmd register.
1062  * Fields:
1063  *     For writes, data which is written into rx control ram. For
1064  *     reads, data read from the rx control ram.
1065  */
1066 typedef union {
1067 	uint64_t value;
1068 	struct {
1069 #if defined(_BIG_ENDIAN)
1070 		uint32_t	data:32;
1071 		uint32_t	data_l:32;
1072 #else
1073 		uint32_t	data_l:32;
1074 		uint32_t	data:32;
1075 #endif
1076 	} bits;
1077 } rdc_ctrl_fifo_data_hi_t;
1078 
1079 
1080 /*
1081  * Register: RdcCtrlFifoDataEcc
1082  * Rx DMA Control Fifo Data ECC
1083  * Description: 16 bits ECC data read or written to the Rx Ctl FIFO.
1084  * See rdcCtrlFifoCmd register.
1085  * Fields:
1086  *     For writes, data which is written into rx control ram. For
1087  *     reads, data read from the rx control ram.
1088  *     For writes, data which is written into rx control ram. For
1089  *     reads, data read from the rx control ram.
1090  */
1091 typedef union {
1092 	uint64_t value;
1093 	struct {
1094 #if defined(_BIG_ENDIAN)
1095 		uint32_t	rsrvd:32;
1096 		uint32_t	rsrvd1:16;
1097 		uint32_t	ecc_data_hi:8;
1098 		uint32_t	ecc_data_lo:8;
1099 #else
1100 		uint32_t	ecc_data_lo:8;
1101 		uint32_t	ecc_data_hi:8;
1102 		uint32_t	rsrvd1:16;
1103 		uint32_t	rsrvd:32;
1104 #endif
1105 	} bits;
1106 } rdc_ctrl_fifo_data_ecc_t;
1107 
1108 
1109 /*
1110  * Register: RdcDataFifoCmd
1111  * Rx DMA Data Fifo Command
1112  * Description: Allows debug access to the entire Rx Data FIFO, along
1113  * with the rdcDataFifoData register. Writing the rdcCtrlFifoCmd
1114  * triggers the access. For writes, software writes the 128 bits of
1115  * data to the rdcDataFifoData registers before writing the write
1116  * command to this register. For reads, software first writes the the
1117  * read command to this register, then reads the 128-bit value from
1118  * the rdcDataFifoData registers. The valid field should be polled by
1119  * software until it goes low, indicating the read or write has
1120  * completed.
1121  * Fields:
1122  *     status of indirect access 0=busy 1=done
1123  *     Command type. 1 indicates a read command, 0 a write command.
1124  *     enable writing of ECC bits 1=enabled, 0=disabled
1125  *     Entry in the rx data ram to read or write
1126  */
1127 typedef union {
1128 	uint64_t value;
1129 	struct {
1130 #if defined(_BIG_ENDIAN)
1131 		uint32_t	rsrvd:32;
1132 		uint32_t	status:1;
1133 		uint32_t	cmd:1;
1134 		uint32_t	ecc_en:1;
1135 		uint32_t	rsrvd1:18;
1136 		uint32_t	entry:11;
1137 #else
1138 		uint32_t	entry:11;
1139 		uint32_t	rsrvd1:18;
1140 		uint32_t	ecc_en:1;
1141 		uint32_t	cmd:1;
1142 		uint32_t	status:1;
1143 		uint32_t	rsrvd:32;
1144 #endif
1145 	} bits;
1146 } rdc_data_fifo_cmd_t;
1147 
1148 
1149 /*
1150  * Register: RdcDataFifoDataLo
1151  * Rx DMA Data Fifo Data Lo
1152  * Description: Lower 64 bits read or written to the Rx Data FIFO.
1153  * See rdcDataFifoCmd register.
1154  * Fields:
1155  *     For writes, data which is written into rx data ram. For reads,
1156  *     data read from the rx data ram.
1157  */
1158 typedef union {
1159 	uint64_t value;
1160 	struct {
1161 #if defined(_BIG_ENDIAN)
1162 		uint32_t	data:32;
1163 		uint32_t	data_l:32;
1164 #else
1165 		uint32_t	data_l:32;
1166 		uint32_t	data:32;
1167 #endif
1168 	} bits;
1169 } rdc_data_fifo_data_lo_t;
1170 
1171 
1172 /*
1173  * Register: RdcDataFifoDataHi
1174  * Rx DMA Data Fifo Data Hi
1175  * Description: Upper 64 bits read or written to the Rx Data FIFO.
1176  * See rdcDataFifoCmd register.
1177  * Fields:
1178  *     For writes, data which is written into rx data ram. For reads,
1179  *     data read from the rx data ram.
1180  */
1181 typedef union {
1182 	uint64_t value;
1183 	struct {
1184 #if defined(_BIG_ENDIAN)
1185 		uint32_t	data:32;
1186 		uint32_t	data_l:32;
1187 #else
1188 		uint32_t	data_l:32;
1189 		uint32_t	data:32;
1190 #endif
1191 	} bits;
1192 } rdc_data_fifo_data_hi_t;
1193 
1194 
1195 /*
1196  * Register: RdcDataFifoDataEcc
1197  * Rx DMA Data Fifo ECC Data
1198  * Description: 16 bits ECC data read or written to the Rx Data FIFO.
1199  * See rdcDataFifoCmd register.
1200  * Fields:
1201  *     For writes, data which is written into rx data ram. For reads,
1202  *     data read from the rx data ram.
1203  *     For writes, data which is written into rx data ram. For reads,
1204  *     data read from the rx data ram.
1205  */
1206 typedef union {
1207 	uint64_t value;
1208 	struct {
1209 #if defined(_BIG_ENDIAN)
1210 		uint32_t	rsrvd:32;
1211 		uint32_t	rsrvd1:16;
1212 		uint32_t	ecc_data_hi:8;
1213 		uint32_t	ecc_data_lo:8;
1214 #else
1215 		uint32_t	ecc_data_lo:8;
1216 		uint32_t	ecc_data_hi:8;
1217 		uint32_t	rsrvd1:16;
1218 		uint32_t	rsrvd:32;
1219 #endif
1220 	} bits;
1221 } rdc_data_fifo_data_ecc_t;
1222 
1223 
1224 /*
1225  * Register: RdcStatIntDbg
1226  * RDC Debug Control and Status Interrupt
1227  * Description: RDC debug control and status interrupt register.
1228  * Debug RDC control and status register bits to check if interrupt
1229  * is asserted used to detect error conditions.
1230  * Fields:
1231  *     Set to 1 to enable interrupt Part of LDF 1.
1232  *     Set to 1 to enable interrupt Part of LDF 1.
1233  *     Set to 1 to enable interrupt Part of LDF 0.
1234  *     Set to 1 to enable interrupt Part of LDF 0.
1235  *     Set to 1 to enable interrupt Part of LDF 1.
1236  *     Set to 1 to enable interrupt Part of LDF 1.
1237  *     Set to 1 to enable interrupt Part of LDF 1.
1238  *     Set to 1 to enable interrupt
1239  *     Set to 1 to enable interrupt Part of LDF 1.
1240  *     Set to 1 to enable interrupt Part of LDF 1.
1241  *     Set to 1 to enable interrupt Part of LDF 1.
1242  */
1243 typedef union {
1244 	uint64_t value;
1245 	struct {
1246 #if defined(_BIG_ENDIAN)
1247 		uint32_t	rsrvd:10;
1248 		uint32_t	rbr_cpl_to:1;
1249 		uint32_t	peu_resp_err:1;
1250 		uint32_t	rsrvd1:5;
1251 		uint32_t	rcr_thres:1;
1252 		uint32_t	rcr_to:1;
1253 		uint32_t	rcr_shadow_par_err:1;
1254 		uint32_t	rbr_prefetch_par_err:1;
1255 		uint32_t	rsrvd2:2;
1256 		uint32_t	rbr_pre_empty:1;
1257 		uint32_t	rcr_shadow_full:1;
1258 		uint32_t	rsrvd3:2;
1259 		uint32_t	rcr_full:1;
1260 		uint32_t	rbr_empty:1;
1261 		uint32_t	rbr_full:1;
1262 		uint32_t	rsrvd4:2;
1263 		uint32_t	rsrvd5:32;
1264 #else
1265 		uint32_t	rsrvd5:32;
1266 		uint32_t	rsrvd4:2;
1267 		uint32_t	rbr_full:1;
1268 		uint32_t	rbr_empty:1;
1269 		uint32_t	rcr_full:1;
1270 		uint32_t	rsrvd3:2;
1271 		uint32_t	rcr_shadow_full:1;
1272 		uint32_t	rbr_pre_empty:1;
1273 		uint32_t	rsrvd2:2;
1274 		uint32_t	rbr_prefetch_par_err:1;
1275 		uint32_t	rcr_shadow_par_err:1;
1276 		uint32_t	rcr_to:1;
1277 		uint32_t	rcr_thres:1;
1278 		uint32_t	rsrvd1:5;
1279 		uint32_t	peu_resp_err:1;
1280 		uint32_t	rbr_cpl_to:1;
1281 		uint32_t	rsrvd:10;
1282 #endif
1283 	} bits;
1284 } rdc_stat_int_dbg_t;
1285 
1286 
1287 /*
1288  * Register: RdcPrefParLog
1289  * Rx DMA Prefetch Buffer Parity Log
1290  * Description: RDC DMA Prefetch Buffer parity log register This
1291  * register logs the first parity error that is encountered. Writing
1292  * a 1 to RdcStat::rbrPrefetchParErr clears this register
1293  * Fields:
1294  *     Address of parity error
1295  */
1296 typedef union {
1297 	uint64_t value;
1298 	struct {
1299 #if defined(_BIG_ENDIAN)
1300 		uint32_t	rsrvd:32;
1301 		uint32_t	rsrvd_l:25;
1302 		uint32_t	address:7;
1303 #else
1304 		uint32_t	address:7;
1305 		uint32_t	rsrvd_l:25;
1306 		uint32_t	rsrvd:32;
1307 #endif
1308 	} bits;
1309 } rdc_pref_par_log_t;
1310 
1311 
1312 /*
1313  * Register: RdcShadowParLog
1314  * Rx DMA Shadow Tail Parity Log
1315  * Description: RDC DMA Shadow Tail parity log register This register
1316  * logs the first parity error that is encountered. Writing a 1 to
1317  * RdcStat::rcrShadowParErr clears this register
1318  * Fields:
1319  *     Address of parity error
1320  */
1321 typedef union {
1322 	uint64_t value;
1323 	struct {
1324 #if defined(_BIG_ENDIAN)
1325 		uint32_t	rsrvd:32;
1326 		uint32_t	rsrvd1:26;
1327 		uint32_t	address:6;
1328 #else
1329 		uint32_t	address:6;
1330 		uint32_t	rsrvd1:26;
1331 		uint32_t	rsrvd:32;
1332 #endif
1333 	} bits;
1334 } rdc_shadow_par_log_t;
1335 
1336 
1337 /*
1338  * Register: RdcCtrlFifoEccLog
1339  * Rx DMA Control Fifo ECC Log
1340  * Description: RDC DMA Control FIFO ECC log register This register
1341  * logs the first ECC error that is encountered. A double-bit ecc
1342  * error over writes any single-bit ecc error previously logged
1343  * Fields:
1344  *     Address of ECC error for upper 64 bits Writing a 1 to
1345  *     RdcFifoErrStat::rxCtrlFifoDed[1] or
1346  *     RdcFifoErrStat::rxCtrlFifoSec[1] clears this register
1347  *     Address of ECC error for lower 64 bits Writing a 1 to
1348  *     RdcFifoErrStat::rxCtrlFifoDed[0] or
1349  *     RdcFifoErrStat::rxCtrlFifoSec[0] clears this register
1350  *     ECC syndrome for upper 64 bits Writing a 1 to
1351  *     RdcFifoErrStat::rxCtrlFifoDed[1] or
1352  *     RdcFifoErrStat::rxCtrlFifoSec[1] clears this register
1353  *     ECC syndrome for lower 64 bits Writing a 1 to
1354  *     RdcFifoErrStat::rxCtrlFifoDed[0] or
1355  *     RdcFifoErrStat::rxCtrlFifoSec[0] clears this register
1356  */
1357 typedef union {
1358 	uint64_t value;
1359 	struct {
1360 #if defined(_BIG_ENDIAN)
1361 		uint32_t	rsrvd:7;
1362 		uint32_t	address_hi:9;
1363 		uint32_t	rsrvd1:7;
1364 		uint32_t	address_lo:9;
1365 		uint32_t	rsrvd2:8;
1366 		uint32_t	syndrome_hi:8;
1367 		uint32_t	rsrvd3:8;
1368 		uint32_t	syndrome_lo:8;
1369 #else
1370 		uint32_t	syndrome_lo:8;
1371 		uint32_t	rsrvd3:8;
1372 		uint32_t	syndrome_hi:8;
1373 		uint32_t	rsrvd2:8;
1374 		uint32_t	address_lo:9;
1375 		uint32_t	rsrvd1:7;
1376 		uint32_t	address_hi:9;
1377 		uint32_t	rsrvd:7;
1378 #endif
1379 	} bits;
1380 } rdc_ctrl_fifo_ecc_log_t;
1381 
1382 
1383 /*
1384  * Register: RdcDataFifoEccLog
1385  * Rx DMA Data Fifo ECC Log
1386  * Description: RDC DMA data FIFO ECC log register This register logs
1387  * the first ECC error that is encountered. A double-bit ecc error
1388  * over writes any single-bit ecc error previously logged
1389  * Fields:
1390  *     Address of ECC error for upper 64 bits Writing a 1 to
1391  *     RdcFifoErrStat::rxDataFifoDed[1] or
1392  *     RdcFifoErrStat::rxDataFifoSec[1] clears this register
1393  *     Address of ECC error for lower 64 bits Writing a 1 to
1394  *     RdcFifoErrStat::rxDataFifoDed[0] or
1395  *     RdcFifoErrStat::rxDataFifoSec[0] clears this register
1396  *     ECC syndrome for upper 64 bits Writing a 1 to
1397  *     RdcFifoErrStat::rxDataFifoDed[1] or
1398  *     RdcFifoErrStat::rxDataFifoSec[1] clears this register
1399  *     ECC syndrome for lower 64 bits Writing a 1 to
1400  *     RdcFifoErrStat::rxDataFifoDed[0] or
1401  *     RdcFifoErrStat::rxDataFifoSec[0] clears this register
1402  */
1403 typedef union {
1404 	uint64_t value;
1405 	struct {
1406 #if defined(_BIG_ENDIAN)
1407 		uint32_t	rsrvd:5;
1408 		uint32_t	address_hi:11;
1409 		uint32_t	rsrvd1:5;
1410 		uint32_t	address_lo:11;
1411 		uint32_t	rsrvd2:8;
1412 		uint32_t	syndrome_hi:8;
1413 		uint32_t	rsrvd3:8;
1414 		uint32_t	syndrome_lo:8;
1415 #else
1416 		uint32_t	syndrome_lo:8;
1417 		uint32_t	rsrvd3:8;
1418 		uint32_t	syndrome_hi:8;
1419 		uint32_t	rsrvd2:8;
1420 		uint32_t	address_lo:11;
1421 		uint32_t	rsrvd1:5;
1422 		uint32_t	address_hi:11;
1423 		uint32_t	rsrvd:5;
1424 #endif
1425 	} bits;
1426 } rdc_data_fifo_ecc_log_t;
1427 
1428 
1429 /*
1430  * Register: RdcFifoErrIntMask
1431  * FIFO Error Interrupt Mask
1432  * Description: FIFO Error interrupt mask register. Control the
1433  * interrupt assertion of FIFO Errors. see FIFO Error Status register
1434  * for more description
1435  * Fields:
1436  *     Set to 0 to enable flagging when rx ctrl ram logs ecc single
1437  *     bit error Part of Device Error 0.
1438  *     Set to 0 to enable flagging when rx ctrl ram logs ecc double
1439  *     bit error Part of Device Error 1.
1440  *     Set to 0 to enable flagging when rx data ram logs ecc single
1441  *     bit error Part of Device Error 0.
1442  *     Set to 0 to enable flagging when rx data ram logs ecc double
1443  *     bit error Part of Device Error 1.
1444  */
1445 typedef union {
1446 	uint64_t value;
1447 	struct {
1448 #if defined(_BIG_ENDIAN)
1449 		uint32_t	rsrvd:32;
1450 		uint32_t	rsrvd1:24;
1451 		uint32_t	rx_ctrl_fifo_sec:2;
1452 		uint32_t	rx_ctrl_fifo_ded:2;
1453 		uint32_t	rx_data_fifo_sec:2;
1454 		uint32_t	rx_data_fifo_ded:2;
1455 #else
1456 		uint32_t	rx_data_fifo_ded:2;
1457 		uint32_t	rx_data_fifo_sec:2;
1458 		uint32_t	rx_ctrl_fifo_ded:2;
1459 		uint32_t	rx_ctrl_fifo_sec:2;
1460 		uint32_t	rsrvd1:24;
1461 		uint32_t	rsrvd:32;
1462 #endif
1463 	} bits;
1464 } rdc_fifo_err_int_mask_t;
1465 
1466 
1467 /*
1468  * Register: RdcFifoErrStat
1469  * FIFO Error Status
1470  * Description: FIFO Error Status register. Log status of FIFO
1471  * Errors. Rx Data buffer is physically two seperate memory, each of
1472  * the two error bits point to one of the memory. Each entry in the
1473  * rx ctrl point to 2 buffer locations and they are read seperatly.
1474  * The two error bits point to each half of the entry.
1475  * Fields:
1476  *     Set to 1 by HW to indicate rx control ram received a ecc
1477  *     single bit error Writing a 1 to either bit clears the
1478  *     RdcCtrlFifoEccLog register Non-Fatal error. Part of Device
1479  *     Error 0
1480  *     Set to 1 by HW to indicate rx control ram received a ecc
1481  *     double bit error Writing a 1 to either bit clears the
1482  *     RdcCtrlFifoEccLog register Fatal error. Part of Device Error 1
1483  *     Set to 1 by HW to indicate rx data ram received a ecc single
1484  *     bit error Writing a 1 to either bit clears the
1485  *     RdcDataFifoEccLog register Non-Fatal error. Part of Device
1486  *     Error 0
1487  *     Set to 1 by HW to indicate rx data ram received a ecc double
1488  *     bit error Writing a 1 to either bit clears the
1489  *     RdcDataFifoEccLog register Fatal error. Part of Device Error 1
1490  */
1491 typedef union {
1492 	uint64_t value;
1493 	struct {
1494 #if defined(_BIG_ENDIAN)
1495 		uint32_t	rsrvd:32;
1496 		uint32_t	rsrvd_l:24;
1497 		uint32_t	rx_ctrl_fifo_sec:2;
1498 		uint32_t	rx_ctrl_fifo_ded:2;
1499 		uint32_t	rx_data_fifo_sec:2;
1500 		uint32_t	rx_data_fifo_ded:2;
1501 #else
1502 		uint32_t	rx_data_fifo_ded:2;
1503 		uint32_t	rx_data_fifo_sec:2;
1504 		uint32_t	rx_ctrl_fifo_ded:2;
1505 		uint32_t	rx_ctrl_fifo_sec:2;
1506 		uint32_t	rsrvd_l:24;
1507 		uint32_t	rsrvd:32;
1508 #endif
1509 	} bits;
1510 } rdc_fifo_err_stat_t;
1511 
1512 
1513 /*
1514  * Register: RdcFifoErrIntDbg
1515  * FIFO Error Interrupt Debug
1516  * Description: FIFO Error interrupt Debug register. Debug Control
1517  * the interrupt assertion of FIFO Errors.
1518  * Fields:
1519  *     Set to 1 to enable interrupt Part of Device Error 0.
1520  *     Set to 1 to enable interrupt Part of Device Error 1.
1521  *     Set to 1 to enable interrupt Part of Device Error 0.
1522  *     Set to 1 to enable interrupt Part of Device Error 1.
1523  */
1524 typedef union {
1525 	uint64_t value;
1526 	struct {
1527 #if defined(_BIG_ENDIAN)
1528 		uint32_t	rsrvd:32;
1529 		uint32_t	rsrvd1:24;
1530 		uint32_t	rx_ctrl_fifo_sec:2;
1531 		uint32_t	rx_ctrl_fifo_ded:2;
1532 		uint32_t	rx_data_fifo_sec:2;
1533 		uint32_t	rx_data_fifo_ded:2;
1534 #else
1535 		uint32_t	rx_data_fifo_ded:2;
1536 		uint32_t	rx_data_fifo_sec:2;
1537 		uint32_t	rx_ctrl_fifo_ded:2;
1538 		uint32_t	rx_ctrl_fifo_sec:2;
1539 		uint32_t	rsrvd1:24;
1540 		uint32_t	rsrvd:32;
1541 #endif
1542 	} bits;
1543 } rdc_fifo_err_int_dbg_t;
1544 
1545 
1546 /*
1547  * Register: RdcPeuTxnLog
1548  * PEU Transaction Log
1549  * Description: PEU Transaction Log register. Counts the memory read
1550  * and write requests sent to peu block. For debug only.
1551  * Fields:
1552  *     Counts the memory write transactions sent to peu block. This
1553  *     counter saturates. This counter increments when vnmDbg is on
1554  *     Counts the memory read transactions sent to peu block. This
1555  *     counter saturates. This counter increments when vnmDbg is on
1556  */
1557 typedef union {
1558 	uint64_t value;
1559 	struct {
1560 #if defined(_BIG_ENDIAN)
1561 		uint32_t	rsrvd:32;
1562 		uint32_t	rsrvd1:16;
1563 		uint32_t	peu_mem_wr_count:8;
1564 		uint32_t	peu_mem_rd_count:8;
1565 #else
1566 		uint32_t	peu_mem_rd_count:8;
1567 		uint32_t	peu_mem_wr_count:8;
1568 		uint32_t	rsrvd1:16;
1569 		uint32_t	rsrvd:32;
1570 #endif
1571 	} bits;
1572 } rdc_peu_txn_log_t;
1573 
1574 
1575 /*
1576  * Register: RdcDbgTrainingVec
1577  * Debug Training Vector
1578  * Description: Debug Training Vector register Debug Training Vector
1579  * for the coreClk domain. For the pcieClk domain, the dbgxMsb and
1580  * dbgyMsb values are flipped on the debug bus.
1581  * Fields:
1582  *     Blade Number, the value read depends on the blade this block
1583  *     resides
1584  *     debug training vector the sub-group select value of 0 selects
1585  *     this vector
1586  *     Blade Number, the value read depends on the blade this block
1587  *     resides
1588  *     debug training vector the sub-group select value of 0 selects
1589  *     this vector
1590  */
1591 typedef union {
1592 	uint64_t value;
1593 	struct {
1594 #if defined(_BIG_ENDIAN)
1595 		uint32_t	rsrvd:32;
1596 		uint32_t	dbgx_msb:1;
1597 		uint32_t	dbgx_bld_num:3;
1598 		uint32_t	dbgx_training_vec:12;
1599 		uint32_t	dbgy_msb:1;
1600 		uint32_t	dbgy_bld_num:3;
1601 		uint32_t	dbgy_training_vec:12;
1602 #else
1603 		uint32_t	dbgy_training_vec:12;
1604 		uint32_t	dbgy_bld_num:3;
1605 		uint32_t	dbgy_msb:1;
1606 		uint32_t	dbgx_training_vec:12;
1607 		uint32_t	dbgx_bld_num:3;
1608 		uint32_t	dbgx_msb:1;
1609 		uint32_t	rsrvd:32;
1610 #endif
1611 	} bits;
1612 } rdc_dbg_training_vec_t;
1613 
1614 
1615 /*
1616  * Register: RdcDbgGrpSel
1617  * Debug Group Select
1618  * Description: Debug Group Select register. Debug Group Select
1619  * register selects the group of signals brought out on the debug
1620  * port
1621  * Fields:
1622  *     high 32b sub-group select
1623  *     low 32b sub-group select
1624  */
1625 typedef union {
1626 	uint64_t value;
1627 	struct {
1628 #if defined(_BIG_ENDIAN)
1629 		uint32_t	rsrvd:32;
1630 		uint32_t	rsrvd_l:16;
1631 		uint32_t	dbg_h32_sub_sel:8;
1632 		uint32_t	dbg_l32_sub_sel:8;
1633 #else
1634 		uint32_t	dbg_l32_sub_sel:8;
1635 		uint32_t	dbg_h32_sub_sel:8;
1636 		uint32_t	rsrvd_l:16;
1637 		uint32_t	rsrvd:32;
1638 #endif
1639 	} bits;
1640 } rdc_dbg_grp_sel_t;
1641 
1642 
1643 #ifdef	__cplusplus
1644 }
1645 #endif
1646 
1647 #endif	/* _HXGE_RDC_HW_H */
1648