1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DAL_HW_SHARED_H__ 27 #define __DAL_HW_SHARED_H__ 28 29 #include "os_types.h" 30 #include "fixed31_32.h" 31 #include "dc_hw_types.h" 32 33 /****************************************************************************** 34 * Data types shared between different Virtual HW blocks 35 ******************************************************************************/ 36 37 #define MAX_AUDIOS 7 38 39 /** 40 * @MAX_PIPES: 41 * 42 * Every ASIC support a fixed number of pipes; MAX_PIPES defines a large number 43 * to be used inside loops and for determining array sizes. 44 */ 45 #define MAX_PIPES 6 46 #define MAX_PHANTOM_PIPES (MAX_PIPES / 2) 47 48 #define MAX_DPIA 6 49 #define MAX_CONNECTOR 6 50 #define MAX_VIRTUAL_LINKS 4 51 52 #define MAX_LINKS (MAX_DPIA + MAX_CONNECTOR + MAX_VIRTUAL_LINKS) 53 54 /** 55 * define MAX_DIG_LINK_ENCODERS - maximum number of digital encoders 56 * 57 * Digital encoders are ENGINE_ID_DIGA...G, there are at most 7, 58 * although not every GPU may have that many. 59 */ 60 #define MAX_DIG_LINK_ENCODERS 7 61 62 /** 63 * define MAX_DAC_LINK_ENCODERS - maximum number of analog link encoders 64 * 65 * Analog encoders are ENGINE_ID_DACA/B, there are at most 2, 66 * although not every GPU may have that many. Modern GPUs typically 67 * don't have analog encoders. 68 */ 69 #define MAX_DAC_LINK_ENCODERS 2 70 71 /** 72 * define MAX_LINK_ENCODERS - maximum number link encoders in total 73 * 74 * This includes both analog and digital encoders. 75 */ 76 #define MAX_LINK_ENCODERS (MAX_DIG_LINK_ENCODERS + MAX_DAC_LINK_ENCODERS) 77 78 #define MAX_DWB_PIPES 1 79 #define MAX_HPO_DP2_ENCODERS 4 80 #define MAX_HPO_DP2_LINK_ENCODERS 4 81 82 /* Pipe topology snapshot structures */ 83 #define MAX_TOPOLOGY_SNAPSHOTS 4 84 85 struct pipe_topology_line { 86 bool is_phantom_pipe; 87 int plane_idx; 88 int slice_idx; 89 int stream_idx; 90 int dpp_inst; 91 int opp_inst; 92 int tg_inst; 93 }; 94 95 struct pipe_topology_snapshot { 96 struct pipe_topology_line pipe_log_lines[MAX_PIPES]; 97 int line_count; 98 uint64_t timestamp_us; 99 int stream_count; 100 int phantom_stream_count; 101 }; 102 103 struct pipe_topology_history { 104 struct pipe_topology_snapshot snapshots[MAX_TOPOLOGY_SNAPSHOTS]; 105 int current_snapshot_index; 106 }; 107 108 struct gamma_curve { 109 uint32_t offset; 110 uint32_t segments_num; 111 }; 112 113 struct curve_points { 114 struct fixed31_32 x; 115 struct fixed31_32 y; 116 struct fixed31_32 offset; 117 struct fixed31_32 slope; 118 119 uint32_t custom_float_x; 120 uint32_t custom_float_y; 121 uint32_t custom_float_offset; 122 uint32_t custom_float_slope; 123 }; 124 125 struct curve_points3 { 126 struct curve_points red; 127 struct curve_points green; 128 struct curve_points blue; 129 }; 130 131 struct pwl_result_data { 132 struct fixed31_32 red; 133 struct fixed31_32 green; 134 struct fixed31_32 blue; 135 136 struct fixed31_32 delta_red; 137 struct fixed31_32 delta_green; 138 struct fixed31_32 delta_blue; 139 140 uint32_t red_reg; 141 uint32_t green_reg; 142 uint32_t blue_reg; 143 144 uint32_t delta_red_reg; 145 uint32_t delta_green_reg; 146 uint32_t delta_blue_reg; 147 }; 148 149 struct dc_rgb { 150 uint32_t red; 151 uint32_t green; 152 uint32_t blue; 153 }; 154 155 struct tetrahedral_33x33x33 { 156 struct dc_rgb lut0[8985]; 157 struct dc_rgb lut1[8984]; 158 struct dc_rgb lut2[8984]; 159 struct dc_rgb lut3[8984]; 160 }; 161 162 struct tetrahedral_17x17x17 { 163 struct dc_rgb lut0[1229]; 164 struct dc_rgb lut1[1228]; 165 struct dc_rgb lut2[1228]; 166 struct dc_rgb lut3[1228]; 167 }; 168 struct tetrahedral_9x9x9 { 169 struct dc_rgb lut0[183]; 170 struct dc_rgb lut1[182]; 171 struct dc_rgb lut2[182]; 172 struct dc_rgb lut3[182]; 173 }; 174 175 enum lut_dimension { 176 LUT_DIM_INVALID = 0, 177 LUT_DIM_9 = 9, 178 LUT_DIM_17 = 17, 179 LUT_DIM_33 = 33, 180 }; 181 182 struct tetrahedral_params { 183 union { 184 //TODO: Uncomment when in use. 185 // struct tetrahedral_33x33x33 tetrahedral_33; 186 struct tetrahedral_17x17x17 tetrahedral_17; 187 struct tetrahedral_9x9x9 tetrahedral_9; 188 }; 189 bool use_tetrahedral_9; 190 bool use_12bits; 191 enum lut_dimension lut_dim; 192 }; 193 194 /* arr_curve_points - regamma regions/segments specification 195 * arr_points - beginning and end point specified separately (only one on DCE) 196 * corner_points - beginning and end point for all 3 colors (DCN) 197 * rgb_resulted - final curve 198 */ 199 struct pwl_params { 200 struct gamma_curve arr_curve_points[34]; 201 union { 202 struct curve_points arr_points[2]; 203 struct curve_points3 corner_points[2]; 204 }; 205 struct pwl_result_data rgb_resulted[256 + 3]; 206 uint32_t hw_points_num; 207 }; 208 209 /* move to dpp 210 * while we are moving functionality out of opp to dpp to align 211 * HW programming to HW IP, we define these struct in hw_shared 212 * so we can still compile while refactoring 213 */ 214 215 enum lb_pixel_depth { 216 /* do not change the values because it is used as bit vector */ 217 LB_PIXEL_DEPTH_18BPP = 1, 218 LB_PIXEL_DEPTH_24BPP = 2, 219 LB_PIXEL_DEPTH_30BPP = 4, 220 LB_PIXEL_DEPTH_36BPP = 8 221 }; 222 223 enum graphics_csc_adjust_type { 224 GRAPHICS_CSC_ADJUST_TYPE_BYPASS = 0, 225 GRAPHICS_CSC_ADJUST_TYPE_HW, /* without adjustments */ 226 GRAPHICS_CSC_ADJUST_TYPE_SW /*use adjustments */ 227 }; 228 229 enum ipp_degamma_mode { 230 IPP_DEGAMMA_MODE_BYPASS, 231 IPP_DEGAMMA_MODE_HW_sRGB, 232 IPP_DEGAMMA_MODE_HW_xvYCC, 233 IPP_DEGAMMA_MODE_USER_PWL 234 }; 235 236 enum gamcor_mode { 237 GAMCOR_MODE_BYPASS, 238 GAMCOR_MODE_RESERVED_1, 239 GAMCOR_MODE_USER_PWL, 240 GAMCOR_MODE_RESERVED_3 241 }; 242 243 enum ipp_output_format { 244 IPP_OUTPUT_FORMAT_12_BIT_FIX, 245 IPP_OUTPUT_FORMAT_16_BIT_BYPASS, 246 IPP_OUTPUT_FORMAT_FLOAT 247 }; 248 249 enum expansion_mode { 250 EXPANSION_MODE_DYNAMIC, 251 EXPANSION_MODE_ZERO 252 }; 253 254 struct default_adjustment { 255 enum lb_pixel_depth lb_color_depth; 256 enum dc_color_space out_color_space; 257 enum dc_color_space in_color_space; 258 enum dc_color_depth color_depth; 259 enum dc_pixel_format surface_pixel_format; 260 enum graphics_csc_adjust_type csc_adjust_type; 261 bool force_hw_default; 262 }; 263 264 265 struct out_csc_color_matrix { 266 enum dc_color_space color_space; 267 uint16_t regval[12]; 268 }; 269 270 enum gamut_remap_select { 271 GAMUT_REMAP_BYPASS = 0, 272 GAMUT_REMAP_COEFF, 273 GAMUT_REMAP_COMA_COEFF, 274 GAMUT_REMAP_COMB_COEFF 275 }; 276 277 enum opp_regamma { 278 OPP_REGAMMA_BYPASS = 0, 279 OPP_REGAMMA_SRGB, 280 OPP_REGAMMA_XVYCC, 281 OPP_REGAMMA_USER 282 }; 283 284 enum optc_dsc_mode { 285 OPTC_DSC_DISABLED = 0, 286 OPTC_DSC_ENABLED_444 = 1, /* 'RGB 444' or 'Simple YCbCr 4:2:2' (4:2:2 upsampled to 4:4:4) */ 287 OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED = 2 /* Native 4:2:2 or 4:2:0 */ 288 }; 289 290 struct dc_bias_and_scale { 291 uint32_t scale_red; 292 uint32_t bias_red; 293 uint32_t scale_green; 294 uint32_t bias_green; 295 uint32_t scale_blue; 296 uint32_t bias_blue; 297 bool bias_and_scale_valid; 298 }; 299 300 enum test_pattern_dyn_range { 301 TEST_PATTERN_DYN_RANGE_VESA = 0, 302 TEST_PATTERN_DYN_RANGE_CEA 303 }; 304 305 enum test_pattern_mode { 306 TEST_PATTERN_MODE_COLORSQUARES_RGB = 0, 307 TEST_PATTERN_MODE_COLORSQUARES_YCBCR601, 308 TEST_PATTERN_MODE_COLORSQUARES_YCBCR709, 309 TEST_PATTERN_MODE_VERTICALBARS, 310 TEST_PATTERN_MODE_HORIZONTALBARS, 311 TEST_PATTERN_MODE_SINGLERAMP_RGB, 312 TEST_PATTERN_MODE_DUALRAMP_RGB, 313 TEST_PATTERN_MODE_XR_BIAS_RGB 314 }; 315 316 enum test_pattern_color_format { 317 TEST_PATTERN_COLOR_FORMAT_BPC_6 = 0, 318 TEST_PATTERN_COLOR_FORMAT_BPC_8, 319 TEST_PATTERN_COLOR_FORMAT_BPC_10, 320 TEST_PATTERN_COLOR_FORMAT_BPC_12 321 }; 322 323 enum controller_dp_test_pattern { 324 CONTROLLER_DP_TEST_PATTERN_D102 = 0, 325 CONTROLLER_DP_TEST_PATTERN_SYMBOLERROR, 326 CONTROLLER_DP_TEST_PATTERN_PRBS7, 327 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES, 328 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS, 329 CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS, 330 CONTROLLER_DP_TEST_PATTERN_COLORRAMP, 331 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, 332 CONTROLLER_DP_TEST_PATTERN_RESERVED_8, 333 CONTROLLER_DP_TEST_PATTERN_RESERVED_9, 334 CONTROLLER_DP_TEST_PATTERN_RESERVED_A, 335 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA, 336 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR 337 }; 338 339 enum controller_dp_color_space { 340 CONTROLLER_DP_COLOR_SPACE_RGB, 341 CONTROLLER_DP_COLOR_SPACE_YCBCR601, 342 CONTROLLER_DP_COLOR_SPACE_YCBCR709, 343 CONTROLLER_DP_COLOR_SPACE_UDEFINED 344 }; 345 346 enum dc_lut_mode { 347 LUT_BYPASS, 348 LUT_RAM_A, 349 LUT_RAM_B 350 }; 351 352 /** 353 * speakersToChannels 354 * 355 * @brief 356 * translate speakers to channels 357 * 358 * FL - Front Left 359 * FR - Front Right 360 * RL - Rear Left 361 * RR - Rear Right 362 * RC - Rear Center 363 * FC - Front Center 364 * FLC - Front Left Center 365 * FRC - Front Right Center 366 * RLC - Rear Left Center 367 * RRC - Rear Right Center 368 * LFE - Low Freq Effect 369 * 370 * FC 371 * FLC FRC 372 * FL FR 373 * 374 * LFE 375 * () 376 * 377 * 378 * RL RR 379 * RLC RRC 380 * RC 381 * 382 * ch 8 7 6 5 4 3 2 1 383 * 0b00000011 - - - - - - FR FL 384 * 0b00000111 - - - - - LFE FR FL 385 * 0b00001011 - - - - FC - FR FL 386 * 0b00001111 - - - - FC LFE FR FL 387 * 0b00010011 - - - RC - - FR FL 388 * 0b00010111 - - - RC - LFE FR FL 389 * 0b00011011 - - - RC FC - FR FL 390 * 0b00011111 - - - RC FC LFE FR FL 391 * 0b00110011 - - RR RL - - FR FL 392 * 0b00110111 - - RR RL - LFE FR FL 393 * 0b00111011 - - RR RL FC - FR FL 394 * 0b00111111 - - RR RL FC LFE FR FL 395 * 0b01110011 - RC RR RL - - FR FL 396 * 0b01110111 - RC RR RL - LFE FR FL 397 * 0b01111011 - RC RR RL FC - FR FL 398 * 0b01111111 - RC RR RL FC LFE FR FL 399 * 0b11110011 RRC RLC RR RL - - FR FL 400 * 0b11110111 RRC RLC RR RL - LFE FR FL 401 * 0b11111011 RRC RLC RR RL FC - FR FL 402 * 0b11111111 RRC RLC RR RL FC LFE FR FL 403 * 0b11000011 FRC FLC - - - - FR FL 404 * 0b11000111 FRC FLC - - - LFE FR FL 405 * 0b11001011 FRC FLC - - FC - FR FL 406 * 0b11001111 FRC FLC - - FC LFE FR FL 407 * 0b11010011 FRC FLC - RC - - FR FL 408 * 0b11010111 FRC FLC - RC - LFE FR FL 409 * 0b11011011 FRC FLC - RC FC - FR FL 410 * 0b11011111 FRC FLC - RC FC LFE FR FL 411 * 0b11110011 FRC FLC RR RL - - FR FL 412 * 0b11110111 FRC FLC RR RL - LFE FR FL 413 * 0b11111011 FRC FLC RR RL FC - FR FL 414 * 0b11111111 FRC FLC RR RL FC LFE FR FL 415 * 416 * @param 417 * speakers - speaker information as it comes from CEA audio block 418 */ 419 /* translate speakers to channels */ 420 421 union audio_cea_channels { 422 uint8_t all; 423 struct audio_cea_channels_bits { 424 uint32_t FL:1; 425 uint32_t FR:1; 426 uint32_t LFE:1; 427 uint32_t FC:1; 428 uint32_t RL_RC:1; 429 uint32_t RR:1; 430 uint32_t RC_RLC_FLC:1; 431 uint32_t RRC_FRC:1; 432 } channels; 433 }; 434 435 #endif /* __DAL_HW_SHARED_H__ */ 436