1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 *
4 * hda_intel.c - Implementation of primary alsa driver code base
5 * for Intel HD Audio.
6 *
7 * Copyright(c) 2004 Intel Corporation
8 *
9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
10 * PeiSen Hou <pshou@realtek.com.tw>
11 *
12 * CONTACTS:
13 *
14 * Matt Jared matt.jared@intel.com
15 * Andy Kopp andy.kopp@intel.com
16 * Dan Kogan dan.d.kogan@intel.com
17 *
18 * CHANGES:
19 *
20 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
21 */
22
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/moduleparam.h>
29 #include <linux/init.h>
30 #include <linux/slab.h>
31 #include <linux/pci.h>
32 #include <linux/mutex.h>
33 #include <linux/io.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/clocksource.h>
36 #include <linux/time.h>
37 #include <linux/completion.h>
38 #include <linux/acpi.h>
39 #include <linux/pgtable.h>
40 #include <linux/dmi.h>
41
42 #ifdef CONFIG_X86
43 /* for snoop control */
44 #include <asm/set_memory.h>
45 #include <asm/cpufeature.h>
46 #endif
47 #include <sound/core.h>
48 #include <sound/initval.h>
49 #include <sound/hdaudio.h>
50 #include <sound/hda_i915.h>
51 #include <sound/intel-dsp-config.h>
52 #include <linux/vgaarb.h>
53 #include <linux/vga_switcheroo.h>
54 #include <linux/apple-gmux.h>
55 #include <linux/firmware.h>
56 #include <sound/hda_codec.h>
57 #include "hda_controller.h"
58 #include "hda_intel.h"
59
60 #define CREATE_TRACE_POINTS
61 #include "hda_intel_trace.h"
62
63 /* position fix mode */
64 enum {
65 POS_FIX_AUTO,
66 POS_FIX_LPIB,
67 POS_FIX_POSBUF,
68 POS_FIX_VIACOMBO,
69 POS_FIX_COMBO,
70 POS_FIX_SKL,
71 POS_FIX_FIFO,
72 };
73
74 /* Defines for ATI HD Audio support in SB450 south bridge */
75 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
76 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
77
78 /* Defines for Nvidia HDA support */
79 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
80 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
81 #define NVIDIA_HDA_ISTRM_COH 0x4d
82 #define NVIDIA_HDA_OSTRM_COH 0x4c
83 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
84
85 /* Defines for Intel SCH HDA snoop control */
86 #define INTEL_HDA_CGCTL 0x48
87 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)
88 #define INTEL_SCH_HDA_DEVC 0x78
89 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
90
91 /* max number of SDs */
92 /* ICH, ATI and VIA have 4 playback and 4 capture */
93 #define ICH6_NUM_CAPTURE 4
94 #define ICH6_NUM_PLAYBACK 4
95
96 /* ULI has 6 playback and 5 capture */
97 #define ULI_NUM_CAPTURE 5
98 #define ULI_NUM_PLAYBACK 6
99
100 /* ATI HDMI may have up to 8 playbacks and 0 capture */
101 #define ATIHDMI_NUM_CAPTURE 0
102 #define ATIHDMI_NUM_PLAYBACK 8
103
104
105 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
106 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
107 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
108 static char *model[SNDRV_CARDS];
109 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
110 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
111 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
112 static int probe_only[SNDRV_CARDS];
113 static int jackpoll_ms[SNDRV_CARDS];
114 static int single_cmd = -1;
115 static int enable_msi = -1;
116 #ifdef CONFIG_SND_HDA_PATCH_LOADER
117 static char *patch[SNDRV_CARDS];
118 #endif
119 #ifdef CONFIG_SND_HDA_INPUT_BEEP
120 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
121 CONFIG_SND_HDA_INPUT_BEEP_MODE};
122 #endif
123 static bool dmic_detect = 1;
124 static bool ctl_dev_id = IS_ENABLED(CONFIG_SND_HDA_CTL_DEV_ID) ? 1 : 0;
125
126 module_param_array(index, int, NULL, 0444);
127 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
128 module_param_array(id, charp, NULL, 0444);
129 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
130 module_param_array(enable, bool, NULL, 0444);
131 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
132 module_param_array(model, charp, NULL, 0444);
133 MODULE_PARM_DESC(model, "Use the given board model.");
134 module_param_array(position_fix, int, NULL, 0444);
135 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
136 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO).");
137 module_param_array(bdl_pos_adj, int, NULL, 0644);
138 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
139 module_param_array(probe_mask, int, NULL, 0444);
140 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
141 module_param_array(probe_only, int, NULL, 0444);
142 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
143 module_param_array(jackpoll_ms, int, NULL, 0444);
144 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
145 module_param(single_cmd, bint, 0444);
146 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
147 "(for debugging only).");
148 module_param(enable_msi, bint, 0444);
149 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
150 #ifdef CONFIG_SND_HDA_PATCH_LOADER
151 module_param_array(patch, charp, NULL, 0444);
152 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
153 #endif
154 #ifdef CONFIG_SND_HDA_INPUT_BEEP
155 module_param_array(beep_mode, bool, NULL, 0444);
156 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
157 "(0=off, 1=on) (default=1).");
158 #endif
159 module_param(dmic_detect, bool, 0444);
160 MODULE_PARM_DESC(dmic_detect, "Allow DSP driver selection (bypass this driver) "
161 "(0=off, 1=on) (default=1); "
162 "deprecated, use snd-intel-dspcfg.dsp_driver option instead");
163 module_param(ctl_dev_id, bool, 0444);
164 MODULE_PARM_DESC(ctl_dev_id, "Use control device identifier (based on codec address).");
165
166 #ifdef CONFIG_PM
167 static int param_set_xint(const char *val, const struct kernel_param *kp);
168 static const struct kernel_param_ops param_ops_xint = {
169 .set = param_set_xint,
170 .get = param_get_int,
171 };
172 #define param_check_xint param_check_int
173
174 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
175 module_param(power_save, xint, 0644);
176 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
177 "(in second, 0 = disable).");
178
179 static int pm_blacklist = -1;
180 module_param(pm_blacklist, bint, 0644);
181 MODULE_PARM_DESC(pm_blacklist, "Enable power-management denylist");
182
183 /* reset the HD-audio controller in power save mode.
184 * this may give more power-saving, but will take longer time to
185 * wake up.
186 */
187 static bool power_save_controller = 1;
188 module_param(power_save_controller, bool, 0644);
189 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
190 #else /* CONFIG_PM */
191 #define power_save 0
192 #define pm_blacklist 0
193 #define power_save_controller false
194 #endif /* CONFIG_PM */
195
196 static int align_buffer_size = -1;
197 module_param(align_buffer_size, bint, 0644);
198 MODULE_PARM_DESC(align_buffer_size,
199 "Force buffer and period sizes to be multiple of 128 bytes.");
200
201 #ifdef CONFIG_X86
202 static int hda_snoop = -1;
203 module_param_named(snoop, hda_snoop, bint, 0444);
204 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
205 #else
206 #define hda_snoop true
207 #endif
208
209
210 MODULE_LICENSE("GPL");
211 MODULE_DESCRIPTION("Intel HDA driver");
212
213 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
214 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
215 #define SUPPORT_VGA_SWITCHEROO
216 #endif
217 #endif
218
219
220 /*
221 */
222
223 /* driver types */
224 enum {
225 AZX_DRIVER_ICH,
226 AZX_DRIVER_PCH,
227 AZX_DRIVER_SCH,
228 AZX_DRIVER_SKL,
229 AZX_DRIVER_HDMI,
230 AZX_DRIVER_ATI,
231 AZX_DRIVER_ATIHDMI,
232 AZX_DRIVER_ATIHDMI_NS,
233 AZX_DRIVER_GFHDMI,
234 AZX_DRIVER_VIA,
235 AZX_DRIVER_SIS,
236 AZX_DRIVER_ULI,
237 AZX_DRIVER_NVIDIA,
238 AZX_DRIVER_TERA,
239 AZX_DRIVER_CTX,
240 AZX_DRIVER_CTHDA,
241 AZX_DRIVER_CMEDIA,
242 AZX_DRIVER_ZHAOXIN,
243 AZX_DRIVER_ZHAOXINHDMI,
244 AZX_DRIVER_LOONGSON,
245 AZX_DRIVER_GENERIC,
246 AZX_NUM_DRIVERS, /* keep this as last entry */
247 };
248
249 #define azx_get_snoop_type(chip) \
250 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
251 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
252
253 /* quirks for old Intel chipsets */
254 #define AZX_DCAPS_INTEL_ICH \
255 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
256
257 /* quirks for Intel PCH */
258 #define AZX_DCAPS_INTEL_PCH_BASE \
259 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
260 AZX_DCAPS_SNOOP_TYPE(SCH))
261
262 /* PCH up to IVB; no runtime PM; bind with i915 gfx */
263 #define AZX_DCAPS_INTEL_PCH_NOPM \
264 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
265
266 /* PCH for HSW/BDW; with runtime PM */
267 /* no i915 binding for this as HSW/BDW has another controller for HDMI */
268 #define AZX_DCAPS_INTEL_PCH \
269 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
270
271 /* HSW HDMI */
272 #define AZX_DCAPS_INTEL_HASWELL \
273 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
274 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
275 AZX_DCAPS_SNOOP_TYPE(SCH))
276
277 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
278 #define AZX_DCAPS_INTEL_BROADWELL \
279 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
280 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
281 AZX_DCAPS_SNOOP_TYPE(SCH))
282
283 #define AZX_DCAPS_INTEL_BAYTRAIL \
284 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
285
286 #define AZX_DCAPS_INTEL_BRASWELL \
287 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
288 AZX_DCAPS_I915_COMPONENT)
289
290 #define AZX_DCAPS_INTEL_SKYLAKE \
291 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
292 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
293
294 #define AZX_DCAPS_INTEL_BROXTON AZX_DCAPS_INTEL_SKYLAKE
295
296 #define AZX_DCAPS_INTEL_LNL \
297 (AZX_DCAPS_INTEL_SKYLAKE | AZX_DCAPS_PIO_COMMANDS)
298
299 /* quirks for ATI SB / AMD Hudson */
300 #define AZX_DCAPS_PRESET_ATI_SB \
301 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB |\
302 AZX_DCAPS_SNOOP_TYPE(ATI))
303
304 /* quirks for ATI/AMD HDMI */
305 #define AZX_DCAPS_PRESET_ATI_HDMI \
306 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB|\
307 AZX_DCAPS_NO_MSI64)
308
309 /* quirks for ATI HDMI with snoop off */
310 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
311 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
312
313 /* quirks for AMD SB */
314 #define AZX_DCAPS_PRESET_AMD_SB \
315 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_AMD_WORKAROUND |\
316 AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME |\
317 AZX_DCAPS_RETRY_PROBE)
318
319 /* quirks for Nvidia */
320 #define AZX_DCAPS_PRESET_NVIDIA \
321 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
322 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
323
324 #define AZX_DCAPS_PRESET_CTHDA \
325 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
326 AZX_DCAPS_NO_64BIT |\
327 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
328
329 /*
330 * vga_switcheroo support
331 */
332 #ifdef SUPPORT_VGA_SWITCHEROO
333 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
334 #define needs_eld_notify_link(chip) ((chip)->bus.keep_power)
335 #else
336 #define use_vga_switcheroo(chip) 0
337 #define needs_eld_notify_link(chip) false
338 #endif
339
340 static const char * const driver_short_names[] = {
341 [AZX_DRIVER_ICH] = "HDA Intel",
342 [AZX_DRIVER_PCH] = "HDA Intel PCH",
343 [AZX_DRIVER_SCH] = "HDA Intel MID",
344 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
345 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
346 [AZX_DRIVER_ATI] = "HDA ATI SB",
347 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
348 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
349 [AZX_DRIVER_GFHDMI] = "HDA GF HDMI",
350 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
351 [AZX_DRIVER_SIS] = "HDA SIS966",
352 [AZX_DRIVER_ULI] = "HDA ULI M5461",
353 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
354 [AZX_DRIVER_TERA] = "HDA Teradici",
355 [AZX_DRIVER_CTX] = "HDA Creative",
356 [AZX_DRIVER_CTHDA] = "HDA Creative",
357 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
358 [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin",
359 [AZX_DRIVER_ZHAOXINHDMI] = "HDA Zhaoxin HDMI",
360 [AZX_DRIVER_LOONGSON] = "HDA Loongson",
361 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
362 };
363
364 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
365 static void set_default_power_save(struct azx *chip);
366
367 /*
368 * initialize the PCI registers
369 */
370 /* update bits in a PCI register byte */
update_pci_byte(struct pci_dev * pci,unsigned int reg,unsigned char mask,unsigned char val)371 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
372 unsigned char mask, unsigned char val)
373 {
374 unsigned char data;
375
376 pci_read_config_byte(pci, reg, &data);
377 data &= ~mask;
378 data |= (val & mask);
379 pci_write_config_byte(pci, reg, data);
380 }
381
azx_init_pci(struct azx * chip)382 static void azx_init_pci(struct azx *chip)
383 {
384 int snoop_type = azx_get_snoop_type(chip);
385
386 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
387 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
388 * Ensuring these bits are 0 clears playback static on some HD Audio
389 * codecs.
390 * The PCI register TCSEL is defined in the Intel manuals.
391 */
392 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
393 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
394 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
395 }
396
397 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
398 * we need to enable snoop.
399 */
400 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
401 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
402 azx_snoop(chip));
403 update_pci_byte(chip->pci,
404 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
405 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
406 }
407
408 /* For NVIDIA HDA, enable snoop */
409 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
410 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
411 azx_snoop(chip));
412 update_pci_byte(chip->pci,
413 NVIDIA_HDA_TRANSREG_ADDR,
414 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
415 update_pci_byte(chip->pci,
416 NVIDIA_HDA_ISTRM_COH,
417 0x01, NVIDIA_HDA_ENABLE_COHBIT);
418 update_pci_byte(chip->pci,
419 NVIDIA_HDA_OSTRM_COH,
420 0x01, NVIDIA_HDA_ENABLE_COHBIT);
421 }
422
423 /* Enable SCH/PCH snoop if needed */
424 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
425 unsigned short snoop;
426 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
427 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
428 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
429 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
430 if (!azx_snoop(chip))
431 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
432 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
433 pci_read_config_word(chip->pci,
434 INTEL_SCH_HDA_DEVC, &snoop);
435 }
436 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
437 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
438 "Disabled" : "Enabled");
439 }
440 }
441
442 /*
443 * In BXT-P A0, HD-Audio DMA requests is later than expected,
444 * and makes an audio stream sensitive to system latencies when
445 * 24/32 bits are playing.
446 * Adjusting threshold of DMA fifo to force the DMA request
447 * sooner to improve latency tolerance at the expense of power.
448 */
bxt_reduce_dma_latency(struct azx * chip)449 static void bxt_reduce_dma_latency(struct azx *chip)
450 {
451 u32 val;
452
453 val = azx_readl(chip, VS_EM4L);
454 val &= (0x3 << 20);
455 azx_writel(chip, VS_EM4L, val);
456 }
457
458 /*
459 * ML_LCAP bits:
460 * bit 0: 6 MHz Supported
461 * bit 1: 12 MHz Supported
462 * bit 2: 24 MHz Supported
463 * bit 3: 48 MHz Supported
464 * bit 4: 96 MHz Supported
465 * bit 5: 192 MHz Supported
466 */
intel_get_lctl_scf(struct azx * chip)467 static int intel_get_lctl_scf(struct azx *chip)
468 {
469 struct hdac_bus *bus = azx_bus(chip);
470 static const int preferred_bits[] = { 2, 3, 1, 4, 5 };
471 u32 val, t;
472 int i;
473
474 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
475
476 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
477 t = preferred_bits[i];
478 if (val & (1 << t))
479 return t;
480 }
481
482 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
483 return 0;
484 }
485
intel_ml_lctl_set_power(struct azx * chip,int state)486 static int intel_ml_lctl_set_power(struct azx *chip, int state)
487 {
488 struct hdac_bus *bus = azx_bus(chip);
489 u32 val;
490 int timeout;
491
492 /*
493 * Changes to LCTL.SCF are only needed for the first multi-link dealing
494 * with external codecs
495 */
496 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
497 val &= ~AZX_ML_LCTL_SPA;
498 val |= state << AZX_ML_LCTL_SPA_SHIFT;
499 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
500 /* wait for CPA */
501 timeout = 50;
502 while (timeout) {
503 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
504 AZX_ML_LCTL_CPA) == (state << AZX_ML_LCTL_CPA_SHIFT))
505 return 0;
506 timeout--;
507 udelay(10);
508 }
509
510 return -1;
511 }
512
intel_init_lctl(struct azx * chip)513 static void intel_init_lctl(struct azx *chip)
514 {
515 struct hdac_bus *bus = azx_bus(chip);
516 u32 val;
517 int ret;
518
519 /* 0. check lctl register value is correct or not */
520 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
521 /* only perform additional configurations if the SCF is initially based on 6MHz */
522 if ((val & AZX_ML_LCTL_SCF) != 0)
523 return;
524
525 /*
526 * Before operating on SPA, CPA must match SPA.
527 * Any deviation may result in undefined behavior.
528 */
529 if (((val & AZX_ML_LCTL_SPA) >> AZX_ML_LCTL_SPA_SHIFT) !=
530 ((val & AZX_ML_LCTL_CPA) >> AZX_ML_LCTL_CPA_SHIFT))
531 return;
532
533 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
534 ret = intel_ml_lctl_set_power(chip, 0);
535 udelay(100);
536 if (ret)
537 goto set_spa;
538
539 /* 2. update SCF to select an audio clock different from 6MHz */
540 val &= ~AZX_ML_LCTL_SCF;
541 val |= intel_get_lctl_scf(chip);
542 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
543
544 set_spa:
545 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
546 intel_ml_lctl_set_power(chip, 1);
547 udelay(100);
548 }
549
hda_intel_init_chip(struct azx * chip,bool full_reset)550 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
551 {
552 struct hdac_bus *bus = azx_bus(chip);
553 struct pci_dev *pci = chip->pci;
554 u32 val;
555
556 snd_hdac_set_codec_wakeup(bus, true);
557 if (chip->driver_type == AZX_DRIVER_SKL) {
558 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
559 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
560 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
561 }
562 azx_init_chip(chip, full_reset);
563 if (chip->driver_type == AZX_DRIVER_SKL) {
564 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
565 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
566 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
567 }
568
569 snd_hdac_set_codec_wakeup(bus, false);
570
571 /* reduce dma latency to avoid noise */
572 if (HDA_CONTROLLER_IS_APL(pci))
573 bxt_reduce_dma_latency(chip);
574
575 if (bus->mlcap != NULL)
576 intel_init_lctl(chip);
577 }
578
579 /* calculate runtime delay from LPIB */
azx_get_delay_from_lpib(struct azx * chip,struct azx_dev * azx_dev,unsigned int pos)580 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
581 unsigned int pos)
582 {
583 struct snd_pcm_substream *substream = azx_dev->core.substream;
584 int stream = substream->stream;
585 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
586 int delay;
587
588 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
589 delay = pos - lpib_pos;
590 else
591 delay = lpib_pos - pos;
592 if (delay < 0) {
593 if (delay >= azx_dev->core.delay_negative_threshold)
594 delay = 0;
595 else
596 delay += azx_dev->core.bufsize;
597 }
598
599 if (delay >= azx_dev->core.period_bytes) {
600 dev_info(chip->card->dev,
601 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
602 delay, azx_dev->core.period_bytes);
603 delay = 0;
604 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
605 chip->get_delay[stream] = NULL;
606 }
607
608 return bytes_to_frames(substream->runtime, delay);
609 }
610
611 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
612
613 /* called from IRQ */
azx_position_check(struct azx * chip,struct azx_dev * azx_dev)614 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
615 {
616 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
617 int ok;
618
619 ok = azx_position_ok(chip, azx_dev);
620 if (ok == 1) {
621 azx_dev->irq_pending = 0;
622 return ok;
623 } else if (ok == 0) {
624 /* bogus IRQ, process it later */
625 azx_dev->irq_pending = 1;
626 schedule_work(&hda->irq_pending_work);
627 }
628 return 0;
629 }
630
631 #define display_power(chip, enable) \
632 snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)
633
634 /*
635 * Check whether the current DMA position is acceptable for updating
636 * periods. Returns non-zero if it's OK.
637 *
638 * Many HD-audio controllers appear pretty inaccurate about
639 * the update-IRQ timing. The IRQ is issued before actually the
640 * data is processed. So, we need to process it afterwords in a
641 * workqueue.
642 *
643 * Returns 1 if OK to proceed, 0 for delay handling, -1 for skipping update
644 */
azx_position_ok(struct azx * chip,struct azx_dev * azx_dev)645 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
646 {
647 struct snd_pcm_substream *substream = azx_dev->core.substream;
648 struct snd_pcm_runtime *runtime = substream->runtime;
649 int stream = substream->stream;
650 u32 wallclk;
651 unsigned int pos;
652 snd_pcm_uframes_t hwptr, target;
653
654 /*
655 * The value of the WALLCLK register is always 0
656 * on the Loongson controller, so we return directly.
657 */
658 if (chip->driver_type == AZX_DRIVER_LOONGSON)
659 return 1;
660
661 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
662 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
663 return -1; /* bogus (too early) interrupt */
664
665 if (chip->get_position[stream])
666 pos = chip->get_position[stream](chip, azx_dev);
667 else { /* use the position buffer as default */
668 pos = azx_get_pos_posbuf(chip, azx_dev);
669 if (!pos || pos == (u32)-1) {
670 dev_info(chip->card->dev,
671 "Invalid position buffer, using LPIB read method instead.\n");
672 chip->get_position[stream] = azx_get_pos_lpib;
673 if (chip->get_position[0] == azx_get_pos_lpib &&
674 chip->get_position[1] == azx_get_pos_lpib)
675 azx_bus(chip)->use_posbuf = false;
676 pos = azx_get_pos_lpib(chip, azx_dev);
677 chip->get_delay[stream] = NULL;
678 } else {
679 chip->get_position[stream] = azx_get_pos_posbuf;
680 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
681 chip->get_delay[stream] = azx_get_delay_from_lpib;
682 }
683 }
684
685 if (pos >= azx_dev->core.bufsize)
686 pos = 0;
687
688 if (WARN_ONCE(!azx_dev->core.period_bytes,
689 "hda-intel: zero azx_dev->period_bytes"))
690 return -1; /* this shouldn't happen! */
691 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
692 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
693 /* NG - it's below the first next period boundary */
694 return chip->bdl_pos_adj ? 0 : -1;
695 azx_dev->core.start_wallclk += wallclk;
696
697 if (azx_dev->core.no_period_wakeup)
698 return 1; /* OK, no need to check period boundary */
699
700 if (runtime->hw_ptr_base != runtime->hw_ptr_interrupt)
701 return 1; /* OK, already in hwptr updating process */
702
703 /* check whether the period gets really elapsed */
704 pos = bytes_to_frames(runtime, pos);
705 hwptr = runtime->hw_ptr_base + pos;
706 if (hwptr < runtime->status->hw_ptr)
707 hwptr += runtime->buffer_size;
708 target = runtime->hw_ptr_interrupt + runtime->period_size;
709 if (hwptr < target) {
710 /* too early wakeup, process it later */
711 return chip->bdl_pos_adj ? 0 : -1;
712 }
713
714 return 1; /* OK, it's fine */
715 }
716
717 /*
718 * The work for pending PCM period updates.
719 */
azx_irq_pending_work(struct work_struct * work)720 static void azx_irq_pending_work(struct work_struct *work)
721 {
722 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
723 struct azx *chip = &hda->chip;
724 struct hdac_bus *bus = azx_bus(chip);
725 struct hdac_stream *s;
726 int pending, ok;
727
728 if (!hda->irq_pending_warned) {
729 dev_info(chip->card->dev,
730 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
731 chip->card->number);
732 hda->irq_pending_warned = 1;
733 }
734
735 for (;;) {
736 pending = 0;
737 spin_lock_irq(&bus->reg_lock);
738 list_for_each_entry(s, &bus->stream_list, list) {
739 struct azx_dev *azx_dev = stream_to_azx_dev(s);
740 if (!azx_dev->irq_pending ||
741 !s->substream ||
742 !s->running)
743 continue;
744 ok = azx_position_ok(chip, azx_dev);
745 if (ok > 0) {
746 azx_dev->irq_pending = 0;
747 spin_unlock(&bus->reg_lock);
748 snd_pcm_period_elapsed(s->substream);
749 spin_lock(&bus->reg_lock);
750 } else if (ok < 0) {
751 pending = 0; /* too early */
752 } else
753 pending++;
754 }
755 spin_unlock_irq(&bus->reg_lock);
756 if (!pending)
757 return;
758 msleep(1);
759 }
760 }
761
762 /* clear irq_pending flags and assure no on-going workq */
azx_clear_irq_pending(struct azx * chip)763 static void azx_clear_irq_pending(struct azx *chip)
764 {
765 struct hdac_bus *bus = azx_bus(chip);
766 struct hdac_stream *s;
767
768 spin_lock_irq(&bus->reg_lock);
769 list_for_each_entry(s, &bus->stream_list, list) {
770 struct azx_dev *azx_dev = stream_to_azx_dev(s);
771 azx_dev->irq_pending = 0;
772 }
773 spin_unlock_irq(&bus->reg_lock);
774 }
775
azx_acquire_irq(struct azx * chip,int do_disconnect)776 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
777 {
778 struct hdac_bus *bus = azx_bus(chip);
779 int ret;
780
781 if (!chip->msi || pci_alloc_irq_vectors(chip->pci, 1, 1, PCI_IRQ_MSI) < 0) {
782 ret = pci_alloc_irq_vectors(chip->pci, 1, 1, PCI_IRQ_INTX);
783 if (ret < 0)
784 return ret;
785 chip->msi = 0;
786 }
787
788 if (request_irq(chip->pci->irq, azx_interrupt,
789 chip->msi ? 0 : IRQF_SHARED,
790 chip->card->irq_descr, chip)) {
791 dev_err(chip->card->dev,
792 "unable to grab IRQ %d, disabling device\n",
793 chip->pci->irq);
794 if (do_disconnect)
795 snd_card_disconnect(chip->card);
796 return -1;
797 }
798 bus->irq = chip->pci->irq;
799 chip->card->sync_irq = bus->irq;
800 return 0;
801 }
802
803 /* get the current DMA position with correction on VIA chips */
azx_via_get_position(struct azx * chip,struct azx_dev * azx_dev)804 static unsigned int azx_via_get_position(struct azx *chip,
805 struct azx_dev *azx_dev)
806 {
807 unsigned int link_pos, mini_pos, bound_pos;
808 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
809 unsigned int fifo_size;
810
811 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
812 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
813 /* Playback, no problem using link position */
814 return link_pos;
815 }
816
817 /* Capture */
818 /* For new chipset,
819 * use mod to get the DMA position just like old chipset
820 */
821 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
822 mod_dma_pos %= azx_dev->core.period_bytes;
823
824 fifo_size = azx_stream(azx_dev)->fifo_size;
825
826 if (azx_dev->insufficient) {
827 /* Link position never gather than FIFO size */
828 if (link_pos <= fifo_size)
829 return 0;
830
831 azx_dev->insufficient = 0;
832 }
833
834 if (link_pos <= fifo_size)
835 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
836 else
837 mini_pos = link_pos - fifo_size;
838
839 /* Find nearest previous boudary */
840 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
841 mod_link_pos = link_pos % azx_dev->core.period_bytes;
842 if (mod_link_pos >= fifo_size)
843 bound_pos = link_pos - mod_link_pos;
844 else if (mod_dma_pos >= mod_mini_pos)
845 bound_pos = mini_pos - mod_mini_pos;
846 else {
847 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
848 if (bound_pos >= azx_dev->core.bufsize)
849 bound_pos = 0;
850 }
851
852 /* Calculate real DMA position we want */
853 return bound_pos + mod_dma_pos;
854 }
855
856 #define AMD_FIFO_SIZE 32
857
858 /* get the current DMA position with FIFO size correction */
azx_get_pos_fifo(struct azx * chip,struct azx_dev * azx_dev)859 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev)
860 {
861 struct snd_pcm_substream *substream = azx_dev->core.substream;
862 struct snd_pcm_runtime *runtime = substream->runtime;
863 unsigned int pos, delay;
864
865 pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
866 if (!runtime)
867 return pos;
868
869 runtime->delay = AMD_FIFO_SIZE;
870 delay = frames_to_bytes(runtime, AMD_FIFO_SIZE);
871 if (azx_dev->insufficient) {
872 if (pos < delay) {
873 delay = pos;
874 runtime->delay = bytes_to_frames(runtime, pos);
875 } else {
876 azx_dev->insufficient = 0;
877 }
878 }
879
880 /* correct the DMA position for capture stream */
881 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
882 if (pos < delay)
883 pos += azx_dev->core.bufsize;
884 pos -= delay;
885 }
886
887 return pos;
888 }
889
azx_get_delay_from_fifo(struct azx * chip,struct azx_dev * azx_dev,unsigned int pos)890 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev,
891 unsigned int pos)
892 {
893 struct snd_pcm_substream *substream = azx_dev->core.substream;
894
895 /* just read back the calculated value in the above */
896 return substream->runtime->delay;
897 }
898
__azx_shutdown_chip(struct azx * chip,bool skip_link_reset)899 static void __azx_shutdown_chip(struct azx *chip, bool skip_link_reset)
900 {
901 azx_stop_chip(chip);
902 if (!skip_link_reset)
903 azx_enter_link_reset(chip);
904 azx_clear_irq_pending(chip);
905 display_power(chip, false);
906 }
907
908 static DEFINE_MUTEX(card_list_lock);
909 static LIST_HEAD(card_list);
910
azx_shutdown_chip(struct azx * chip)911 static void azx_shutdown_chip(struct azx *chip)
912 {
913 __azx_shutdown_chip(chip, false);
914 }
915
azx_add_card_list(struct azx * chip)916 static void azx_add_card_list(struct azx *chip)
917 {
918 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
919 mutex_lock(&card_list_lock);
920 list_add(&hda->list, &card_list);
921 mutex_unlock(&card_list_lock);
922 }
923
azx_del_card_list(struct azx * chip)924 static void azx_del_card_list(struct azx *chip)
925 {
926 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
927 mutex_lock(&card_list_lock);
928 list_del_init(&hda->list);
929 mutex_unlock(&card_list_lock);
930 }
931
932 /* trigger power-save check at writing parameter */
param_set_xint(const char * val,const struct kernel_param * kp)933 static int __maybe_unused param_set_xint(const char *val, const struct kernel_param *kp)
934 {
935 struct hda_intel *hda;
936 struct azx *chip;
937 int prev = power_save;
938 int ret = param_set_int(val, kp);
939
940 if (ret || prev == power_save)
941 return ret;
942
943 if (pm_blacklist > 0)
944 return 0;
945
946 mutex_lock(&card_list_lock);
947 list_for_each_entry(hda, &card_list, list) {
948 chip = &hda->chip;
949 if (!hda->probe_continued || chip->disabled ||
950 hda->runtime_pm_disabled)
951 continue;
952 snd_hda_set_power_save(&chip->bus, power_save * 1000);
953 }
954 mutex_unlock(&card_list_lock);
955 return 0;
956 }
957
958 /*
959 * power management
960 */
azx_is_pm_ready(struct snd_card * card)961 static bool azx_is_pm_ready(struct snd_card *card)
962 {
963 struct azx *chip;
964 struct hda_intel *hda;
965
966 if (!card)
967 return false;
968 chip = card->private_data;
969 hda = container_of(chip, struct hda_intel, chip);
970 if (chip->disabled || hda->init_failed || !chip->running)
971 return false;
972 return true;
973 }
974
__azx_runtime_resume(struct azx * chip)975 static void __azx_runtime_resume(struct azx *chip)
976 {
977 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
978 struct hdac_bus *bus = azx_bus(chip);
979 struct hda_codec *codec;
980 int status;
981
982 display_power(chip, true);
983 if (hda->need_i915_power)
984 snd_hdac_i915_set_bclk(bus);
985
986 /* Read STATESTS before controller reset */
987 status = azx_readw(chip, STATESTS);
988
989 azx_init_pci(chip);
990 hda_intel_init_chip(chip, true);
991
992 /* Avoid codec resume if runtime resume is for system suspend */
993 if (!chip->pm_prepared) {
994 list_for_each_codec(codec, &chip->bus) {
995 if (codec->relaxed_resume)
996 continue;
997
998 if (codec->forced_resume || (status & (1 << codec->addr)))
999 pm_request_resume(hda_codec_dev(codec));
1000 }
1001 }
1002
1003 /* power down again for link-controlled chips */
1004 if (!hda->need_i915_power)
1005 display_power(chip, false);
1006 }
1007
azx_prepare(struct device * dev)1008 static int azx_prepare(struct device *dev)
1009 {
1010 struct snd_card *card = dev_get_drvdata(dev);
1011 struct azx *chip;
1012
1013 if (!azx_is_pm_ready(card))
1014 return 0;
1015
1016 chip = card->private_data;
1017 chip->pm_prepared = 1;
1018 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1019
1020 flush_work(&azx_bus(chip)->unsol_work);
1021
1022 /* HDA controller always requires different WAKEEN for runtime suspend
1023 * and system suspend, so don't use direct-complete here.
1024 */
1025 return 0;
1026 }
1027
azx_complete(struct device * dev)1028 static void azx_complete(struct device *dev)
1029 {
1030 struct snd_card *card = dev_get_drvdata(dev);
1031 struct azx *chip;
1032
1033 if (!azx_is_pm_ready(card))
1034 return;
1035
1036 chip = card->private_data;
1037 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1038 chip->pm_prepared = 0;
1039 }
1040
azx_suspend(struct device * dev)1041 static int azx_suspend(struct device *dev)
1042 {
1043 struct snd_card *card = dev_get_drvdata(dev);
1044 struct azx *chip;
1045
1046 if (!azx_is_pm_ready(card))
1047 return 0;
1048
1049 chip = card->private_data;
1050 azx_shutdown_chip(chip);
1051
1052 trace_azx_suspend(chip);
1053 return 0;
1054 }
1055
azx_resume(struct device * dev)1056 static int azx_resume(struct device *dev)
1057 {
1058 struct snd_card *card = dev_get_drvdata(dev);
1059 struct azx *chip;
1060
1061 if (!azx_is_pm_ready(card))
1062 return 0;
1063
1064 chip = card->private_data;
1065
1066 __azx_runtime_resume(chip);
1067
1068 trace_azx_resume(chip);
1069 return 0;
1070 }
1071
1072 /* put codec down to D3 at hibernation for Intel SKL+;
1073 * otherwise BIOS may still access the codec and screw up the driver
1074 */
azx_freeze_noirq(struct device * dev)1075 static int azx_freeze_noirq(struct device *dev)
1076 {
1077 struct snd_card *card = dev_get_drvdata(dev);
1078 struct azx *chip = card->private_data;
1079 struct pci_dev *pci = to_pci_dev(dev);
1080
1081 if (!azx_is_pm_ready(card))
1082 return 0;
1083 if (chip->driver_type == AZX_DRIVER_SKL)
1084 pci_set_power_state(pci, PCI_D3hot);
1085
1086 return 0;
1087 }
1088
azx_thaw_noirq(struct device * dev)1089 static int azx_thaw_noirq(struct device *dev)
1090 {
1091 struct snd_card *card = dev_get_drvdata(dev);
1092 struct azx *chip = card->private_data;
1093 struct pci_dev *pci = to_pci_dev(dev);
1094
1095 if (!azx_is_pm_ready(card))
1096 return 0;
1097 if (chip->driver_type == AZX_DRIVER_SKL)
1098 pci_set_power_state(pci, PCI_D0);
1099
1100 return 0;
1101 }
1102
azx_runtime_suspend(struct device * dev)1103 static int azx_runtime_suspend(struct device *dev)
1104 {
1105 struct snd_card *card = dev_get_drvdata(dev);
1106 struct azx *chip;
1107
1108 if (!azx_is_pm_ready(card))
1109 return 0;
1110 chip = card->private_data;
1111
1112 /* enable controller wake up event */
1113 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | STATESTS_INT_MASK);
1114
1115 azx_shutdown_chip(chip);
1116 trace_azx_runtime_suspend(chip);
1117 return 0;
1118 }
1119
azx_runtime_resume(struct device * dev)1120 static int azx_runtime_resume(struct device *dev)
1121 {
1122 struct snd_card *card = dev_get_drvdata(dev);
1123 struct azx *chip;
1124
1125 if (!azx_is_pm_ready(card))
1126 return 0;
1127 chip = card->private_data;
1128 __azx_runtime_resume(chip);
1129
1130 /* disable controller Wake Up event*/
1131 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & ~STATESTS_INT_MASK);
1132
1133 trace_azx_runtime_resume(chip);
1134 return 0;
1135 }
1136
azx_runtime_idle(struct device * dev)1137 static int azx_runtime_idle(struct device *dev)
1138 {
1139 struct snd_card *card = dev_get_drvdata(dev);
1140 struct azx *chip;
1141 struct hda_intel *hda;
1142
1143 if (!card)
1144 return 0;
1145
1146 chip = card->private_data;
1147 hda = container_of(chip, struct hda_intel, chip);
1148 if (chip->disabled || hda->init_failed)
1149 return 0;
1150
1151 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1152 azx_bus(chip)->codec_powered || !chip->running)
1153 return -EBUSY;
1154
1155 /* ELD notification gets broken when HD-audio bus is off */
1156 if (needs_eld_notify_link(chip))
1157 return -EBUSY;
1158
1159 return 0;
1160 }
1161
1162 static const struct dev_pm_ops azx_pm = {
1163 SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1164 .prepare = pm_sleep_ptr(azx_prepare),
1165 .complete = pm_sleep_ptr(azx_complete),
1166 .freeze_noirq = pm_sleep_ptr(azx_freeze_noirq),
1167 .thaw_noirq = pm_sleep_ptr(azx_thaw_noirq),
1168 RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1169 };
1170
1171
1172 static int azx_probe_continue(struct azx *chip);
1173
1174 #ifdef SUPPORT_VGA_SWITCHEROO
1175 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1176
azx_vs_set_state(struct pci_dev * pci,enum vga_switcheroo_state state)1177 static void azx_vs_set_state(struct pci_dev *pci,
1178 enum vga_switcheroo_state state)
1179 {
1180 struct snd_card *card = pci_get_drvdata(pci);
1181 struct azx *chip = card->private_data;
1182 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1183 struct hda_codec *codec;
1184 bool disabled;
1185
1186 wait_for_completion(&hda->probe_wait);
1187 if (hda->init_failed)
1188 return;
1189
1190 disabled = (state == VGA_SWITCHEROO_OFF);
1191 if (chip->disabled == disabled)
1192 return;
1193
1194 if (!hda->probe_continued) {
1195 chip->disabled = disabled;
1196 if (!disabled) {
1197 dev_info(chip->card->dev,
1198 "Start delayed initialization\n");
1199 if (azx_probe_continue(chip) < 0)
1200 dev_err(chip->card->dev, "initialization error\n");
1201 }
1202 } else {
1203 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1204 disabled ? "Disabling" : "Enabling");
1205 if (disabled) {
1206 list_for_each_codec(codec, &chip->bus) {
1207 pm_runtime_suspend(hda_codec_dev(codec));
1208 pm_runtime_disable(hda_codec_dev(codec));
1209 }
1210 pm_runtime_suspend(card->dev);
1211 pm_runtime_disable(card->dev);
1212 /* when we get suspended by vga_switcheroo we end up in D3cold,
1213 * however we have no ACPI handle, so pci/acpi can't put us there,
1214 * put ourselves there */
1215 pci->current_state = PCI_D3cold;
1216 chip->disabled = true;
1217 if (snd_hda_lock_devices(&chip->bus))
1218 dev_warn(chip->card->dev,
1219 "Cannot lock devices!\n");
1220 } else {
1221 snd_hda_unlock_devices(&chip->bus);
1222 chip->disabled = false;
1223 pm_runtime_enable(card->dev);
1224 list_for_each_codec(codec, &chip->bus) {
1225 pm_runtime_enable(hda_codec_dev(codec));
1226 pm_runtime_resume(hda_codec_dev(codec));
1227 }
1228 }
1229 }
1230 }
1231
azx_vs_can_switch(struct pci_dev * pci)1232 static bool azx_vs_can_switch(struct pci_dev *pci)
1233 {
1234 struct snd_card *card = pci_get_drvdata(pci);
1235 struct azx *chip = card->private_data;
1236 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1237
1238 wait_for_completion(&hda->probe_wait);
1239 if (hda->init_failed)
1240 return false;
1241 if (chip->disabled || !hda->probe_continued)
1242 return true;
1243 if (snd_hda_lock_devices(&chip->bus))
1244 return false;
1245 snd_hda_unlock_devices(&chip->bus);
1246 return true;
1247 }
1248
1249 /*
1250 * The discrete GPU cannot power down unless the HDA controller runtime
1251 * suspends, so activate runtime PM on codecs even if power_save == 0.
1252 */
setup_vga_switcheroo_runtime_pm(struct azx * chip)1253 static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1254 {
1255 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1256 struct hda_codec *codec;
1257
1258 if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) {
1259 list_for_each_codec(codec, &chip->bus)
1260 codec->auto_runtime_pm = 1;
1261 /* reset the power save setup */
1262 if (chip->running)
1263 set_default_power_save(chip);
1264 }
1265 }
1266
azx_vs_gpu_bound(struct pci_dev * pci,enum vga_switcheroo_client_id client_id)1267 static void azx_vs_gpu_bound(struct pci_dev *pci,
1268 enum vga_switcheroo_client_id client_id)
1269 {
1270 struct snd_card *card = pci_get_drvdata(pci);
1271 struct azx *chip = card->private_data;
1272
1273 if (client_id == VGA_SWITCHEROO_DIS)
1274 chip->bus.keep_power = 0;
1275 setup_vga_switcheroo_runtime_pm(chip);
1276 }
1277
init_vga_switcheroo(struct azx * chip)1278 static void init_vga_switcheroo(struct azx *chip)
1279 {
1280 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1281 struct pci_dev *p = get_bound_vga(chip->pci);
1282 struct pci_dev *parent;
1283 if (p) {
1284 dev_info(chip->card->dev,
1285 "Handle vga_switcheroo audio client\n");
1286 hda->use_vga_switcheroo = 1;
1287
1288 /* cleared in either gpu_bound op or codec probe, or when its
1289 * upstream port has _PR3 (i.e. dGPU).
1290 */
1291 parent = pci_upstream_bridge(p);
1292 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1;
1293 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
1294 pci_dev_put(p);
1295 }
1296 }
1297
1298 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1299 .set_gpu_state = azx_vs_set_state,
1300 .can_switch = azx_vs_can_switch,
1301 .gpu_bound = azx_vs_gpu_bound,
1302 };
1303
register_vga_switcheroo(struct azx * chip)1304 static int register_vga_switcheroo(struct azx *chip)
1305 {
1306 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1307 struct pci_dev *p;
1308 int err;
1309
1310 if (!hda->use_vga_switcheroo)
1311 return 0;
1312
1313 p = get_bound_vga(chip->pci);
1314 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1315 pci_dev_put(p);
1316
1317 if (err < 0)
1318 return err;
1319 hda->vga_switcheroo_registered = 1;
1320
1321 return 0;
1322 }
1323 #else
1324 #define init_vga_switcheroo(chip) /* NOP */
1325 #define register_vga_switcheroo(chip) 0
1326 #define check_hdmi_disabled(pci) false
1327 #define setup_vga_switcheroo_runtime_pm(chip) /* NOP */
1328 #endif /* SUPPORT_VGA_SWITCHER */
1329
1330 /*
1331 * destructor
1332 */
azx_free(struct azx * chip)1333 static void azx_free(struct azx *chip)
1334 {
1335 struct pci_dev *pci = chip->pci;
1336 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1337 struct hdac_bus *bus = azx_bus(chip);
1338
1339 if (hda->freed)
1340 return;
1341
1342 if (azx_has_pm_runtime(chip) && chip->running) {
1343 pm_runtime_get_noresume(&pci->dev);
1344 pm_runtime_forbid(&pci->dev);
1345 pm_runtime_dont_use_autosuspend(&pci->dev);
1346 }
1347
1348 chip->running = 0;
1349
1350 azx_del_card_list(chip);
1351
1352 hda->init_failed = 1; /* to be sure */
1353 complete_all(&hda->probe_wait);
1354
1355 if (use_vga_switcheroo(hda)) {
1356 if (chip->disabled && hda->probe_continued)
1357 snd_hda_unlock_devices(&chip->bus);
1358 if (hda->vga_switcheroo_registered) {
1359 vga_switcheroo_unregister_client(chip->pci);
1360
1361 /* Some GPUs don't have sound, and azx_first_init fails,
1362 * leaving the device probed but non-functional. As long
1363 * as it's probed, the PCI subsystem keeps its runtime
1364 * PM status as active. Force it to suspended (as we
1365 * actually stop the chip) to allow GPU to suspend via
1366 * vga_switcheroo, and print a warning.
1367 */
1368 dev_warn(&pci->dev, "GPU sound probed, but not operational: please add a quirk to driver_denylist\n");
1369 pm_runtime_disable(&pci->dev);
1370 pm_runtime_set_suspended(&pci->dev);
1371 pm_runtime_enable(&pci->dev);
1372 }
1373 }
1374
1375 if (bus->chip_init) {
1376 azx_clear_irq_pending(chip);
1377 azx_stop_all_streams(chip);
1378 azx_stop_chip(chip);
1379 }
1380
1381 if (bus->irq >= 0)
1382 free_irq(bus->irq, (void*)chip);
1383
1384 azx_free_stream_pages(chip);
1385 azx_free_streams(chip);
1386 snd_hdac_bus_exit(bus);
1387
1388 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1389 release_firmware(chip->fw);
1390 #endif
1391 display_power(chip, false);
1392
1393 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
1394 snd_hdac_i915_exit(bus);
1395
1396 hda->freed = 1;
1397 }
1398
azx_dev_disconnect(struct snd_device * device)1399 static int azx_dev_disconnect(struct snd_device *device)
1400 {
1401 struct azx *chip = device->device_data;
1402 struct hdac_bus *bus = azx_bus(chip);
1403
1404 chip->bus.shutdown = 1;
1405 cancel_work_sync(&bus->unsol_work);
1406
1407 return 0;
1408 }
1409
azx_dev_free(struct snd_device * device)1410 static int azx_dev_free(struct snd_device *device)
1411 {
1412 azx_free(device->device_data);
1413 return 0;
1414 }
1415
1416 #ifdef SUPPORT_VGA_SWITCHEROO
1417 #ifdef CONFIG_ACPI
1418 /* ATPX is in the integrated GPU's namespace */
atpx_present(void)1419 static bool atpx_present(void)
1420 {
1421 struct pci_dev *pdev = NULL;
1422 acpi_handle dhandle, atpx_handle;
1423 acpi_status status;
1424
1425 while ((pdev = pci_get_base_class(PCI_BASE_CLASS_DISPLAY, pdev))) {
1426 if ((pdev->class != PCI_CLASS_DISPLAY_VGA << 8) &&
1427 (pdev->class != PCI_CLASS_DISPLAY_OTHER << 8))
1428 continue;
1429
1430 dhandle = ACPI_HANDLE(&pdev->dev);
1431 if (dhandle) {
1432 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
1433 if (ACPI_SUCCESS(status)) {
1434 pci_dev_put(pdev);
1435 return true;
1436 }
1437 }
1438 }
1439 return false;
1440 }
1441 #else
atpx_present(void)1442 static bool atpx_present(void)
1443 {
1444 return false;
1445 }
1446 #endif
1447
1448 /*
1449 * Check of disabled HDMI controller by vga_switcheroo
1450 */
get_bound_vga(struct pci_dev * pci)1451 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1452 {
1453 struct pci_dev *p;
1454
1455 /* check only discrete GPU */
1456 switch (pci->vendor) {
1457 case PCI_VENDOR_ID_ATI:
1458 case PCI_VENDOR_ID_AMD:
1459 if (pci->devfn == 1) {
1460 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1461 pci->bus->number, 0);
1462 if (p) {
1463 /* ATPX is in the integrated GPU's ACPI namespace
1464 * rather than the dGPU's namespace. However,
1465 * the dGPU is the one who is involved in
1466 * vgaswitcheroo.
1467 */
1468 if (((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) &&
1469 (atpx_present() || apple_gmux_detect(NULL, NULL)))
1470 return p;
1471 pci_dev_put(p);
1472 }
1473 }
1474 break;
1475 case PCI_VENDOR_ID_NVIDIA:
1476 if (pci->devfn == 1) {
1477 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1478 pci->bus->number, 0);
1479 if (p) {
1480 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
1481 return p;
1482 pci_dev_put(p);
1483 }
1484 }
1485 break;
1486 }
1487 return NULL;
1488 }
1489
check_hdmi_disabled(struct pci_dev * pci)1490 static bool check_hdmi_disabled(struct pci_dev *pci)
1491 {
1492 bool vga_inactive = false;
1493 struct pci_dev *p = get_bound_vga(pci);
1494
1495 if (p) {
1496 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1497 vga_inactive = true;
1498 pci_dev_put(p);
1499 }
1500 return vga_inactive;
1501 }
1502 #endif /* SUPPORT_VGA_SWITCHEROO */
1503
1504 /*
1505 * allow/deny-listing for position_fix
1506 */
1507 static const struct snd_pci_quirk position_fix_list[] = {
1508 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1509 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1510 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1511 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1512 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1513 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1514 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1515 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1516 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1517 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1518 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1519 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1520 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1521 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1522 {}
1523 };
1524
check_position_fix(struct azx * chip,int fix)1525 static int check_position_fix(struct azx *chip, int fix)
1526 {
1527 const struct snd_pci_quirk *q;
1528
1529 switch (fix) {
1530 case POS_FIX_AUTO:
1531 case POS_FIX_LPIB:
1532 case POS_FIX_POSBUF:
1533 case POS_FIX_VIACOMBO:
1534 case POS_FIX_COMBO:
1535 case POS_FIX_SKL:
1536 case POS_FIX_FIFO:
1537 return fix;
1538 }
1539
1540 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1541 if (q) {
1542 dev_info(chip->card->dev,
1543 "position_fix set to %d for device %04x:%04x\n",
1544 q->value, q->subvendor, q->subdevice);
1545 return q->value;
1546 }
1547
1548 /* Check VIA/ATI HD Audio Controller exist */
1549 if (chip->driver_type == AZX_DRIVER_VIA) {
1550 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1551 return POS_FIX_VIACOMBO;
1552 }
1553 if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) {
1554 dev_dbg(chip->card->dev, "Using FIFO position fix\n");
1555 return POS_FIX_FIFO;
1556 }
1557 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1558 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1559 return POS_FIX_LPIB;
1560 }
1561 if (chip->driver_type == AZX_DRIVER_SKL) {
1562 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1563 return POS_FIX_SKL;
1564 }
1565 return POS_FIX_AUTO;
1566 }
1567
assign_position_fix(struct azx * chip,int fix)1568 static void assign_position_fix(struct azx *chip, int fix)
1569 {
1570 static const azx_get_pos_callback_t callbacks[] = {
1571 [POS_FIX_AUTO] = NULL,
1572 [POS_FIX_LPIB] = azx_get_pos_lpib,
1573 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1574 [POS_FIX_VIACOMBO] = azx_via_get_position,
1575 [POS_FIX_COMBO] = azx_get_pos_lpib,
1576 [POS_FIX_SKL] = azx_get_pos_posbuf,
1577 [POS_FIX_FIFO] = azx_get_pos_fifo,
1578 };
1579
1580 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1581
1582 /* combo mode uses LPIB only for playback */
1583 if (fix == POS_FIX_COMBO)
1584 chip->get_position[1] = NULL;
1585
1586 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
1587 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1588 chip->get_delay[0] = chip->get_delay[1] =
1589 azx_get_delay_from_lpib;
1590 }
1591
1592 if (fix == POS_FIX_FIFO)
1593 chip->get_delay[0] = chip->get_delay[1] =
1594 azx_get_delay_from_fifo;
1595 }
1596
1597 /*
1598 * deny-lists for probe_mask
1599 */
1600 static const struct snd_pci_quirk probe_mask_list[] = {
1601 /* Thinkpad often breaks the controller communication when accessing
1602 * to the non-working (or non-existing) modem codec slot.
1603 */
1604 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1605 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1606 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1607 /* broken BIOS */
1608 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1609 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1610 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1611 /* forced codec slots */
1612 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1613 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1614 SND_PCI_QUIRK(0x1558, 0x0351, "Schenker Dock 15", 0x105),
1615 /* WinFast VP200 H (Teradici) user reported broken communication */
1616 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1617 {}
1618 };
1619
1620 #define AZX_FORCE_CODEC_MASK 0x100
1621
check_probe_mask(struct azx * chip,int dev)1622 static void check_probe_mask(struct azx *chip, int dev)
1623 {
1624 const struct snd_pci_quirk *q;
1625
1626 chip->codec_probe_mask = probe_mask[dev];
1627 if (chip->codec_probe_mask == -1) {
1628 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1629 if (q) {
1630 dev_info(chip->card->dev,
1631 "probe_mask set to 0x%x for device %04x:%04x\n",
1632 q->value, q->subvendor, q->subdevice);
1633 chip->codec_probe_mask = q->value;
1634 }
1635 }
1636
1637 /* check forced option */
1638 if (chip->codec_probe_mask != -1 &&
1639 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1640 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1641 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1642 (int)azx_bus(chip)->codec_mask);
1643 }
1644 }
1645
1646 /*
1647 * allow/deny-list for enable_msi
1648 */
1649 static const struct snd_pci_quirk msi_deny_list[] = {
1650 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1651 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1652 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1653 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1654 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1655 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1656 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1657 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1658 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1659 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1660 {}
1661 };
1662
check_msi(struct azx * chip)1663 static void check_msi(struct azx *chip)
1664 {
1665 const struct snd_pci_quirk *q;
1666
1667 if (enable_msi >= 0) {
1668 chip->msi = !!enable_msi;
1669 return;
1670 }
1671 chip->msi = 1; /* enable MSI as default */
1672 q = snd_pci_quirk_lookup(chip->pci, msi_deny_list);
1673 if (q) {
1674 dev_info(chip->card->dev,
1675 "msi for device %04x:%04x set to %d\n",
1676 q->subvendor, q->subdevice, q->value);
1677 chip->msi = q->value;
1678 return;
1679 }
1680
1681 /* NVidia chipsets seem to cause troubles with MSI */
1682 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1683 dev_info(chip->card->dev, "Disabling MSI\n");
1684 chip->msi = 0;
1685 }
1686 }
1687
1688 /* check the snoop mode availability */
azx_check_snoop_available(struct azx * chip)1689 static void azx_check_snoop_available(struct azx *chip)
1690 {
1691 int snoop = hda_snoop;
1692
1693 if (snoop >= 0) {
1694 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1695 snoop ? "snoop" : "non-snoop");
1696 chip->snoop = snoop;
1697 chip->uc_buffer = !snoop;
1698 return;
1699 }
1700
1701 snoop = true;
1702 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1703 chip->driver_type == AZX_DRIVER_VIA) {
1704 /* force to non-snoop mode for a new VIA controller
1705 * when BIOS is set
1706 */
1707 u8 val;
1708 pci_read_config_byte(chip->pci, 0x42, &val);
1709 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1710 chip->pci->revision == 0x20))
1711 snoop = false;
1712 }
1713
1714 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1715 snoop = false;
1716
1717 chip->snoop = snoop;
1718 if (!snoop) {
1719 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1720 /* C-Media requires non-cached pages only for CORB/RIRB */
1721 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1722 chip->uc_buffer = true;
1723 }
1724 }
1725
azx_probe_work(struct work_struct * work)1726 static void azx_probe_work(struct work_struct *work)
1727 {
1728 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work.work);
1729 azx_probe_continue(&hda->chip);
1730 }
1731
default_bdl_pos_adj(struct azx * chip)1732 static int default_bdl_pos_adj(struct azx *chip)
1733 {
1734 /* some exceptions: Atoms seem problematic with value 1 */
1735 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1736 switch (chip->pci->device) {
1737 case PCI_DEVICE_ID_INTEL_HDA_BYT:
1738 case PCI_DEVICE_ID_INTEL_HDA_BSW:
1739 return 32;
1740 case PCI_DEVICE_ID_INTEL_HDA_APL:
1741 return 64;
1742 }
1743 }
1744
1745 switch (chip->driver_type) {
1746 /*
1747 * increase the bdl size for Glenfly Gpus for hardware
1748 * limitation on hdac interrupt interval
1749 */
1750 case AZX_DRIVER_GFHDMI:
1751 return 128;
1752 case AZX_DRIVER_ICH:
1753 case AZX_DRIVER_PCH:
1754 return 1;
1755 case AZX_DRIVER_ZHAOXINHDMI:
1756 return 128;
1757 default:
1758 return 32;
1759 }
1760 }
1761
1762 /*
1763 * constructor
1764 */
1765 static const struct hda_controller_ops pci_hda_ops;
1766
azx_create(struct snd_card * card,struct pci_dev * pci,int dev,unsigned int driver_caps,struct azx ** rchip)1767 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1768 int dev, unsigned int driver_caps,
1769 struct azx **rchip)
1770 {
1771 static const struct snd_device_ops ops = {
1772 .dev_disconnect = azx_dev_disconnect,
1773 .dev_free = azx_dev_free,
1774 };
1775 struct hda_intel *hda;
1776 struct azx *chip;
1777 int err;
1778
1779 *rchip = NULL;
1780
1781 err = pcim_enable_device(pci);
1782 if (err < 0)
1783 return err;
1784
1785 hda = devm_kzalloc(&pci->dev, sizeof(*hda), GFP_KERNEL);
1786 if (!hda)
1787 return -ENOMEM;
1788
1789 chip = &hda->chip;
1790 mutex_init(&chip->open_mutex);
1791 chip->card = card;
1792 chip->pci = pci;
1793 chip->ops = &pci_hda_ops;
1794 chip->driver_caps = driver_caps;
1795 chip->driver_type = driver_caps & 0xff;
1796 check_msi(chip);
1797 chip->dev_index = dev;
1798 if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
1799 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
1800 INIT_LIST_HEAD(&chip->pcm_list);
1801 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1802 INIT_LIST_HEAD(&hda->list);
1803 init_vga_switcheroo(chip);
1804 init_completion(&hda->probe_wait);
1805
1806 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1807
1808 if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1809 chip->fallback_to_single_cmd = 1;
1810 else /* explicitly set to single_cmd or not */
1811 chip->single_cmd = single_cmd;
1812
1813 azx_check_snoop_available(chip);
1814
1815 if (bdl_pos_adj[dev] < 0)
1816 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1817 else
1818 chip->bdl_pos_adj = bdl_pos_adj[dev];
1819
1820 err = azx_bus_init(chip, model[dev]);
1821 if (err < 0)
1822 return err;
1823
1824 /* use the non-cached pages in non-snoop mode */
1825 if (!azx_snoop(chip))
1826 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_WC;
1827
1828 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1829 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1830 chip->bus.core.needs_damn_long_delay = 1;
1831 }
1832
1833 check_probe_mask(chip, dev);
1834
1835 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1836 if (err < 0) {
1837 dev_err(card->dev, "Error creating device [card]!\n");
1838 azx_free(chip);
1839 return err;
1840 }
1841
1842 /* continue probing in work context as may trigger request module */
1843 INIT_DELAYED_WORK(&hda->probe_work, azx_probe_work);
1844
1845 *rchip = chip;
1846
1847 return 0;
1848 }
1849
azx_first_init(struct azx * chip)1850 static int azx_first_init(struct azx *chip)
1851 {
1852 int dev = chip->dev_index;
1853 struct pci_dev *pci = chip->pci;
1854 struct snd_card *card = chip->card;
1855 struct hdac_bus *bus = azx_bus(chip);
1856 int err;
1857 unsigned short gcap;
1858 unsigned int dma_bits = 64;
1859
1860 #if BITS_PER_LONG != 64
1861 /* Fix up base address on ULI M5461 */
1862 if (chip->driver_type == AZX_DRIVER_ULI) {
1863 u16 tmp3;
1864 pci_read_config_word(pci, 0x40, &tmp3);
1865 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1866 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1867 }
1868 #endif
1869 /*
1870 * Fix response write request not synced to memory when handle
1871 * hdac interrupt on Glenfly Gpus
1872 */
1873 if (chip->driver_type == AZX_DRIVER_GFHDMI)
1874 bus->polling_mode = 1;
1875
1876 if (chip->driver_type == AZX_DRIVER_LOONGSON) {
1877 bus->polling_mode = 1;
1878 bus->not_use_interrupts = 1;
1879 bus->access_sdnctl_in_dword = 1;
1880 if (!chip->jackpoll_interval)
1881 chip->jackpoll_interval = msecs_to_jiffies(1500);
1882 }
1883
1884 if (chip->driver_type == AZX_DRIVER_ZHAOXINHDMI)
1885 bus->polling_mode = 1;
1886
1887 bus->remap_addr = pcim_iomap_region(pci, 0, "ICH HD audio");
1888 if (IS_ERR(bus->remap_addr))
1889 return PTR_ERR(bus->remap_addr);
1890
1891 bus->addr = pci_resource_start(pci, 0);
1892
1893 if (chip->driver_type == AZX_DRIVER_SKL)
1894 snd_hdac_bus_parse_capabilities(bus);
1895
1896 /*
1897 * Some Intel CPUs has always running timer (ART) feature and
1898 * controller may have Global time sync reporting capability, so
1899 * check both of these before declaring synchronized time reporting
1900 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1901 */
1902 chip->gts_present = false;
1903
1904 #ifdef CONFIG_X86
1905 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1906 chip->gts_present = true;
1907 #endif
1908
1909 if (chip->msi && chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1910 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1911 pci->no_64bit_msi = true;
1912 }
1913
1914 pci_set_master(pci);
1915
1916 gcap = azx_readw(chip, GCAP);
1917 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1918
1919 /* AMD devices support 40 or 48bit DMA, take the safe one */
1920 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1921 dma_bits = 40;
1922
1923 /* disable SB600 64bit support for safety */
1924 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1925 struct pci_dev *p_smbus;
1926 dma_bits = 40;
1927 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1928 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1929 NULL);
1930 if (p_smbus) {
1931 if (p_smbus->revision < 0x30)
1932 gcap &= ~AZX_GCAP_64OK;
1933 pci_dev_put(p_smbus);
1934 }
1935 }
1936
1937 /* NVidia hardware normally only supports up to 40 bits of DMA */
1938 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1939 dma_bits = 40;
1940
1941 /* disable 64bit DMA address on some devices */
1942 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1943 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1944 gcap &= ~AZX_GCAP_64OK;
1945 }
1946
1947 /* disable buffer size rounding to 128-byte multiples if supported */
1948 if (align_buffer_size >= 0)
1949 chip->align_buffer_size = !!align_buffer_size;
1950 else {
1951 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1952 chip->align_buffer_size = 0;
1953 else
1954 chip->align_buffer_size = 1;
1955 }
1956
1957 /* allow 64bit DMA address if supported by H/W */
1958 if (!(gcap & AZX_GCAP_64OK))
1959 dma_bits = 32;
1960 if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(dma_bits)))
1961 dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32));
1962 dma_set_max_seg_size(&pci->dev, UINT_MAX);
1963
1964 /* read number of streams from GCAP register instead of using
1965 * hardcoded value
1966 */
1967 chip->capture_streams = (gcap >> 8) & 0x0f;
1968 chip->playback_streams = (gcap >> 12) & 0x0f;
1969 if (!chip->playback_streams && !chip->capture_streams) {
1970 /* gcap didn't give any info, switching to old method */
1971
1972 switch (chip->driver_type) {
1973 case AZX_DRIVER_ULI:
1974 chip->playback_streams = ULI_NUM_PLAYBACK;
1975 chip->capture_streams = ULI_NUM_CAPTURE;
1976 break;
1977 case AZX_DRIVER_ATIHDMI:
1978 case AZX_DRIVER_ATIHDMI_NS:
1979 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1980 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1981 break;
1982 case AZX_DRIVER_GFHDMI:
1983 case AZX_DRIVER_ZHAOXINHDMI:
1984 case AZX_DRIVER_GENERIC:
1985 default:
1986 chip->playback_streams = ICH6_NUM_PLAYBACK;
1987 chip->capture_streams = ICH6_NUM_CAPTURE;
1988 break;
1989 }
1990 }
1991 chip->capture_index_offset = 0;
1992 chip->playback_index_offset = chip->capture_streams;
1993 chip->num_streams = chip->playback_streams + chip->capture_streams;
1994
1995 /* sanity check for the SDxCTL.STRM field overflow */
1996 if (chip->num_streams > 15 &&
1997 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1998 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1999 "forcing separate stream tags", chip->num_streams);
2000 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
2001 }
2002
2003 /* initialize streams */
2004 err = azx_init_streams(chip);
2005 if (err < 0)
2006 return err;
2007
2008 err = azx_alloc_stream_pages(chip);
2009 if (err < 0)
2010 return err;
2011
2012 /* initialize chip */
2013 azx_init_pci(chip);
2014
2015 snd_hdac_i915_set_bclk(bus);
2016
2017 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
2018
2019 /* codec detection */
2020 if (!azx_bus(chip)->codec_mask) {
2021 dev_err(card->dev, "no codecs found!\n");
2022 /* keep running the rest for the runtime PM */
2023 }
2024
2025 if (azx_acquire_irq(chip, 0) < 0)
2026 return -EBUSY;
2027
2028 strcpy(card->driver, "HDA-Intel");
2029 strscpy(card->shortname, driver_short_names[chip->driver_type],
2030 sizeof(card->shortname));
2031 snprintf(card->longname, sizeof(card->longname),
2032 "%s at 0x%lx irq %i",
2033 card->shortname, bus->addr, bus->irq);
2034
2035 return 0;
2036 }
2037
2038 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2039 /* callback from request_firmware_nowait() */
azx_firmware_cb(const struct firmware * fw,void * context)2040 static void azx_firmware_cb(const struct firmware *fw, void *context)
2041 {
2042 struct snd_card *card = context;
2043 struct azx *chip = card->private_data;
2044
2045 if (fw)
2046 chip->fw = fw;
2047 else
2048 dev_err(card->dev, "Cannot load firmware, continue without patching\n");
2049 if (!chip->disabled) {
2050 /* continue probing */
2051 azx_probe_continue(chip);
2052 }
2053 }
2054 #endif
2055
disable_msi_reset_irq(struct azx * chip)2056 static int disable_msi_reset_irq(struct azx *chip)
2057 {
2058 struct hdac_bus *bus = azx_bus(chip);
2059 int err;
2060
2061 free_irq(bus->irq, chip);
2062 bus->irq = -1;
2063 chip->card->sync_irq = -1;
2064 pci_free_irq_vectors(chip->pci);
2065 chip->msi = 0;
2066 err = azx_acquire_irq(chip, 1);
2067 if (err < 0)
2068 return err;
2069
2070 return 0;
2071 }
2072
2073 /* Denylist for skipping the whole probe:
2074 * some HD-audio PCI entries are exposed without any codecs, and such devices
2075 * should be ignored from the beginning.
2076 */
2077 static const struct pci_device_id driver_denylist[] = {
2078 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */
2079 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */
2080 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */
2081 { PCI_DEVICE_SUB(0x1022, 0x15e3, 0x1022, 0xd601) }, /* ASRock X670E Taichi */
2082 {}
2083 };
2084
2085 static struct pci_device_id driver_denylist_ideapad_z570[] = {
2086 { PCI_DEVICE_SUB(0x10de, 0x0bea, 0x0000, 0x0000) }, /* NVIDIA GF108 HDA */
2087 {}
2088 };
2089
2090 /* DMI-based denylist, to be used when:
2091 * - PCI subsystem IDs are zero, impossible to distinguish from valid sound cards.
2092 * - Different modifications of the same laptop use different GPU models.
2093 */
2094 static const struct dmi_system_id driver_denylist_dmi[] = {
2095 {
2096 /* No HDA in NVIDIA DGPU. BIOS disables it, but quirk_nvidia_hda() reenables. */
2097 .matches = {
2098 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
2099 DMI_MATCH(DMI_PRODUCT_VERSION, "Ideapad Z570"),
2100 },
2101 .driver_data = &driver_denylist_ideapad_z570,
2102 },
2103 {}
2104 };
2105
2106 static const struct hda_controller_ops pci_hda_ops = {
2107 .disable_msi_reset_irq = disable_msi_reset_irq,
2108 .position_check = azx_position_check,
2109 };
2110
2111 static DECLARE_BITMAP(probed_devs, SNDRV_CARDS);
2112
azx_probe(struct pci_dev * pci,const struct pci_device_id * pci_id)2113 static int azx_probe(struct pci_dev *pci,
2114 const struct pci_device_id *pci_id)
2115 {
2116 const struct dmi_system_id *dmi;
2117 struct snd_card *card;
2118 struct hda_intel *hda;
2119 struct azx *chip;
2120 bool schedule_probe;
2121 int dev;
2122 int err;
2123
2124 if (pci_match_id(driver_denylist, pci)) {
2125 dev_info(&pci->dev, "Skipping the device on the denylist\n");
2126 return -ENODEV;
2127 }
2128
2129 dmi = dmi_first_match(driver_denylist_dmi);
2130 if (dmi && pci_match_id(dmi->driver_data, pci)) {
2131 dev_info(&pci->dev, "Skipping the device on the DMI denylist\n");
2132 return -ENODEV;
2133 }
2134
2135 dev = find_first_zero_bit(probed_devs, SNDRV_CARDS);
2136 if (dev >= SNDRV_CARDS)
2137 return -ENODEV;
2138 if (!enable[dev]) {
2139 set_bit(dev, probed_devs);
2140 return -ENOENT;
2141 }
2142
2143 /*
2144 * stop probe if another Intel's DSP driver should be activated
2145 */
2146 if (dmic_detect) {
2147 err = snd_intel_dsp_driver_probe(pci);
2148 if (err != SND_INTEL_DSP_DRIVER_ANY && err != SND_INTEL_DSP_DRIVER_LEGACY) {
2149 dev_dbg(&pci->dev, "HDAudio driver not selected, aborting probe\n");
2150 return -ENODEV;
2151 }
2152 } else {
2153 dev_warn(&pci->dev, "dmic_detect option is deprecated, pass snd-intel-dspcfg.dsp_driver=1 option instead\n");
2154 }
2155
2156 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2157 0, &card);
2158 if (err < 0) {
2159 dev_err(&pci->dev, "Error creating card!\n");
2160 return err;
2161 }
2162
2163 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2164 if (err < 0)
2165 goto out_free;
2166 card->private_data = chip;
2167 hda = container_of(chip, struct hda_intel, chip);
2168
2169 pci_set_drvdata(pci, card);
2170
2171 #ifdef CONFIG_SND_HDA_I915
2172 /* bind with i915 if needed */
2173 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
2174 err = snd_hdac_i915_init(azx_bus(chip));
2175 if (err < 0) {
2176 if (err == -EPROBE_DEFER)
2177 goto out_free;
2178
2179 /* if the controller is bound only with HDMI/DP
2180 * (for HSW and BDW), we need to abort the probe;
2181 * for other chips, still continue probing as other
2182 * codecs can be on the same link.
2183 */
2184 if (HDA_CONTROLLER_IN_GPU(pci)) {
2185 dev_err_probe(card->dev, err,
2186 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2187
2188 goto out_free;
2189 } else {
2190 /* don't bother any longer */
2191 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;
2192 }
2193 }
2194
2195 /* HSW/BDW controllers need this power */
2196 if (HDA_CONTROLLER_IN_GPU(pci))
2197 hda->need_i915_power = true;
2198 }
2199 #else
2200 if (HDA_CONTROLLER_IN_GPU(pci))
2201 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2202 #endif
2203
2204 err = register_vga_switcheroo(chip);
2205 if (err < 0) {
2206 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2207 goto out_free;
2208 }
2209
2210 if (check_hdmi_disabled(pci)) {
2211 dev_info(card->dev, "VGA controller is disabled\n");
2212 dev_info(card->dev, "Delaying initialization\n");
2213 chip->disabled = true;
2214 }
2215
2216 schedule_probe = !chip->disabled;
2217
2218 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2219 if (patch[dev] && *patch[dev]) {
2220 dev_info(card->dev, "Applying patch firmware '%s'\n",
2221 patch[dev]);
2222 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2223 &pci->dev, GFP_KERNEL, card,
2224 azx_firmware_cb);
2225 if (err < 0)
2226 goto out_free;
2227 schedule_probe = false; /* continued in azx_firmware_cb() */
2228 }
2229 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2230
2231 if (schedule_probe)
2232 schedule_delayed_work(&hda->probe_work, 0);
2233
2234 set_bit(dev, probed_devs);
2235 if (chip->disabled)
2236 complete_all(&hda->probe_wait);
2237 return 0;
2238
2239 out_free:
2240 pci_set_drvdata(pci, NULL);
2241 snd_card_free(card);
2242 return err;
2243 }
2244
2245 /* On some boards setting power_save to a non 0 value leads to clicking /
2246 * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2247 * figure out how to avoid these sounds, but that is not always feasible.
2248 * So we keep a list of devices where we disable powersaving as its known
2249 * to causes problems on these devices.
2250 */
2251 static const struct snd_pci_quirk power_save_denylist[] = {
2252 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2253 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
2254 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2255 SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2256 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2257 SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2258 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2259 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2260 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2261 SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2262 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2263 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2264 SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
2265 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2266 SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
2267 /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2268 SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
2269 /* https://bugs.launchpad.net/bugs/1821663 */
2270 SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
2271 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2272 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
2273 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2274 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2275 SND_PCI_QUIRK(0x17aa, 0x316e, "Lenovo ThinkCentre M70q", 0),
2276 /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
2277 SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
2278 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2279 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
2280 /* https://bugs.launchpad.net/bugs/1821663 */
2281 SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
2282 /* KONTRON SinglePC may cause a stall at runtime resume */
2283 SND_PCI_QUIRK(0x1734, 0x1232, "KONTRON SinglePC", 0),
2284 /* Dell ALC3271 */
2285 SND_PCI_QUIRK(0x1028, 0x0962, "Dell ALC3271", 0),
2286 /* https://bugzilla.kernel.org/show_bug.cgi?id=220210 */
2287 SND_PCI_QUIRK(0x17aa, 0x5079, "Lenovo Thinkpad E15", 0),
2288 {}
2289 };
2290
set_default_power_save(struct azx * chip)2291 static void set_default_power_save(struct azx *chip)
2292 {
2293 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2294 int val = power_save;
2295
2296 if (pm_blacklist < 0) {
2297 const struct snd_pci_quirk *q;
2298
2299 q = snd_pci_quirk_lookup(chip->pci, power_save_denylist);
2300 if (q && val) {
2301 dev_info(chip->card->dev, "device %04x:%04x is on the power_save denylist, forcing power_save to 0\n",
2302 q->subvendor, q->subdevice);
2303 val = 0;
2304 hda->runtime_pm_disabled = 1;
2305 }
2306 } else if (pm_blacklist > 0) {
2307 dev_info(chip->card->dev, "Forcing power_save to 0 via option\n");
2308 val = 0;
2309 }
2310 snd_hda_set_power_save(&chip->bus, val * 1000);
2311 }
2312
2313 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2314 static const unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2315 [AZX_DRIVER_NVIDIA] = 8,
2316 [AZX_DRIVER_TERA] = 1,
2317 };
2318
azx_probe_continue(struct azx * chip)2319 static int azx_probe_continue(struct azx *chip)
2320 {
2321 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2322 struct hdac_bus *bus = azx_bus(chip);
2323 struct pci_dev *pci = chip->pci;
2324 int dev = chip->dev_index;
2325 int err;
2326
2327 if (chip->disabled || hda->init_failed)
2328 return -EIO;
2329 if (hda->probe_retry)
2330 goto probe_retry;
2331
2332 to_hda_bus(bus)->bus_probing = 1;
2333 hda->probe_continued = 1;
2334
2335 /* Request display power well for the HDA controller or codec. For
2336 * Haswell/Broadwell, both the display HDA controller and codec need
2337 * this power. For other platforms, like Baytrail/Braswell, only the
2338 * display codec needs the power and it can be released after probe.
2339 */
2340 display_power(chip, true);
2341
2342 err = azx_first_init(chip);
2343 if (err < 0)
2344 goto out_free;
2345
2346 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2347 chip->beep_mode = beep_mode[dev];
2348 #endif
2349
2350 chip->ctl_dev_id = ctl_dev_id;
2351
2352 /* create codec instances */
2353 if (bus->codec_mask) {
2354 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2355 if (err < 0)
2356 goto out_free;
2357 }
2358
2359 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2360 if (chip->fw) {
2361 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2362 chip->fw->data);
2363 if (err < 0)
2364 goto out_free;
2365 }
2366 #endif
2367
2368 probe_retry:
2369 if (bus->codec_mask && !(probe_only[dev] & 1)) {
2370 err = azx_codec_configure(chip);
2371 if (err) {
2372 if ((chip->driver_caps & AZX_DCAPS_RETRY_PROBE) &&
2373 ++hda->probe_retry < 60) {
2374 schedule_delayed_work(&hda->probe_work,
2375 msecs_to_jiffies(1000));
2376 return 0; /* keep things up */
2377 }
2378 dev_err(chip->card->dev, "Cannot probe codecs, giving up\n");
2379 goto out_free;
2380 }
2381 }
2382
2383 err = snd_card_register(chip->card);
2384 if (err < 0)
2385 goto out_free;
2386
2387 setup_vga_switcheroo_runtime_pm(chip);
2388
2389 chip->running = 1;
2390 azx_add_card_list(chip);
2391
2392 set_default_power_save(chip);
2393
2394 if (azx_has_pm_runtime(chip)) {
2395 pm_runtime_use_autosuspend(&pci->dev);
2396 pm_runtime_allow(&pci->dev);
2397 pm_runtime_put_autosuspend(&pci->dev);
2398 }
2399
2400 out_free:
2401 if (err < 0) {
2402 pci_set_drvdata(pci, NULL);
2403 snd_card_free(chip->card);
2404 return err;
2405 }
2406
2407 if (!hda->need_i915_power)
2408 display_power(chip, false);
2409 complete_all(&hda->probe_wait);
2410 to_hda_bus(bus)->bus_probing = 0;
2411 hda->probe_retry = 0;
2412 return 0;
2413 }
2414
azx_remove(struct pci_dev * pci)2415 static void azx_remove(struct pci_dev *pci)
2416 {
2417 struct snd_card *card = pci_get_drvdata(pci);
2418 struct azx *chip;
2419 struct hda_intel *hda;
2420
2421 if (card) {
2422 /* cancel the pending probing work */
2423 chip = card->private_data;
2424 hda = container_of(chip, struct hda_intel, chip);
2425 /* FIXME: below is an ugly workaround.
2426 * Both device_release_driver() and driver_probe_device()
2427 * take *both* the device's and its parent's lock before
2428 * calling the remove() and probe() callbacks. The codec
2429 * probe takes the locks of both the codec itself and its
2430 * parent, i.e. the PCI controller dev. Meanwhile, when
2431 * the PCI controller is unbound, it takes its lock, too
2432 * ==> ouch, a deadlock!
2433 * As a workaround, we unlock temporarily here the controller
2434 * device during cancel_work_sync() call.
2435 */
2436 device_unlock(&pci->dev);
2437 cancel_delayed_work_sync(&hda->probe_work);
2438 device_lock(&pci->dev);
2439
2440 clear_bit(chip->dev_index, probed_devs);
2441 pci_set_drvdata(pci, NULL);
2442 snd_card_free(card);
2443 }
2444 }
2445
azx_shutdown(struct pci_dev * pci)2446 static void azx_shutdown(struct pci_dev *pci)
2447 {
2448 struct snd_card *card = pci_get_drvdata(pci);
2449 struct azx *chip;
2450
2451 if (!card)
2452 return;
2453 chip = card->private_data;
2454 if (chip && chip->running)
2455 __azx_shutdown_chip(chip, true);
2456 }
2457
2458 /* PCI IDs */
2459 static const struct pci_device_id azx_ids[] = {
2460 /* CPT */
2461 { PCI_DEVICE_DATA(INTEL, HDA_CPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) },
2462 /* PBG */
2463 { PCI_DEVICE_DATA(INTEL, HDA_PBG, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) },
2464 /* Panther Point */
2465 { PCI_DEVICE_DATA(INTEL, HDA_PPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) },
2466 /* Lynx Point */
2467 { PCI_DEVICE_DATA(INTEL, HDA_LPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
2468 /* 9 Series */
2469 { PCI_DEVICE_DATA(INTEL, HDA_9_SERIES, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
2470 /* Wellsburg */
2471 { PCI_DEVICE_DATA(INTEL, HDA_WBG_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
2472 { PCI_DEVICE_DATA(INTEL, HDA_WBG_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
2473 /* Lewisburg */
2474 { PCI_DEVICE_DATA(INTEL, HDA_LBG_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE) },
2475 { PCI_DEVICE_DATA(INTEL, HDA_LBG_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE) },
2476 /* Lynx Point-LP */
2477 { PCI_DEVICE_DATA(INTEL, HDA_LPT_LP_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
2478 /* Lynx Point-LP */
2479 { PCI_DEVICE_DATA(INTEL, HDA_LPT_LP_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
2480 /* Wildcat Point-LP */
2481 { PCI_DEVICE_DATA(INTEL, HDA_WPT_LP, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
2482 /* Skylake (Sunrise Point) */
2483 { PCI_DEVICE_DATA(INTEL, HDA_SKL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2484 /* Skylake-LP (Sunrise Point-LP) */
2485 { PCI_DEVICE_DATA(INTEL, HDA_SKL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2486 /* Kabylake */
2487 { PCI_DEVICE_DATA(INTEL, HDA_KBL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2488 /* Kabylake-LP */
2489 { PCI_DEVICE_DATA(INTEL, HDA_KBL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2490 /* Kabylake-H */
2491 { PCI_DEVICE_DATA(INTEL, HDA_KBL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2492 /* Coffelake */
2493 { PCI_DEVICE_DATA(INTEL, HDA_CNL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2494 /* Cannonlake */
2495 { PCI_DEVICE_DATA(INTEL, HDA_CNL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2496 /* CometLake-LP */
2497 { PCI_DEVICE_DATA(INTEL, HDA_CML_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2498 /* CometLake-H */
2499 { PCI_DEVICE_DATA(INTEL, HDA_CML_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2500 { PCI_DEVICE_DATA(INTEL, HDA_RKL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2501 /* CometLake-S */
2502 { PCI_DEVICE_DATA(INTEL, HDA_CML_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2503 /* CometLake-R */
2504 { PCI_DEVICE_DATA(INTEL, HDA_CML_R, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2505 /* Icelake */
2506 { PCI_DEVICE_DATA(INTEL, HDA_ICL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2507 /* Icelake-H */
2508 { PCI_DEVICE_DATA(INTEL, HDA_ICL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2509 /* Jasperlake */
2510 { PCI_DEVICE_DATA(INTEL, HDA_ICL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2511 { PCI_DEVICE_DATA(INTEL, HDA_JSL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2512 /* Tigerlake */
2513 { PCI_DEVICE_DATA(INTEL, HDA_TGL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2514 /* Tigerlake-H */
2515 { PCI_DEVICE_DATA(INTEL, HDA_TGL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2516 /* DG1 */
2517 { PCI_DEVICE_DATA(INTEL, HDA_DG1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2518 /* DG2 */
2519 { PCI_DEVICE_DATA(INTEL, HDA_DG2_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2520 { PCI_DEVICE_DATA(INTEL, HDA_DG2_1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2521 { PCI_DEVICE_DATA(INTEL, HDA_DG2_2, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2522 /* Alderlake-S */
2523 { PCI_DEVICE_DATA(INTEL, HDA_ADL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2524 /* Alderlake-P */
2525 { PCI_DEVICE_DATA(INTEL, HDA_ADL_P, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2526 { PCI_DEVICE_DATA(INTEL, HDA_ADL_PS, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2527 { PCI_DEVICE_DATA(INTEL, HDA_ADL_PX, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2528 /* Alderlake-M */
2529 { PCI_DEVICE_DATA(INTEL, HDA_ADL_M, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2530 /* Alderlake-N */
2531 { PCI_DEVICE_DATA(INTEL, HDA_ADL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2532 /* Elkhart Lake */
2533 { PCI_DEVICE_DATA(INTEL, HDA_EHL_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2534 { PCI_DEVICE_DATA(INTEL, HDA_EHL_3, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2535 /* Raptor Lake */
2536 { PCI_DEVICE_DATA(INTEL, HDA_RPL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2537 { PCI_DEVICE_DATA(INTEL, HDA_RPL_P_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2538 { PCI_DEVICE_DATA(INTEL, HDA_RPL_P_1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2539 { PCI_DEVICE_DATA(INTEL, HDA_RPL_M, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2540 { PCI_DEVICE_DATA(INTEL, HDA_RPL_PX, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2541 { PCI_DEVICE_DATA(INTEL, HDA_MTL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2542 /* Battlemage */
2543 { PCI_DEVICE_DATA(INTEL, HDA_BMG, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2544 /* Lunarlake-P */
2545 { PCI_DEVICE_DATA(INTEL, HDA_LNL_P, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_LNL) },
2546 /* Arrow Lake-S */
2547 { PCI_DEVICE_DATA(INTEL, HDA_ARL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2548 /* Arrow Lake */
2549 { PCI_DEVICE_DATA(INTEL, HDA_ARL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2550 /* Panther Lake */
2551 { PCI_DEVICE_DATA(INTEL, HDA_PTL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_LNL) },
2552 /* Panther Lake-H */
2553 { PCI_DEVICE_DATA(INTEL, HDA_PTL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_LNL) },
2554 /* Wildcat Lake */
2555 { PCI_DEVICE_DATA(INTEL, HDA_WCL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_LNL) },
2556 /* Apollolake (Broxton-P) */
2557 { PCI_DEVICE_DATA(INTEL, HDA_APL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON) },
2558 /* Gemini-Lake */
2559 { PCI_DEVICE_DATA(INTEL, HDA_GML, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON) },
2560 /* Haswell */
2561 { PCI_DEVICE_DATA(INTEL, HDA_HSW_0, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) },
2562 { PCI_DEVICE_DATA(INTEL, HDA_HSW_2, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) },
2563 { PCI_DEVICE_DATA(INTEL, HDA_HSW_3, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) },
2564 /* Broadwell */
2565 { PCI_DEVICE_DATA(INTEL, HDA_BDW, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL) },
2566 /* 5 Series/3400 */
2567 { PCI_DEVICE_DATA(INTEL, HDA_5_3400_SERIES_0, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM) },
2568 { PCI_DEVICE_DATA(INTEL, HDA_5_3400_SERIES_1, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM) },
2569 /* Poulsbo */
2570 { PCI_DEVICE_DATA(INTEL, HDA_POULSBO, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE |
2571 AZX_DCAPS_POSFIX_LPIB) },
2572 /* Oaktrail */
2573 { PCI_DEVICE_DATA(INTEL, HDA_OAKTRAIL, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE) },
2574 /* BayTrail */
2575 { PCI_DEVICE_DATA(INTEL, HDA_BYT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL) },
2576 /* Braswell */
2577 { PCI_DEVICE_DATA(INTEL, HDA_BSW, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL) },
2578 /* ICH6 */
2579 { PCI_DEVICE_DATA(INTEL, HDA_ICH6, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
2580 /* ICH7 */
2581 { PCI_DEVICE_DATA(INTEL, HDA_ICH7, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
2582 /* ESB2 */
2583 { PCI_DEVICE_DATA(INTEL, HDA_ESB2, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
2584 /* ICH8 */
2585 { PCI_DEVICE_DATA(INTEL, HDA_ICH8, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
2586 /* ICH9 */
2587 { PCI_DEVICE_DATA(INTEL, HDA_ICH9_0, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
2588 /* ICH9 */
2589 { PCI_DEVICE_DATA(INTEL, HDA_ICH9_1, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
2590 /* ICH10 */
2591 { PCI_DEVICE_DATA(INTEL, HDA_ICH10_0, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
2592 /* ICH10 */
2593 { PCI_DEVICE_DATA(INTEL, HDA_ICH10_1, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
2594 /* Generic Intel */
2595 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2596 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2597 .class_mask = 0xffffff,
2598 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2599 /* ATI SB 450/600/700/800/900 */
2600 { PCI_VDEVICE(ATI, 0x437b),
2601 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2602 { PCI_VDEVICE(ATI, 0x4383),
2603 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2604 /* AMD Hudson */
2605 { PCI_VDEVICE(AMD, 0x780d),
2606 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2607 /* AMD, X370 & co */
2608 { PCI_VDEVICE(AMD, 0x1457),
2609 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2610 /* AMD, X570 & co */
2611 { PCI_VDEVICE(AMD, 0x1487),
2612 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2613 /* AMD Stoney */
2614 { PCI_VDEVICE(AMD, 0x157a),
2615 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2616 AZX_DCAPS_PM_RUNTIME },
2617 /* AMD Raven */
2618 { PCI_VDEVICE(AMD, 0x15e3),
2619 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2620 /* ATI HDMI */
2621 { PCI_VDEVICE(ATI, 0x0002),
2622 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2623 AZX_DCAPS_PM_RUNTIME },
2624 { PCI_VDEVICE(ATI, 0x1308),
2625 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2626 { PCI_VDEVICE(ATI, 0x157a),
2627 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2628 { PCI_VDEVICE(ATI, 0x15b3),
2629 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2630 { PCI_VDEVICE(ATI, 0x793b),
2631 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2632 { PCI_VDEVICE(ATI, 0x7919),
2633 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2634 { PCI_VDEVICE(ATI, 0x960f),
2635 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2636 { PCI_VDEVICE(ATI, 0x970f),
2637 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2638 { PCI_VDEVICE(ATI, 0x9840),
2639 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2640 { PCI_VDEVICE(ATI, 0xaa00),
2641 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2642 { PCI_VDEVICE(ATI, 0xaa08),
2643 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2644 { PCI_VDEVICE(ATI, 0xaa10),
2645 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2646 { PCI_VDEVICE(ATI, 0xaa18),
2647 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2648 { PCI_VDEVICE(ATI, 0xaa20),
2649 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2650 { PCI_VDEVICE(ATI, 0xaa28),
2651 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2652 { PCI_VDEVICE(ATI, 0xaa30),
2653 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2654 { PCI_VDEVICE(ATI, 0xaa38),
2655 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2656 { PCI_VDEVICE(ATI, 0xaa40),
2657 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2658 { PCI_VDEVICE(ATI, 0xaa48),
2659 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2660 { PCI_VDEVICE(ATI, 0xaa50),
2661 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2662 { PCI_VDEVICE(ATI, 0xaa58),
2663 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2664 { PCI_VDEVICE(ATI, 0xaa60),
2665 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2666 { PCI_VDEVICE(ATI, 0xaa68),
2667 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2668 { PCI_VDEVICE(ATI, 0xaa80),
2669 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2670 { PCI_VDEVICE(ATI, 0xaa88),
2671 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2672 { PCI_VDEVICE(ATI, 0xaa90),
2673 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2674 { PCI_VDEVICE(ATI, 0xaa98),
2675 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2676 { PCI_VDEVICE(ATI, 0x9902),
2677 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2678 { PCI_VDEVICE(ATI, 0xaaa0),
2679 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2680 { PCI_VDEVICE(ATI, 0xaaa8),
2681 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2682 { PCI_VDEVICE(ATI, 0xaab0),
2683 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2684 { PCI_VDEVICE(ATI, 0xaac0),
2685 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2686 AZX_DCAPS_PM_RUNTIME },
2687 { PCI_VDEVICE(ATI, 0xaac8),
2688 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2689 AZX_DCAPS_PM_RUNTIME },
2690 { PCI_VDEVICE(ATI, 0xaad8),
2691 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2692 AZX_DCAPS_PM_RUNTIME },
2693 { PCI_VDEVICE(ATI, 0xaae0),
2694 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2695 AZX_DCAPS_PM_RUNTIME },
2696 { PCI_VDEVICE(ATI, 0xaae8),
2697 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2698 AZX_DCAPS_PM_RUNTIME },
2699 { PCI_VDEVICE(ATI, 0xaaf0),
2700 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2701 AZX_DCAPS_PM_RUNTIME },
2702 { PCI_VDEVICE(ATI, 0xaaf8),
2703 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2704 AZX_DCAPS_PM_RUNTIME },
2705 { PCI_VDEVICE(ATI, 0xab00),
2706 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2707 AZX_DCAPS_PM_RUNTIME },
2708 { PCI_VDEVICE(ATI, 0xab08),
2709 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2710 AZX_DCAPS_PM_RUNTIME },
2711 { PCI_VDEVICE(ATI, 0xab10),
2712 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2713 AZX_DCAPS_PM_RUNTIME },
2714 { PCI_VDEVICE(ATI, 0xab18),
2715 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2716 AZX_DCAPS_PM_RUNTIME },
2717 { PCI_VDEVICE(ATI, 0xab20),
2718 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2719 AZX_DCAPS_PM_RUNTIME },
2720 { PCI_VDEVICE(ATI, 0xab28),
2721 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2722 AZX_DCAPS_PM_RUNTIME },
2723 { PCI_VDEVICE(ATI, 0xab30),
2724 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2725 AZX_DCAPS_PM_RUNTIME },
2726 { PCI_VDEVICE(ATI, 0xab38),
2727 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2728 AZX_DCAPS_PM_RUNTIME },
2729 { PCI_VDEVICE(ATI, 0xab40),
2730 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2731 AZX_DCAPS_PM_RUNTIME },
2732 /* GLENFLY */
2733 { PCI_DEVICE(PCI_VENDOR_ID_GLENFLY, PCI_ANY_ID),
2734 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2735 .class_mask = 0xffffff,
2736 .driver_data = AZX_DRIVER_GFHDMI | AZX_DCAPS_POSFIX_LPIB |
2737 AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT },
2738 /* VIA VT8251/VT8237A */
2739 { PCI_VDEVICE(VIA, 0x3288), .driver_data = AZX_DRIVER_VIA },
2740 /* VIA GFX VT7122/VX900 */
2741 { PCI_VDEVICE(VIA, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2742 /* VIA GFX VT6122/VX11 */
2743 { PCI_VDEVICE(VIA, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2744 /* SIS966 */
2745 { PCI_VDEVICE(SI, 0x7502), .driver_data = AZX_DRIVER_SIS },
2746 /* ULI M5461 */
2747 { PCI_VDEVICE(AL, 0x5461), .driver_data = AZX_DRIVER_ULI },
2748 /* NVIDIA MCP */
2749 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2750 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2751 .class_mask = 0xffffff,
2752 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2753 /* Teradici */
2754 { PCI_DEVICE(0x6549, 0x1200),
2755 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2756 { PCI_DEVICE(0x6549, 0x2200),
2757 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2758 /* Creative X-Fi (CA0110-IBG) */
2759 /* CTHDA chips */
2760 { PCI_VDEVICE(CREATIVE, 0x0010),
2761 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2762 { PCI_VDEVICE(CREATIVE, 0x0012),
2763 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2764 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2765 /* the following entry conflicts with snd-ctxfi driver,
2766 * as ctxfi driver mutates from HD-audio to native mode with
2767 * a special command sequence.
2768 */
2769 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2770 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2771 .class_mask = 0xffffff,
2772 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2773 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2774 #else
2775 /* this entry seems still valid -- i.e. without emu20kx chip */
2776 { PCI_VDEVICE(CREATIVE, 0x0009),
2777 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2778 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2779 #endif
2780 /* CM8888 */
2781 { PCI_VDEVICE(CMEDIA, 0x5011),
2782 .driver_data = AZX_DRIVER_CMEDIA |
2783 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2784 /* Vortex86MX */
2785 { PCI_VDEVICE(RDC, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2786 /* VMware HDAudio */
2787 { PCI_VDEVICE(VMWARE, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2788 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2789 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2790 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2791 .class_mask = 0xffffff,
2792 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2793 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2794 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2795 .class_mask = 0xffffff,
2796 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2797 /* Zhaoxin */
2798 { PCI_VDEVICE(ZHAOXIN, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN },
2799 { PCI_VDEVICE(ZHAOXIN, 0x9141),
2800 .driver_data = AZX_DRIVER_ZHAOXINHDMI | AZX_DCAPS_POSFIX_LPIB |
2801 AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT },
2802 { PCI_VDEVICE(ZHAOXIN, 0x9142),
2803 .driver_data = AZX_DRIVER_ZHAOXINHDMI | AZX_DCAPS_POSFIX_LPIB |
2804 AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT },
2805 { PCI_VDEVICE(ZHAOXIN, 0x9144),
2806 .driver_data = AZX_DRIVER_ZHAOXINHDMI | AZX_DCAPS_POSFIX_LPIB |
2807 AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT },
2808 { PCI_VDEVICE(ZHAOXIN, 0x9145),
2809 .driver_data = AZX_DRIVER_ZHAOXINHDMI | AZX_DCAPS_POSFIX_LPIB |
2810 AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT },
2811 { PCI_VDEVICE(ZHAOXIN, 0x9146),
2812 .driver_data = AZX_DRIVER_ZHAOXINHDMI | AZX_DCAPS_POSFIX_LPIB |
2813 AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT },
2814 /* Loongson HDAudio*/
2815 { PCI_VDEVICE(LOONGSON, PCI_DEVICE_ID_LOONGSON_HDA),
2816 .driver_data = AZX_DRIVER_LOONGSON | AZX_DCAPS_NO_TCSEL },
2817 { PCI_VDEVICE(LOONGSON, PCI_DEVICE_ID_LOONGSON_HDMI),
2818 .driver_data = AZX_DRIVER_LOONGSON | AZX_DCAPS_NO_TCSEL },
2819 { 0, }
2820 };
2821 MODULE_DEVICE_TABLE(pci, azx_ids);
2822
2823 /* pci_driver definition */
2824 static struct pci_driver azx_driver = {
2825 .name = KBUILD_MODNAME,
2826 .id_table = azx_ids,
2827 .probe = azx_probe,
2828 .remove = azx_remove,
2829 .shutdown = azx_shutdown,
2830 .driver = {
2831 .pm = pm_ptr(&azx_pm),
2832 },
2833 };
2834
2835 module_pci_driver(azx_driver);
2836