1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License, Version 1.0 only
6 * (the "License"). You may not use this file except in compliance
7 * with the License.
8 *
9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10 * or http://www.opensolaris.org/os/licensing.
11 * See the License for the specific language governing permissions
12 * and limitations under the License.
13 *
14 * When distributing Covered Code, include this CDDL HEADER in each
15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16 * If applicable, add the following below this CDDL HEADER, with the
17 * fields enclosed by brackets "[]" replaced with your own identifying
18 * information: Portions Copyright [yyyy] [name of copyright owner]
19 *
20 * CDDL HEADER END
21 */
22 /*
23 * Copyright 2004 Sun Microsystems, Inc. All rights reserved.
24 * Use is subject to license terms.
25 */
26
27 #pragma ident "%Z%%M% %I% %E% SMI"
28
29 /*
30 * hci1394_s1394if.c
31 * The interface into the HAL from the services layer.
32 */
33
34 #include <sys/conf.h>
35 #include <sys/ddi.h>
36 #include <sys/modctl.h>
37 #include <sys/stat.h>
38 #include <sys/sunddi.h>
39 #include <sys/cmn_err.h>
40
41 #include <sys/1394/h1394.h>
42 #include <sys/1394/ixl1394.h>
43 #include <sys/1394/adapters/hci1394.h>
44
45
46 static void hci1394_s1394if_shutdown(void *hal_private);
47 static int hci1394_s1394if_phy(void *hal_private, cmd1394_cmd_t *cmd_id,
48 h1394_cmd_priv_t *cmd_private, int *result);
49 static int hci1394_s1394if_write(void *hal_private, cmd1394_cmd_t *cmd_id,
50 h1394_cmd_priv_t *cmd_private, int *result);
51 static int hci1394_s1394if_read(void *hal_private, cmd1394_cmd_t *cmd_id,
52 h1394_cmd_priv_t *cmd_private, int *result);
53 static int hci1394_s1394if_lock(void *hal_private, cmd1394_cmd_t *cmd_id,
54 h1394_cmd_priv_t *cmd_private, int *result);
55 static int hci1394_s1394if_write_response(void *hal_private,
56 cmd1394_cmd_t *cmd_id, h1394_cmd_priv_t *cmd_private, int *result);
57 static int hci1394_s1394if_read_response(void *hal_private,
58 cmd1394_cmd_t *cmd_id, h1394_cmd_priv_t *cmd_private, int *result);
59 static int hci1394_s1394if_lock_response(void *hal_private,
60 cmd1394_cmd_t *cmd_id, h1394_cmd_priv_t *cmd_private, int *result);
61 static void hci1394_s1394if_response_complete(void *hal_private,
62 cmd1394_cmd_t *cmd_id, h1394_cmd_priv_t *cmd_private);
63 static int hci1394_s1394if_reset_bus(void *hal_private);
64 static int hci1394_s1394if_set_contender_bit(void *hal_private);
65 static int hci1394_s1394if_set_root_holdoff_bit(void *hal_private);
66 static int hci1394_s1394if_set_gap_count(void *hal_private, uint_t gap_count);
67 static int hci1394_s1394if_update_config_rom(void *hal_private,
68 void *local_buf, uint_t quadlet_count);
69 static int hci1394_s1394if_phy_filter_set(void *hal_private,
70 uint64_t mask, uint_t generation);
71 static int hci1394_s1394if_phy_filter_clr(void *hal_private,
72 uint64_t mask, uint_t generation);
73 static int hci1394_s1394if_short_bus_reset(void *hal_private);
74 static int hci1394_s1394if_csr_read(void *hal_private,
75 uint_t offset, uint32_t *data);
76 static int hci1394_s1394if_csr_write(void *hal_private,
77 uint_t offset, uint32_t data);
78 static int hci1394_s1394if_csr_cswap32(void *hal_private, uint_t generation,
79 uint_t offset, uint32_t compare, uint32_t swap, uint32_t *old);
80 static void hci1394_s1394if_power_state_change(void *hal_private,
81 h1394_node_pwr_flags_t nodeflags);
82
83
84 /* entry points into HAL from Services Layer */
85 h1394_evts_t hci1394_evts = {
86 H1394_EVTS_V1, /* hal_version */
87 0, /* reserved */
88 hci1394_s1394if_shutdown, /* shutdown */
89 hci1394_s1394if_phy, /* send_phy_config_pkt */
90 hci1394_s1394if_read, /* read */
91 hci1394_s1394if_read_response, /* read_response */
92 hci1394_s1394if_write, /* write */
93 hci1394_s1394if_write_response, /* write_response */
94 hci1394_s1394if_response_complete, /* response_complete */
95 hci1394_s1394if_lock, /* lock */
96 hci1394_s1394if_lock_response, /* lock_response */
97 hci1394_alloc_isoch_dma, /* allocate_isoch_dma */
98 hci1394_free_isoch_dma, /* free_isoch_dma */
99 hci1394_start_isoch_dma, /* start_isoch_dma */
100 hci1394_stop_isoch_dma, /* stop_isoch_dma */
101 hci1394_update_isoch_dma, /* update_isoch_dma */
102 hci1394_s1394if_update_config_rom, /* update_config_rom */
103 hci1394_s1394if_reset_bus, /* bus_reset */
104 hci1394_s1394if_short_bus_reset, /* short_bus_reset */
105 hci1394_s1394if_set_contender_bit, /* set_contender_bit */
106 hci1394_s1394if_set_root_holdoff_bit, /* set_root_holdoff_bit */
107 hci1394_s1394if_set_gap_count, /* set_gap_count */
108 hci1394_s1394if_csr_read, /* csr_read */
109 hci1394_s1394if_csr_write, /* csr_write */
110 hci1394_s1394if_csr_cswap32, /* csr_cswap32 */
111 hci1394_s1394if_phy_filter_set, /* phys_arreq_enable_set */
112 hci1394_s1394if_phy_filter_clr, /* phys_arreq_enable_clr */
113 hci1394_s1394if_power_state_change /* node_power_state_change */
114 };
115
116
117 /*
118 * hci1394_s1394if_shutdown()
119 * Shutdown the HAL. This is called when a critical error has been detected.
120 * This routine should shutdown the HAL so that it will no longer send or
121 * receive information to/from the 1394 bus. The purpose of this function is
122 * to try and keep the machine from crashing.
123 */
124 static void
hci1394_s1394if_shutdown(void * hal_private)125 hci1394_s1394if_shutdown(void *hal_private)
126 {
127 hci1394_state_t *soft_state;
128
129
130 ASSERT(hal_private != NULL);
131 TNF_PROBE_0_DEBUG(hci1394_s1394if_shutdown_enter,
132 HCI1394_TNF_HAL_STACK, "");
133
134 soft_state = (hci1394_state_t *)hal_private;
135 hci1394_shutdown(soft_state->drvinfo.di_dip);
136
137 TNF_PROBE_0_DEBUG(hci1394_s1394if_shutdown_exit,
138 HCI1394_TNF_HAL_STACK, "");
139 }
140
141
142 /*
143 * hci1394_s1394if_phy()
144 * write a phy packet out to the 1394 bus. A phy packet consists of one
145 * quadlet of data.
146 */
147 static int
hci1394_s1394if_phy(void * hal_private,cmd1394_cmd_t * cmd_id,h1394_cmd_priv_t * cmd_private,int * result)148 hci1394_s1394if_phy(void *hal_private, cmd1394_cmd_t *cmd_id,
149 h1394_cmd_priv_t *cmd_private, int *result)
150 {
151 hci1394_state_t *soft_state;
152 int status;
153
154
155 ASSERT(hal_private != NULL);
156 TNF_PROBE_0_DEBUG(hci1394_s1394if_phy_enter,
157 HCI1394_TNF_HAL_STACK, "");
158
159 soft_state = (hci1394_state_t *)hal_private;
160
161 /* make sure we are not in a bus reset or shutdown */
162 if (hci1394_state(&soft_state->drvinfo) != HCI1394_NORMAL) {
163 if (hci1394_state(&soft_state->drvinfo) == HCI1394_BUS_RESET) {
164 *result = H1394_STATUS_INVALID_BUSGEN;
165 } else {
166 *result = H1394_STATUS_INTERNAL_ERROR;
167 }
168 TNF_PROBE_0(hci1394_state_fail, HCI1394_TNF_HAL_ERROR, "");
169 TNF_PROBE_0_DEBUG(hci1394_s1394if_phy_exit,
170 HCI1394_TNF_HAL_STACK, "");
171 return (DDI_FAILURE);
172 }
173
174 status = hci1394_async_phy(soft_state->async, cmd_id, cmd_private,
175 result);
176 if (status != DDI_SUCCESS) {
177 TNF_PROBE_0(hci1394_async_phy_fail, HCI1394_TNF_HAL_ERROR, "");
178 TNF_PROBE_0_DEBUG(hci1394_s1394if_phy_exit,
179 HCI1394_TNF_HAL_STACK, "");
180 return (DDI_FAILURE);
181 }
182
183 TNF_PROBE_0_DEBUG(hci1394_s1394if_phy_exit,
184 HCI1394_TNF_HAL_STACK, "");
185
186 return (DDI_SUCCESS);
187 }
188
189
190 /*
191 * hci1394_s1394if_write()
192 * Perform a 1394 write operation. This can be either a quadlet or block
193 * write.
194 */
195 static int
hci1394_s1394if_write(void * hal_private,cmd1394_cmd_t * cmd_id,h1394_cmd_priv_t * cmd_private,int * result)196 hci1394_s1394if_write(void *hal_private, cmd1394_cmd_t *cmd_id,
197 h1394_cmd_priv_t *cmd_private, int *result)
198 {
199 hci1394_state_t *soft_state;
200 int status;
201
202
203 ASSERT(hal_private != NULL);
204 TNF_PROBE_0_DEBUG(hci1394_s1394if_write_enter,
205 HCI1394_TNF_HAL_STACK, "");
206
207 soft_state = (hci1394_state_t *)hal_private;
208
209 /* make sure we are not in a bus reset or shutdown */
210 if (hci1394_state(&soft_state->drvinfo) != HCI1394_NORMAL) {
211 if (hci1394_state(&soft_state->drvinfo) == HCI1394_BUS_RESET) {
212 *result = H1394_STATUS_INVALID_BUSGEN;
213 } else {
214 *result = H1394_STATUS_INTERNAL_ERROR;
215 }
216 TNF_PROBE_0(hci1394_state_fail, HCI1394_TNF_HAL_ERROR, "");
217 TNF_PROBE_0_DEBUG(hci1394_s1394if_write_exit,
218 HCI1394_TNF_HAL_STACK, "");
219 return (DDI_FAILURE);
220 }
221
222 status = hci1394_async_write(soft_state->async, cmd_id, cmd_private,
223 result);
224 if (status != DDI_SUCCESS) {
225 TNF_PROBE_0(hci1394_async_write_fail, HCI1394_TNF_HAL_ERROR,
226 "");
227 TNF_PROBE_0_DEBUG(hci1394_s1394if_write_exit,
228 HCI1394_TNF_HAL_STACK, "");
229 return (DDI_FAILURE);
230 }
231
232 TNF_PROBE_0_DEBUG(hci1394_s1394if_write_exit,
233 HCI1394_TNF_HAL_STACK, "");
234
235 return (DDI_SUCCESS);
236 }
237
238
239 /*
240 * hci1394_s1394if_read()
241 * Perform a 1394 read operation. This can be either a quadlet or block
242 * read.
243 */
244 static int
hci1394_s1394if_read(void * hal_private,cmd1394_cmd_t * cmd_id,h1394_cmd_priv_t * cmd_private,int * result)245 hci1394_s1394if_read(void *hal_private, cmd1394_cmd_t *cmd_id,
246 h1394_cmd_priv_t *cmd_private, int *result)
247 {
248 hci1394_state_t *soft_state;
249 int status;
250
251
252 ASSERT(hal_private != NULL);
253 TNF_PROBE_0_DEBUG(hci1394_s1394if_read_enter,
254 HCI1394_TNF_HAL_STACK, "");
255
256 soft_state = (hci1394_state_t *)hal_private;
257
258 /* make sure we are not in a bus reset or shutdown */
259 if (hci1394_state(&soft_state->drvinfo) != HCI1394_NORMAL) {
260 if (hci1394_state(&soft_state->drvinfo) == HCI1394_BUS_RESET) {
261 *result = H1394_STATUS_INVALID_BUSGEN;
262 } else {
263 *result = H1394_STATUS_INTERNAL_ERROR;
264 }
265 TNF_PROBE_0(hci1394_state_fail, HCI1394_TNF_HAL_ERROR, "");
266 TNF_PROBE_0_DEBUG(hci1394_s1394if_read_exit,
267 HCI1394_TNF_HAL_STACK, "");
268 return (DDI_FAILURE);
269 }
270
271 status = hci1394_async_read(soft_state->async, cmd_id, cmd_private,
272 result);
273 if (status != DDI_SUCCESS) {
274 TNF_PROBE_0(hci1394_async_read_fail, HCI1394_TNF_HAL_ERROR, "");
275 TNF_PROBE_0_DEBUG(hci1394_s1394if_read_exit,
276 HCI1394_TNF_HAL_STACK, "");
277 return (DDI_FAILURE);
278 }
279
280 TNF_PROBE_0_DEBUG(hci1394_s1394if_read_exit,
281 HCI1394_TNF_HAL_STACK, "");
282
283 return (DDI_SUCCESS);
284 }
285
286
287 /*
288 * hci1394_s1394if_lock()
289 * Perform a 1394/1212 lock operation. This can be one of the following lock
290 * operations: (CMD1394_LOCK_MASK_SWAP, CMD1394_LOCK_COMPARE_SWAP
291 * CMD1394_LOCK_FETCH_ADD, CMD1394_LOCK_LITTLE_ADD, CMD1394_LOCK_BOUNDED_ADD
292 * CMD1394_LOCK_WRAP_ADD)
293 */
294 static int
hci1394_s1394if_lock(void * hal_private,cmd1394_cmd_t * cmd_id,h1394_cmd_priv_t * cmd_private,int * result)295 hci1394_s1394if_lock(void *hal_private, cmd1394_cmd_t *cmd_id,
296 h1394_cmd_priv_t *cmd_private, int *result)
297 {
298 hci1394_state_t *soft_state;
299 int status;
300
301
302 ASSERT(hal_private != NULL);
303 TNF_PROBE_0_DEBUG(hci1394_s1394if_lock_enter,
304 HCI1394_TNF_HAL_STACK, "");
305
306 soft_state = (hci1394_state_t *)hal_private;
307
308 /* make sure we are not in a bus reset or shutdown */
309 if (hci1394_state(&soft_state->drvinfo) != HCI1394_NORMAL) {
310 if (hci1394_state(&soft_state->drvinfo) == HCI1394_BUS_RESET) {
311 *result = H1394_STATUS_INVALID_BUSGEN;
312 } else {
313 *result = H1394_STATUS_INTERNAL_ERROR;
314 }
315 TNF_PROBE_0(hci1394_state_fail, HCI1394_TNF_HAL_ERROR, "");
316 TNF_PROBE_0_DEBUG(hci1394_s1394if_lock_exit,
317 HCI1394_TNF_HAL_STACK, "");
318 return (DDI_FAILURE);
319 }
320
321 status = hci1394_async_lock(soft_state->async, cmd_id, cmd_private,
322 result);
323 if (status != DDI_SUCCESS) {
324 TNF_PROBE_0(hci1394_async_lock_fail, HCI1394_TNF_HAL_ERROR, "");
325 TNF_PROBE_0_DEBUG(hci1394_s1394if_lock_exit,
326 HCI1394_TNF_HAL_STACK, "");
327 return (DDI_FAILURE);
328 }
329
330 TNF_PROBE_0_DEBUG(hci1394_s1394if_lock_exit,
331 HCI1394_TNF_HAL_STACK, "");
332
333 return (DDI_SUCCESS);
334 }
335
336
337 /*
338 * hci1394_s1394if_write_response()
339 * Send a response to a write request received off of the 1394 bus. This
340 * could have been with a quadlet or block write request.
341 */
342 static int
hci1394_s1394if_write_response(void * hal_private,cmd1394_cmd_t * cmd_id,h1394_cmd_priv_t * cmd_private,int * result)343 hci1394_s1394if_write_response(void *hal_private, cmd1394_cmd_t *cmd_id,
344 h1394_cmd_priv_t *cmd_private, int *result)
345 {
346 hci1394_state_t *soft_state;
347 int status;
348
349
350 ASSERT(hal_private != NULL);
351 TNF_PROBE_0_DEBUG(hci1394_s1394if_write_response_enter,
352 HCI1394_TNF_HAL_STACK, "");
353
354 soft_state = (hci1394_state_t *)hal_private;
355
356 /* make sure we are not in a bus reset or shutdown */
357 if (hci1394_state(&soft_state->drvinfo) != HCI1394_NORMAL) {
358 if (hci1394_state(&soft_state->drvinfo) == HCI1394_BUS_RESET) {
359 *result = H1394_STATUS_INVALID_BUSGEN;
360 } else {
361 *result = H1394_STATUS_INTERNAL_ERROR;
362 }
363 TNF_PROBE_0(hci1394_state_fail, HCI1394_TNF_HAL_ERROR, "");
364 TNF_PROBE_0_DEBUG(hci1394_s1394if_write_response_exit,
365 HCI1394_TNF_HAL_STACK, "");
366 return (DDI_FAILURE);
367 }
368
369 status = hci1394_async_write_response(soft_state->async, cmd_id,
370 cmd_private, result);
371 if (status != DDI_SUCCESS) {
372 TNF_PROBE_0(hci1394_async_write_response_fail,
373 HCI1394_TNF_HAL_ERROR, "");
374 TNF_PROBE_0_DEBUG(hci1394_s1394if_write_response_exit,
375 HCI1394_TNF_HAL_STACK, "");
376 return (DDI_FAILURE);
377 }
378
379 TNF_PROBE_0_DEBUG(hci1394_s1394if_write_response_exit,
380 HCI1394_TNF_HAL_STACK, "");
381
382 return (DDI_SUCCESS);
383 }
384
385
386 /*
387 * hci1394_s1394if_read_response()
388 * Send a response to a read request received off of the 1394 bus. This
389 * could have been with a quadlet or block read request.
390 */
391 static int
hci1394_s1394if_read_response(void * hal_private,cmd1394_cmd_t * cmd_id,h1394_cmd_priv_t * cmd_private,int * result)392 hci1394_s1394if_read_response(void *hal_private, cmd1394_cmd_t *cmd_id,
393 h1394_cmd_priv_t *cmd_private, int *result)
394 {
395 hci1394_state_t *soft_state;
396 int status;
397
398
399 ASSERT(hal_private != NULL);
400 TNF_PROBE_0_DEBUG(hci1394_s1394if_read_response_enter,
401 HCI1394_TNF_HAL_STACK, "");
402
403 soft_state = (hci1394_state_t *)hal_private;
404
405 /* make sure we are not in a bus reset or shutdown */
406 if (hci1394_state(&soft_state->drvinfo) != HCI1394_NORMAL) {
407 if (hci1394_state(&soft_state->drvinfo) == HCI1394_BUS_RESET) {
408 *result = H1394_STATUS_INVALID_BUSGEN;
409 } else {
410 *result = H1394_STATUS_INTERNAL_ERROR;
411 }
412 TNF_PROBE_0(hci1394_state_fail, HCI1394_TNF_HAL_ERROR, "");
413 TNF_PROBE_0_DEBUG(hci1394_s1394if_read_response_exit,
414 HCI1394_TNF_HAL_STACK, "");
415 return (DDI_FAILURE);
416 }
417
418 status = hci1394_async_read_response(soft_state->async, cmd_id,
419 cmd_private, result);
420 if (status != DDI_SUCCESS) {
421 TNF_PROBE_0(hci1394_async_read_response_fail,
422 HCI1394_TNF_HAL_ERROR, "");
423 TNF_PROBE_0_DEBUG(hci1394_s1394if_read_response_exit,
424 HCI1394_TNF_HAL_STACK, "");
425 return (DDI_FAILURE);
426 }
427
428 TNF_PROBE_0_DEBUG(hci1394_s1394if_read_response_exit,
429 HCI1394_TNF_HAL_STACK, "");
430
431 return (DDI_SUCCESS);
432 }
433
434
435 /*
436 * hci1394_s1394if_lock_response()
437 * Send a response to a lock request received off of the 1394 bus. This
438 * could have been one of the following lock operations:
439 * (CMD1394_LOCK_MASK_SWAP, CMD1394_LOCK_COMPARE_SWAP CMD1394_LOCK_FETCH_ADD,
440 * CMD1394_LOCK_LITTLE_ADD, CMD1394_LOCK_BOUNDED_ADD, CMD1394_LOCK_WRAP_ADD)
441 */
442 static int
hci1394_s1394if_lock_response(void * hal_private,cmd1394_cmd_t * cmd_id,h1394_cmd_priv_t * cmd_private,int * result)443 hci1394_s1394if_lock_response(void *hal_private, cmd1394_cmd_t *cmd_id,
444 h1394_cmd_priv_t *cmd_private, int *result)
445 {
446 hci1394_state_t *soft_state;
447 int status;
448
449
450 ASSERT(hal_private != NULL);
451 TNF_PROBE_0_DEBUG(hci1394_s1394if_lock_response_enter,
452 HCI1394_TNF_HAL_STACK, "");
453
454 soft_state = (hci1394_state_t *)hal_private;
455
456 /* make sure we are not in a bus reset or shutdown */
457 if (hci1394_state(&soft_state->drvinfo) != HCI1394_NORMAL) {
458 if (hci1394_state(&soft_state->drvinfo) == HCI1394_BUS_RESET) {
459 *result = H1394_STATUS_INVALID_BUSGEN;
460 } else {
461 *result = H1394_STATUS_INTERNAL_ERROR;
462 }
463 TNF_PROBE_0(hci1394_state_fail, HCI1394_TNF_HAL_ERROR, "");
464 TNF_PROBE_0_DEBUG(hci1394_s1394if_lock_response_exit,
465 HCI1394_TNF_HAL_STACK, "");
466 return (DDI_FAILURE);
467 }
468
469 status = hci1394_async_lock_response(soft_state->async, cmd_id,
470 cmd_private, result);
471 if (status != DDI_SUCCESS) {
472 TNF_PROBE_0(hci1394_async_lock_response_fail,
473 HCI1394_TNF_HAL_ERROR, "");
474 TNF_PROBE_0_DEBUG(hci1394_s1394if_lock_response_exit,
475 HCI1394_TNF_HAL_STACK, "");
476 return (DDI_FAILURE);
477 }
478
479 TNF_PROBE_0_DEBUG(hci1394_s1394if_lock_response_exit,
480 HCI1394_TNF_HAL_STACK, "");
481
482 return (DDI_SUCCESS);
483 }
484
485
486 /*
487 * hci1394_s1394if_response_complete()
488 * This notifies the HAL that the services layer and target driver are done
489 * with a command that was received off of the 1394 bus. This will usually
490 * be called after the response to the command has been command_complete'd.
491 * The HAL is free to re-use the command or free up the memory from this
492 * command after this call has returned. This should only be called for
493 * ARREQ's.
494 */
495 static void
hci1394_s1394if_response_complete(void * hal_private,cmd1394_cmd_t * cmd_id,h1394_cmd_priv_t * cmd_private)496 hci1394_s1394if_response_complete(void *hal_private, cmd1394_cmd_t *cmd_id,
497 h1394_cmd_priv_t *cmd_private)
498 {
499 hci1394_state_t *soft_state;
500
501 ASSERT(hal_private != NULL);
502 TNF_PROBE_0_DEBUG(hci1394_s1394if_response_complete_enter,
503 HCI1394_TNF_HAL_STACK, "");
504 soft_state = (hci1394_state_t *)hal_private;
505 hci1394_async_response_complete(soft_state->async, cmd_id, cmd_private);
506 TNF_PROBE_0_DEBUG(hci1394_s1394if_response_complete_exit,
507 HCI1394_TNF_HAL_STACK, "");
508 }
509
510
511 /*
512 * hci1394_s1394if_reset_bus()
513 * This routine resets the 1394 bus. It performs a "long" bus reset. It
514 * should work on all OpenHCI adapters.
515 */
516 static int
hci1394_s1394if_reset_bus(void * hal_private)517 hci1394_s1394if_reset_bus(void *hal_private)
518 {
519 hci1394_state_t *soft_state;
520 int status;
521
522
523 ASSERT(hal_private != NULL);
524 TNF_PROBE_0_DEBUG(hci1394_s1394if_reset_bus_enter,
525 HCI1394_TNF_HAL_STACK, "");
526
527 soft_state = (hci1394_state_t *)hal_private;
528
529 /* make sure we are not shutdown */
530 if (hci1394_state(&soft_state->drvinfo) == HCI1394_SHUTDOWN) {
531 TNF_PROBE_0(hci1394_state_fail, HCI1394_TNF_HAL_ERROR, "");
532 TNF_PROBE_0_DEBUG(hci1394_s1394if_reset_bus_exit,
533 HCI1394_TNF_HAL_STACK, "");
534 return (DDI_FAILURE);
535 }
536
537 status = hci1394_ohci_bus_reset(soft_state->ohci);
538 if (status != DDI_SUCCESS) {
539 TNF_PROBE_0(hci1394_s1394if_reset_bus_fail,
540 HCI1394_TNF_HAL_ERROR, "");
541 TNF_PROBE_0_DEBUG(hci1394_s1394if_reset_bus_exit,
542 HCI1394_TNF_HAL_STACK, "");
543 return (DDI_FAILURE);
544 }
545
546 TNF_PROBE_0_DEBUG(hci1394_s1394if_reset_bus_exit,
547 HCI1394_TNF_HAL_STACK, "");
548
549 return (DDI_SUCCESS);
550 }
551
552
553 /*
554 * hci1394_s1394if_set_contender_bit()
555 * This routine sets up the PHY so that the selfid contender bit will be set
556 * on subsequent bus resets. This routine will fail when we have a 1394-1995
557 * PHY since this PHY does not have a SW controllable contender bit.
558 */
559 static int
hci1394_s1394if_set_contender_bit(void * hal_private)560 hci1394_s1394if_set_contender_bit(void *hal_private)
561 {
562 hci1394_state_t *soft_state;
563 int status;
564
565
566 ASSERT(hal_private != NULL);
567 TNF_PROBE_0_DEBUG(hci1394_s1394if_set_contender_bit_enter,
568 HCI1394_TNF_HAL_STACK, "");
569
570 soft_state = (hci1394_state_t *)hal_private;
571
572 /* make sure we are not shutdown */
573 if (hci1394_state(&soft_state->drvinfo) == HCI1394_SHUTDOWN) {
574 TNF_PROBE_0(hci1394_state_fail, HCI1394_TNF_HAL_ERROR, "");
575 TNF_PROBE_0_DEBUG(hci1394_s1394if_set_contender_bit_exit,
576 HCI1394_TNF_HAL_STACK, "");
577 return (DDI_FAILURE);
578 }
579
580 if (soft_state->halinfo.phy == H1394_PHY_1995) {
581 TNF_PROBE_0(hci1394_s1394if_set_contender_bit_phyver_fail,
582 HCI1394_TNF_HAL_ERROR, "");
583 TNF_PROBE_0_DEBUG(hci1394_s1394if_set_root_holdoff_bit_exit,
584 HCI1394_TNF_HAL_STACK, "");
585 return (DDI_FAILURE);
586 }
587
588 status = hci1394_ohci_contender_enable(soft_state->ohci);
589 if (status != DDI_SUCCESS) {
590 TNF_PROBE_0(hci1394_s1394if_set_contender_bit_fail,
591 HCI1394_TNF_HAL_ERROR, "");
592 TNF_PROBE_0_DEBUG(hci1394_s1394if_set_contender_bit_exit,
593 HCI1394_TNF_HAL_STACK, "");
594 return (DDI_FAILURE);
595 }
596
597 TNF_PROBE_0_DEBUG(hci1394_s1394if_set_contender_bit_exit,
598 HCI1394_TNF_HAL_STACK, "");
599
600 return (DDI_SUCCESS);
601 }
602
603
604 /*
605 * hci1394_s1394if_set_root_holdoff_bit()
606 * This routine will set the root holdoff bit in the PHY. The Services Layer
607 * should send out a PHY configuration packet first to tell everyone which
608 * node to set the root holdoff bit on. If it is our root holdoff bit we
609 * are setting, the PHY will automatically set it unless we have an old
610 * (1394-1995) PHY. If we have a 1394-1995 PHY, the SL needs to call this
611 * routine after sending the PHY configuration packet. The SL also needs to
612 * call this if they want to perform a long bus reset and have the root
613 * holdoff bit set. We do this so that we do not have to do a read before
614 * the write. A PHY register write has less of a chance of failing.
615 */
616 static int
hci1394_s1394if_set_root_holdoff_bit(void * hal_private)617 hci1394_s1394if_set_root_holdoff_bit(void *hal_private)
618 {
619 hci1394_state_t *soft_state;
620 int status;
621
622
623 ASSERT(hal_private != NULL);
624 TNF_PROBE_0_DEBUG(hci1394_s1394if_set_root_holdoff_bit_enter,
625 HCI1394_TNF_HAL_STACK, "");
626
627 soft_state = (hci1394_state_t *)hal_private;
628
629 /* make sure we are not shutdown */
630 if (hci1394_state(&soft_state->drvinfo) == HCI1394_SHUTDOWN) {
631 TNF_PROBE_0(hci1394_state_fail, HCI1394_TNF_HAL_ERROR, "");
632 TNF_PROBE_0_DEBUG(hci1394_s1394if_set_root_holdoff_bit_exit,
633 HCI1394_TNF_HAL_STACK, "");
634 return (DDI_FAILURE);
635 }
636
637 status = hci1394_ohci_root_holdoff_enable(soft_state->ohci);
638 if (status != DDI_SUCCESS) {
639 TNF_PROBE_0(hci1394_s1394if_set_root_holdoff_bit_fail,
640 HCI1394_TNF_HAL_ERROR, "");
641 TNF_PROBE_0_DEBUG(hci1394_s1394if_set_root_holdoff_bit_exit,
642 HCI1394_TNF_HAL_STACK, "");
643 return (DDI_FAILURE);
644 }
645
646 TNF_PROBE_0_DEBUG(hci1394_s1394if_set_root_holdoff_bit_exit,
647 HCI1394_TNF_HAL_STACK, "");
648
649 return (DDI_SUCCESS);
650 }
651
652
653 /*
654 * hci1394_s1394if_set_gap_count()
655 * This routine will set the gap count bit in the PHY. The Services Layer
656 * should send out a PHY configuration packet first to tell everyone what
657 * gap count to use. Our PHY will automatically set the gap count unless we
658 * have an old (1394-1995) PHY. If we have a 1394-1995 PHY, the SL needs to
659 * call this routine after sending the PHY configuration packet and before
660 * generating a bus reset. The SL also needs to call before the they call to
661 * perform a long bus reset. We do this so that we do not have to do a PHY
662 * read before the write. A PHY register write has less of a chance of
663 * failing.
664 */
665 static int
hci1394_s1394if_set_gap_count(void * hal_private,uint_t gap_count)666 hci1394_s1394if_set_gap_count(void *hal_private, uint_t gap_count)
667 {
668 hci1394_state_t *soft_state;
669 int status;
670
671
672 ASSERT(hal_private != NULL);
673 TNF_PROBE_0_DEBUG(hci1394_s1394if_set_gap_count_enter,
674 HCI1394_TNF_HAL_STACK, "");
675
676 soft_state = (hci1394_state_t *)hal_private;
677
678 /* make sure we are not shutdown */
679 if (hci1394_state(&soft_state->drvinfo) == HCI1394_SHUTDOWN) {
680 TNF_PROBE_0(hci1394_state_fail, HCI1394_TNF_HAL_ERROR, "");
681 TNF_PROBE_0_DEBUG(hci1394_s1394if_set_gap_count_exit,
682 HCI1394_TNF_HAL_STACK, "");
683 return (DDI_FAILURE);
684 }
685
686 status = hci1394_ohci_gap_count_set(soft_state->ohci, gap_count);
687 if (status != DDI_SUCCESS) {
688 TNF_PROBE_0(hci1394_s1394if_set_gap_count_fail,
689 HCI1394_TNF_HAL_ERROR, "");
690 TNF_PROBE_0_DEBUG(hci1394_s1394if_set_gap_count_exit,
691 HCI1394_TNF_HAL_STACK, "");
692 return (DDI_FAILURE);
693 }
694
695 TNF_PROBE_0_DEBUG(hci1394_s1394if_set_gap_count_exit,
696 HCI1394_TNF_HAL_STACK, "");
697
698 return (DDI_SUCCESS);
699 }
700
701
702 /*
703 * hci1394_s1394if_phy_filter_set()
704 * reads/writes to physically mapped memory from devices on the bus are
705 * disabled by default. They can be enabled on a node by node basis. All
706 * physical accesses are disabled every bus reset so they must be re-enabled
707 * every bus reset (This is due to the fact the the node ids change every bus
708 * reset). A 64-bit mask is passed in to enable nodes to be able to rd/wr
709 * physically mapped memory over the 1394 bus. A bit = to 1 enables that
710 * node's physical accesses, a bit = to 0 does nothing (i.e. a bitwise or is
711 * performed). The LSB of the mask (bit 0), maps to node #0, bit #62, maps to
712 * node 62. The MSB (#63) is not used since the can only be 63 nodes
713 * (0 - 62) on the bus.
714 *
715 * hci1394_s1394if_phy_filter_clr() is used to disable access to physical
716 * memory. This is only required if the node had previously been enabled.
717 *
718 * generation is used to verify that we are have not gotten a bus reset since
719 * the mask was built.
720 */
721 static int
hci1394_s1394if_phy_filter_set(void * hal_private,uint64_t mask,uint_t generation)722 hci1394_s1394if_phy_filter_set(void *hal_private,
723 uint64_t mask, uint_t generation)
724 {
725 hci1394_state_t *soft_state;
726 int status;
727
728
729 ASSERT(hal_private != NULL);
730 TNF_PROBE_0_DEBUG(hci1394_s1394if_phy_filter_set_enter,
731 HCI1394_TNF_HAL_STACK, "");
732
733 soft_state = (hci1394_state_t *)hal_private;
734
735 /* make sure we are not shutdown */
736 if (hci1394_state(&soft_state->drvinfo) == HCI1394_SHUTDOWN) {
737 TNF_PROBE_0(hci1394_state_fail, HCI1394_TNF_HAL_ERROR, "");
738 TNF_PROBE_0_DEBUG(hci1394_s1394if_phy_filter_set_exit,
739 HCI1394_TNF_HAL_STACK, "");
740 return (DDI_FAILURE);
741 }
742
743 status = hci1394_ohci_phy_filter_set(soft_state->ohci, mask,
744 generation);
745 if (status != DDI_SUCCESS) {
746 TNF_PROBE_0(hci1394_s1394if_phy_filter_set_fail,
747 HCI1394_TNF_HAL_ERROR, "");
748 TNF_PROBE_0_DEBUG(hci1394_s1394if_phy_filter_set_exit,
749 HCI1394_TNF_HAL_STACK, "");
750 return (DDI_FAILURE);
751 }
752
753 TNF_PROBE_0_DEBUG(hci1394_s1394if_phy_filter_set_exit,
754 HCI1394_TNF_HAL_STACK, "");
755
756 return (DDI_SUCCESS);
757 }
758
759
760 /*
761 * hci1394_s1394if_phy_filter_clr()
762 * reads/writes to physically mapped memory from devices on the bus are
763 * disabled by default. They can be enabled/disabled on a node by node basis.
764 * All physical accesses are disabled every bus reset so they must be
765 * re-enabled every bus reset (This is due to the fact the the node ids
766 * change every bus reset). Only nodes which have been enabled and no longer
767 * need access to physical memory need to be disabled.
768 *
769 * A 64-bit mask is passed in to disable nodes from being able to rd/wr
770 * physically mapped memory over the 1394 bus. A bit = to 1 disables that
771 * node's physical accesses, a bit = to 0 does nothing (i.e. a bitwise or is
772 * performed). The LSB of the mask (bit 0), maps to node #0, bit #62, maps to
773 * node 62. The MSB (#63) is not used since there can only be 63 nodes
774 * (0 - 62) on the bus.
775 *
776 * hci1394_s1394if_phy_filter_set() is used to enable access to physical
777 * memory.
778 *
779 * generation is used to verify that we are have not gotten a bus reset since
780 * the mask was build.
781 */
782 static int
hci1394_s1394if_phy_filter_clr(void * hal_private,uint64_t mask,uint_t generation)783 hci1394_s1394if_phy_filter_clr(void *hal_private,
784 uint64_t mask, uint_t generation)
785 {
786 hci1394_state_t *soft_state;
787 int status;
788
789
790 ASSERT(hal_private != NULL);
791 TNF_PROBE_0_DEBUG(hci1394_s1394if_phy_filter_clr_enter,
792 HCI1394_TNF_HAL_STACK, "");
793
794 soft_state = (hci1394_state_t *)hal_private;
795
796 /* make sure we are not shutdown */
797 if (hci1394_state(&soft_state->drvinfo) == HCI1394_SHUTDOWN) {
798 TNF_PROBE_0(hci1394_state_fail, HCI1394_TNF_HAL_ERROR, "");
799 TNF_PROBE_0_DEBUG(hci1394_s1394if_phy_filter_clr_exit,
800 HCI1394_TNF_HAL_STACK, "");
801 return (DDI_FAILURE);
802 }
803
804 status = hci1394_ohci_phy_filter_clr(soft_state->ohci, mask,
805 generation);
806 if (status != DDI_SUCCESS) {
807 TNF_PROBE_0(hci1394_s1394if_phy_filter_clr_fail,
808 HCI1394_TNF_HAL_ERROR, "");
809 TNF_PROBE_0_DEBUG(hci1394_s1394if_phy_filter_clr_exit,
810 HCI1394_TNF_HAL_STACK, "");
811 return (DDI_FAILURE);
812 }
813
814 TNF_PROBE_0_DEBUG(hci1394_s1394if_phy_filter_clr_exit,
815 HCI1394_TNF_HAL_STACK, "");
816
817 return (DDI_SUCCESS);
818 }
819
820
821 /*
822 * hci1394_s1394if_short_bus_reset()
823 * This routine resets the 1394 bus. It performs a "short" bus reset. It
824 * will only work on adapters with a 1394A or later PHY. Calling this routine
825 * when we have a 1394-1995 PHY is an error.
826 */
827 static int
hci1394_s1394if_short_bus_reset(void * hal_private)828 hci1394_s1394if_short_bus_reset(void *hal_private)
829 {
830 hci1394_state_t *soft_state;
831 int status;
832
833
834 ASSERT(hal_private != NULL);
835 TNF_PROBE_0_DEBUG(hci1394_s1394if_short_bus_reset_enter,
836 HCI1394_TNF_HAL_STACK, "");
837
838 soft_state = (hci1394_state_t *)hal_private;
839
840 /* make sure we are not shutdown */
841 if (hci1394_state(&soft_state->drvinfo) == HCI1394_SHUTDOWN) {
842 TNF_PROBE_0(hci1394_state_fail, HCI1394_TNF_HAL_ERROR, "");
843 TNF_PROBE_0_DEBUG(hci1394_s1394if_short_bus_reset_exit,
844 HCI1394_TNF_HAL_STACK, "");
845 return (DDI_FAILURE);
846 }
847
848 if (soft_state->halinfo.phy == H1394_PHY_1995) {
849 TNF_PROBE_0(hci1394_s1394if_short_bus_reset_phyver_fail,
850 HCI1394_TNF_HAL_ERROR, "");
851 TNF_PROBE_0_DEBUG(hci1394_s1394if_set_root_holdoff_bit_exit,
852 HCI1394_TNF_HAL_STACK, "");
853 return (DDI_FAILURE);
854 }
855
856 status = hci1394_ohci_bus_reset_short(soft_state->ohci);
857 if (status != DDI_SUCCESS) {
858 TNF_PROBE_0(hci1394_s1394if_short_bus_reset_fail,
859 HCI1394_TNF_HAL_ERROR, "");
860 TNF_PROBE_0_DEBUG(hci1394_s1394if_short_bus_reset_exit,
861 HCI1394_TNF_HAL_STACK, "");
862 return (DDI_FAILURE);
863 }
864
865 TNF_PROBE_0_DEBUG(hci1394_s1394if_short_bus_reset_exit,
866 HCI1394_TNF_HAL_STACK, "");
867
868 return (DDI_SUCCESS);
869 }
870
871
872 /*
873 * hci1394_s1394if_update_config_rom()
874 * This routine updates the configuration ROM. It copies "quadlet_count"
875 * 32-bit words from "local_buf" to the config ROM starting at the first
876 * location in config ROM. This routine is meant to update the entire config
877 * ROM and not meant for a partial update.
878 */
879 static int
hci1394_s1394if_update_config_rom(void * hal_private,void * local_buf,uint_t quadlet_count)880 hci1394_s1394if_update_config_rom(void *hal_private,
881 void *local_buf, uint_t quadlet_count)
882 {
883 hci1394_state_t *soft_state;
884
885
886 ASSERT(hal_private != NULL);
887 ASSERT(local_buf != NULL);
888 TNF_PROBE_0_DEBUG(hci1394_s1394if_update_config_rom_enter,
889 HCI1394_TNF_HAL_STACK, "");
890
891 soft_state = (hci1394_state_t *)hal_private;
892
893 /* make sure we are not shutdown */
894 if (hci1394_state(&soft_state->drvinfo) == HCI1394_SHUTDOWN) {
895 TNF_PROBE_0(hci1394_state_fail, HCI1394_TNF_HAL_ERROR, "");
896 TNF_PROBE_0_DEBUG(hci1394_s1394if_update_config_rom_exit,
897 HCI1394_TNF_HAL_STACK, "");
898 return (DDI_FAILURE);
899 }
900
901 hci1394_ohci_cfgrom_update(soft_state->ohci, local_buf, quadlet_count);
902
903 TNF_PROBE_0_DEBUG(hci1394_s1394if_update_config_rom_exit,
904 HCI1394_TNF_HAL_STACK, "");
905
906 return (DDI_SUCCESS);
907 }
908
909
910 /*
911 * hci1394_s1394if_csr_read()
912 * CSR register read interface
913 * For more information on CSR registers, see
914 * IEEE 1212
915 * IEEE 1394-1995
916 * section 8.3.2
917 * IEEE P1394A Draft 3.0
918 * sections 10.32,10.33
919 */
920 static int
hci1394_s1394if_csr_read(void * hal_private,uint_t offset,uint32_t * data)921 hci1394_s1394if_csr_read(void *hal_private, uint_t offset, uint32_t *data)
922 {
923 hci1394_state_t *soft_state;
924 int status;
925
926
927 ASSERT(hal_private != NULL);
928 ASSERT(data != NULL);
929 TNF_PROBE_0_DEBUG(hci1394_s1394if_csr_read_enter,
930 HCI1394_TNF_HAL_STACK, "");
931
932 soft_state = (hci1394_state_t *)hal_private;
933
934 /* make sure we are not shutdown */
935 if (hci1394_state(&soft_state->drvinfo) == HCI1394_SHUTDOWN) {
936 TNF_PROBE_0(hci1394_state_fail, HCI1394_TNF_HAL_ERROR, "");
937 TNF_PROBE_0_DEBUG(hci1394_s1394if_csr_read_exit,
938 HCI1394_TNF_HAL_STACK, "");
939 return (DDI_FAILURE);
940 }
941
942 switch (offset) {
943 case CSR_STATE_CLEAR:
944 hci1394_csr_state_get(soft_state->csr, data);
945 status = DDI_SUCCESS;
946 break;
947 case CSR_STATE_SET:
948 /* Write Only Register */
949 status = DDI_FAILURE;
950 break;
951 case CSR_NODE_IDS:
952 hci1394_ohci_nodeid_get(soft_state->ohci, data);
953 status = DDI_SUCCESS;
954 break;
955 case CSR_RESET_START:
956 /* Not supported */
957 status = DDI_FAILURE;
958 break;
959 case CSR_SPLIT_TIMEOUT_HI:
960 hci1394_csr_split_timeout_hi_get(soft_state->csr, data);
961 status = DDI_SUCCESS;
962 break;
963 case CSR_SPLIT_TIMEOUT_LO:
964 hci1394_csr_split_timeout_lo_get(soft_state->csr, data);
965 status = DDI_SUCCESS;
966 break;
967 case CSR_CYCLE_TIME:
968 /* CYCLE_TIME is implemented in HW */
969 hci1394_ohci_cycletime_get(soft_state->ohci, data);
970 status = DDI_SUCCESS;
971 break;
972 case CSR_BUS_TIME:
973 /* BUS_TIME is implemented in the hci1394_ohci_* SW */
974 hci1394_ohci_bustime_get(soft_state->ohci, data);
975 status = DDI_SUCCESS;
976 break;
977 case CSR_BUSY_TIMEOUT:
978 hci1394_ohci_atreq_retries_get(soft_state->ohci, data);
979 status = DDI_SUCCESS;
980 break;
981 case CSR_BUS_MANAGER_ID:
982 /* BUS_MANAGER_ID is implemented in HW */
983 status = hci1394_ohci_csr_read(soft_state->ohci, 0, data);
984 break;
985 case CSR_BANDWIDTH_AVAILABLE:
986 /* BANDWIDTH_AVAILABLE is implemented in HW */
987 status = hci1394_ohci_csr_read(soft_state->ohci, 1, data);
988 break;
989 case CSR_CHANNELS_AVAILABLE_HI:
990 /* CHANNELS_AVAILABLE_HI is implemented in HW */
991 status = hci1394_ohci_csr_read(soft_state->ohci, 2, data);
992 break;
993 case CSR_CHANNELS_AVAILABLE_LO:
994 /* CHANNELS_AVAILABLE_LO is implemented in HW */
995 status = hci1394_ohci_csr_read(soft_state->ohci, 3, data);
996 break;
997 default:
998 status = DDI_FAILURE;
999 break;
1000 }
1001
1002 if (status != DDI_SUCCESS) {
1003 TNF_PROBE_1(hci1394_s1394if_csr_read_fail,
1004 HCI1394_TNF_HAL_ERROR, "", tnf_uint, csr_address, offset);
1005 }
1006
1007 TNF_PROBE_0_DEBUG(hci1394_s1394if_csr_read_exit,
1008 HCI1394_TNF_HAL_STACK, "");
1009
1010 return (status);
1011 }
1012
1013
1014 /*
1015 * hci1394_s1394if_csr_write()
1016 * CSR register write interface
1017 * For more information on CSR registers, see
1018 * IEEE 1212
1019 * IEEE 1394-1995
1020 * section 8.3.2
1021 * IEEE P1394A Draft 3.0
1022 * sections 10.32,10.33
1023 */
1024 static int
hci1394_s1394if_csr_write(void * hal_private,uint_t offset,uint32_t data)1025 hci1394_s1394if_csr_write(void *hal_private, uint_t offset, uint32_t data)
1026 {
1027 hci1394_state_t *soft_state;
1028 int status;
1029
1030
1031 ASSERT(hal_private != NULL);
1032 TNF_PROBE_0_DEBUG(hci1394_s1394if_csr_write_enter,
1033 HCI1394_TNF_HAL_STACK, "");
1034
1035 soft_state = (hci1394_state_t *)hal_private;
1036
1037 /* make sure we are not shutdown */
1038 if (hci1394_state(&soft_state->drvinfo) == HCI1394_SHUTDOWN) {
1039 TNF_PROBE_0(hci1394_state_fail, HCI1394_TNF_HAL_ERROR, "");
1040 TNF_PROBE_0_DEBUG(hci1394_s1394if_csr_write_exit,
1041 HCI1394_TNF_HAL_STACK, "");
1042 return (DDI_FAILURE);
1043 }
1044
1045 switch (offset) {
1046 case CSR_STATE_CLEAR:
1047 hci1394_csr_state_bclr(soft_state->csr, data);
1048 status = DDI_SUCCESS;
1049 break;
1050 case CSR_STATE_SET:
1051 hci1394_csr_state_bset(soft_state->csr, data);
1052 status = DDI_SUCCESS;
1053 break;
1054 case CSR_NODE_IDS:
1055 hci1394_ohci_nodeid_set(soft_state->ohci, data);
1056 status = DDI_SUCCESS;
1057 break;
1058 case CSR_RESET_START:
1059 /* Not supported */
1060 status = DDI_FAILURE;
1061 break;
1062
1063 /*
1064 * there is a race condition when updating the split timeout
1065 * due to the nature of the interface. (i.e. having a separate
1066 * hi an lo register)
1067 */
1068 case CSR_SPLIT_TIMEOUT_HI:
1069 hci1394_csr_split_timeout_hi_set(soft_state->csr, data);
1070 /*
1071 * update the pending list timeout value. The split timeout
1072 * is stored in 1394 bus cycles and the timeout is specified in
1073 * nS. Therefore, we need to convert the split timeout into nS.
1074 */
1075 hci1394_async_pending_timeout_update(soft_state->async,
1076 OHCI_BUS_CYCLE_TO_nS(hci1394_csr_split_timeout_get(
1077 soft_state->csr)));
1078 status = DDI_SUCCESS;
1079 break;
1080 case CSR_SPLIT_TIMEOUT_LO:
1081 hci1394_csr_split_timeout_lo_set(soft_state->csr, data);
1082 /*
1083 * update the pending list timeout value. The split timeout
1084 * is stored in 1394 bus cycles and the timeout is specified in
1085 * nS. Therefore, we need to convert the split timeout into nS.
1086 */
1087 hci1394_async_pending_timeout_update(soft_state->async,
1088 OHCI_BUS_CYCLE_TO_nS(hci1394_csr_split_timeout_get(
1089 soft_state->csr)));
1090 status = DDI_SUCCESS;
1091 break;
1092
1093 case CSR_CYCLE_TIME:
1094 hci1394_ohci_cycletime_set(soft_state->ohci, data);
1095 status = DDI_SUCCESS;
1096 break;
1097 case CSR_BUS_TIME:
1098 hci1394_ohci_bustime_set(soft_state->ohci, data);
1099 status = DDI_SUCCESS;
1100 break;
1101 case CSR_BUSY_TIMEOUT:
1102 hci1394_ohci_atreq_retries_set(soft_state->ohci, data);
1103 status = DDI_SUCCESS;
1104 break;
1105 case CSR_BUS_MANAGER_ID:
1106 /* Invalid access, only read/cswap32 allowed */
1107 status = DDI_FAILURE;
1108 break;
1109 case CSR_BANDWIDTH_AVAILABLE:
1110 /* Invalid access, only read/cswap32 allowed */
1111 status = DDI_FAILURE;
1112 break;
1113 case CSR_CHANNELS_AVAILABLE_HI:
1114 /* Invalid access, only read/cswap32 allowed */
1115 status = DDI_FAILURE;
1116 break;
1117 case CSR_CHANNELS_AVAILABLE_LO:
1118 /* Invalid access, only read/cswap32 allowed */
1119 status = DDI_FAILURE;
1120 break;
1121 default:
1122 status = DDI_FAILURE;
1123 break;
1124 }
1125
1126 if (status != DDI_SUCCESS) {
1127 TNF_PROBE_1(hci1394_s1394if_csr_write_fail,
1128 HCI1394_TNF_HAL_ERROR, "", tnf_uint, csr_address, offset);
1129 }
1130
1131 TNF_PROBE_0_DEBUG(hci1394_s1394if_csr_write_exit,
1132 HCI1394_TNF_HAL_STACK, "");
1133
1134 return (status);
1135 }
1136
1137
1138 /*
1139 * hci1394_s1394if_csr_cswap32()
1140 * CSR register cswap32 interface
1141 * For more information on CSR registers, see
1142 * IEEE 1212
1143 * IEEE 1394-1995
1144 * section 8.3.2
1145 * IEEE P1394A Draft 3.0
1146 * sections 10.32,10.33
1147 */
1148 static int
hci1394_s1394if_csr_cswap32(void * hal_private,uint_t generation,uint_t offset,uint32_t compare,uint32_t swap,uint32_t * old)1149 hci1394_s1394if_csr_cswap32(void *hal_private, uint_t generation, uint_t offset,
1150 uint32_t compare, uint32_t swap, uint32_t *old)
1151 {
1152 hci1394_state_t *soft_state;
1153 int status;
1154
1155
1156 ASSERT(hal_private != NULL);
1157 ASSERT(old != NULL);
1158 TNF_PROBE_0_DEBUG(hci1394_s1394if_csr_cswap32_enter,
1159 HCI1394_TNF_HAL_STACK, "");
1160
1161 soft_state = (hci1394_state_t *)hal_private;
1162
1163 /* make sure we are not shutdown */
1164 if (hci1394_state(&soft_state->drvinfo) == HCI1394_SHUTDOWN) {
1165 TNF_PROBE_0(hci1394_state_fail, HCI1394_TNF_HAL_ERROR, "");
1166 TNF_PROBE_0_DEBUG(hci1394_s1394if_csr_cswap32_exit,
1167 HCI1394_TNF_HAL_STACK, "");
1168 return (DDI_FAILURE);
1169 }
1170
1171 switch (offset) {
1172 case CSR_STATE_CLEAR:
1173 /* Invalid access, only read/write allowed */
1174 status = DDI_FAILURE;
1175 break;
1176 case CSR_STATE_SET:
1177 /* Invalid access, only write allowed */
1178 status = DDI_FAILURE;
1179 break;
1180 case CSR_NODE_IDS:
1181 /* Invalid access, only read/write allowed */
1182 status = DDI_FAILURE;
1183 break;
1184 case CSR_RESET_START:
1185 /* Invalid access, only read/write allowed */
1186 status = DDI_FAILURE;
1187 break;
1188 case CSR_SPLIT_TIMEOUT_HI:
1189 /* Invalid access, only read/write allowed */
1190 status = DDI_FAILURE;
1191 break;
1192 case CSR_SPLIT_TIMEOUT_LO:
1193 /* Invalid access, only read/write allowed */
1194 status = DDI_FAILURE;
1195 break;
1196 case CSR_CYCLE_TIME:
1197 /* Invalid access, only read/write allowed */
1198 status = DDI_FAILURE;
1199 break;
1200 case CSR_BUS_TIME:
1201 /* Invalid access, only read/write allowed */
1202 status = DDI_FAILURE;
1203 break;
1204 case CSR_BUSY_TIMEOUT:
1205 /* Invalid access, only read/write allowed */
1206 status = DDI_FAILURE;
1207 break;
1208 case CSR_BUS_MANAGER_ID:
1209 /* BUS_MANAGER_ID is implemented in HW */
1210 status = hci1394_ohci_csr_cswap(soft_state->ohci, generation,
1211 OHCI_CSR_SEL_BUS_MGR_ID, compare, swap, old);
1212 break;
1213 case CSR_BANDWIDTH_AVAILABLE:
1214 /* BANDWIDTH_AVAILABLE is implemented in HW */
1215 status = hci1394_ohci_csr_cswap(soft_state->ohci, generation,
1216 OHCI_CSR_SEL_BANDWIDTH_AVAIL, compare, swap, old);
1217 break;
1218 case CSR_CHANNELS_AVAILABLE_HI:
1219 /* CHANNELS_AVAILABLE_HI is implemented in HW */
1220 status = hci1394_ohci_csr_cswap(soft_state->ohci, generation,
1221 OHCI_CSR_SEL_CHANS_AVAIL_HI, compare, swap, old);
1222 break;
1223 case CSR_CHANNELS_AVAILABLE_LO:
1224 /* CHANNELS_AVAILABLE_LO is implemented in HW */
1225 status = hci1394_ohci_csr_cswap(soft_state->ohci, generation,
1226 OHCI_CSR_SEL_CHANS_AVAIL_LO, compare, swap, old);
1227 break;
1228 default:
1229 status = DDI_FAILURE;
1230 break;
1231 }
1232
1233 if (status != DDI_SUCCESS) {
1234 TNF_PROBE_1(hci1394_s1394if_csr_read_fail,
1235 HCI1394_TNF_HAL_ERROR, "", tnf_uint, csr_address, offset);
1236 }
1237
1238 TNF_PROBE_0_DEBUG(hci1394_s1394if_csr_cswap32_exit,
1239 HCI1394_TNF_HAL_STACK, "");
1240
1241 return (status);
1242 }
1243
1244
1245 /*
1246 * hci1394_s1394if_power_state_change()
1247 * Signals that a change in the bus topology has taken place which may affect
1248 * power management.
1249 */
1250 /*ARGSUSED*/
1251 static void
hci1394_s1394if_power_state_change(void * hal_private,h1394_node_pwr_flags_t nodeflags)1252 hci1394_s1394if_power_state_change(void *hal_private,
1253 h1394_node_pwr_flags_t nodeflags)
1254 {
1255 /* not implemented */
1256 }
1257