1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
23 * Use is subject to license terms.
24 */
25
26 /*
27 * hci1394_isr.c
28 * Contains the core interrupt handling logic for the hci1394 driver.
29 * It also contains the routine which sets up the initial interrupt
30 * mask during HW init.
31 */
32
33 #include <sys/conf.h>
34 #include <sys/ddi.h>
35 #include <sys/modctl.h>
36 #include <sys/stat.h>
37 #include <sys/sunddi.h>
38 #include <sys/cmn_err.h>
39
40 #include <sys/1394/h1394.h>
41 #include <sys/1394/adapters/hci1394.h>
42
43
44 static uint_t hci1394_isr(caddr_t parm);
45 static void hci1394_isr_bus_reset(hci1394_state_t *soft_state);
46 static void hci1394_isr_self_id(hci1394_state_t *soft_state);
47 static void hci1394_isr_isoch_ir(hci1394_state_t *soft_state);
48 static void hci1394_isr_isoch_it(hci1394_state_t *soft_state);
49 static void hci1394_isr_atreq_complete(hci1394_state_t *soft_state);
50 static void hci1394_isr_arresp(hci1394_state_t *soft_state);
51 static void hci1394_isr_arreq(hci1394_state_t *soft_state);
52 static void hci1394_isr_atresp_complete(hci1394_state_t *soft_state);
53
54
55 /*
56 * hci1394_isr_init()
57 * Get the iblock_cookie, make sure we are not using a high level interrupt,
58 * register our interrupt service routine.
59 */
60 int
hci1394_isr_init(hci1394_state_t * soft_state)61 hci1394_isr_init(hci1394_state_t *soft_state)
62 {
63 int status;
64
65
66 ASSERT(soft_state != NULL);
67 TNF_PROBE_0_DEBUG(hci1394_isr_init_enter, HCI1394_TNF_HAL_STACK, "");
68
69 /* This driver does not support running at a high level interrupt */
70 status = ddi_intr_hilevel(soft_state->drvinfo.di_dip, 0);
71 if (status != 0) {
72 TNF_PROBE_1(hci1394_isr_init_hli_fail,
73 HCI1394_TNF_HAL_ERROR, "", tnf_string, errmsg,
74 "High Level interrupts not supported");
75 TNF_PROBE_0_DEBUG(hci1394_isr_init_exit,
76 HCI1394_TNF_HAL_STACK, "");
77 return (DDI_FAILURE);
78 }
79
80 /* There should only be 1 1394 interrupt for an OpenHCI adapter */
81 status = ddi_get_iblock_cookie(soft_state->drvinfo.di_dip, 0,
82 &soft_state->drvinfo.di_iblock_cookie);
83 if (status != DDI_SUCCESS) {
84 TNF_PROBE_0(hci1394_isr_init_gic_fail,
85 HCI1394_TNF_HAL_ERROR, "");
86 TNF_PROBE_0_DEBUG(hci1394_isr_init_exit,
87 HCI1394_TNF_HAL_STACK, "");
88 return (DDI_FAILURE);
89 }
90
91 TNF_PROBE_0_DEBUG(hci1394_isr_init_exit, HCI1394_TNF_HAL_STACK, "");
92
93 return (DDI_SUCCESS);
94 }
95
96
97 /*
98 * hci1394_isr_fini()
99 * un-register our interrupt service routine.
100 */
101 /* ARGSUSED */
102 void
hci1394_isr_fini(hci1394_state_t * soft_state)103 hci1394_isr_fini(hci1394_state_t *soft_state)
104 {
105 ASSERT(soft_state != NULL);
106 TNF_PROBE_0_DEBUG(hci1394_isr_fini_enter, HCI1394_TNF_HAL_STACK, "");
107
108 /* nothing to do right now */
109
110 TNF_PROBE_0_DEBUG(hci1394_isr_fini_exit, HCI1394_TNF_HAL_STACK, "");
111 }
112
113
114 /*
115 * hci1394_isr_handler_init()
116 * register our interrupt service routine.
117 */
118 int
hci1394_isr_handler_init(hci1394_state_t * soft_state)119 hci1394_isr_handler_init(hci1394_state_t *soft_state)
120 {
121 int status;
122
123 ASSERT(soft_state != NULL);
124
125 /* Initialize interrupt handler */
126 status = ddi_add_intr(soft_state->drvinfo.di_dip, 0, NULL, NULL,
127 hci1394_isr, (caddr_t)soft_state);
128 if (status != DDI_SUCCESS) {
129 TNF_PROBE_0(hci1394_isr_handler_init_fail,
130 HCI1394_TNF_HAL_ERROR, "");
131 return (DDI_FAILURE);
132 }
133
134 return (DDI_SUCCESS);
135 }
136
137
138 /*
139 * hci1394_isr_handler_fini()
140 * un-register our interrupt service routine.
141 */
142 void
hci1394_isr_handler_fini(hci1394_state_t * soft_state)143 hci1394_isr_handler_fini(hci1394_state_t *soft_state)
144 {
145 ASSERT(soft_state != NULL);
146
147 /* Remove interrupt handler */
148 ddi_remove_intr(soft_state->drvinfo.di_dip, 0,
149 soft_state->drvinfo.di_iblock_cookie);
150 }
151
152
153 /*
154 * hci1394_isr_mask_setup()
155 * Setup the initial interrupt mask for OpenHCI. These are the interrupts
156 * that our interrupt handler is expected to handle.
157 */
158 void
hci1394_isr_mask_setup(hci1394_state_t * soft_state)159 hci1394_isr_mask_setup(hci1394_state_t *soft_state)
160 {
161 ASSERT(soft_state != NULL);
162 TNF_PROBE_0_DEBUG(hci1394_isr_mask_setup_enter, HCI1394_TNF_HAL_STACK,
163 "");
164
165 /* start off with all interrupts cleared/disabled */
166 hci1394_ohci_ir_intr_disable(soft_state->ohci, 0xFFFFFFFF);
167 hci1394_ohci_ir_intr_clear(soft_state->ohci, 0xFFFFFFFF);
168 hci1394_ohci_it_intr_disable(soft_state->ohci, 0xFFFFFFFF);
169 hci1394_ohci_it_intr_clear(soft_state->ohci, 0xFFFFFFFF);
170 hci1394_ohci_intr_disable(soft_state->ohci, 0xFFFFFFFF);
171 hci1394_ohci_intr_clear(soft_state->ohci, 0xFFFFFFFF);
172
173 /* Setup Interrupt Mask Register */
174 hci1394_ohci_intr_enable(soft_state->ohci,
175 (OHCI_INTR_UNRECOVERABLE_ERR | OHCI_INTR_CYC_TOO_LONG |
176 OHCI_INTR_BUS_RESET | OHCI_INTR_SELFID_CMPLT |
177 OHCI_INTR_REQ_TX_CMPLT | OHCI_INTR_RESP_TX_CMPLT |
178 OHCI_INTR_RQPKT | OHCI_INTR_RSPKT | OHCI_INTR_ISOCH_TX |
179 OHCI_INTR_ISOCH_RX | OHCI_INTR_POST_WR_ERR | OHCI_INTR_PHY |
180 OHCI_INTR_LOCK_RESP_ERR));
181
182 TNF_PROBE_0_DEBUG(hci1394_isr_mask_setup_exit, HCI1394_TNF_HAL_STACK,
183 "");
184 }
185
186
187 /*
188 * hci1394_isr()
189 * Core interrupt handler. Every interrupt enabled in
190 * hci1394_isr_mask_setup() should be covered here. There may be other
191 * interrupts supported in here even if they are not initially enabled
192 * (like OHCI_INTR_CYC_64_SECS) since they may be enabled later (i.e. due to
193 * CSR register write)
194 */
195 static uint_t
hci1394_isr(caddr_t parm)196 hci1394_isr(caddr_t parm)
197 {
198 hci1394_state_t *soft_state;
199 h1394_posted_wr_err_t posted_wr_err;
200 uint32_t interrupt_event;
201 uint_t status;
202
203
204 status = DDI_INTR_UNCLAIMED;
205 soft_state = (hci1394_state_t *)parm;
206
207 ASSERT(soft_state != NULL);
208 TNF_PROBE_0_DEBUG(hci1394_isr_enter, HCI1394_TNF_HAL_STACK, "");
209
210 if (hci1394_state(&soft_state->drvinfo) == HCI1394_SHUTDOWN)
211 return (DDI_INTR_UNCLAIMED);
212
213 /*
214 * Get all of the enabled 1394 interrupts which are currently
215 * asserted.
216 */
217 interrupt_event = hci1394_ohci_intr_asserted(soft_state->ohci);
218 do {
219 /* handle the asserted interrupts */
220 if (interrupt_event & OHCI_INTR_BUS_RESET) {
221 hci1394_isr_bus_reset(soft_state);
222 status = DDI_INTR_CLAIMED;
223 }
224 if (interrupt_event & OHCI_INTR_SELFID_CMPLT) {
225 hci1394_isr_self_id(soft_state);
226 status = DDI_INTR_CLAIMED;
227 }
228 if (interrupt_event & OHCI_INTR_ISOCH_TX) {
229 hci1394_isr_isoch_it(soft_state);
230 status = DDI_INTR_CLAIMED;
231 }
232 if (interrupt_event & OHCI_INTR_ISOCH_RX) {
233 hci1394_isr_isoch_ir(soft_state);
234 status = DDI_INTR_CLAIMED;
235 }
236 if (interrupt_event & OHCI_INTR_REQ_TX_CMPLT) {
237 hci1394_isr_atreq_complete(soft_state);
238 status = DDI_INTR_CLAIMED;
239 }
240 if (interrupt_event & OHCI_INTR_RSPKT) {
241 hci1394_isr_arresp(soft_state);
242 status = DDI_INTR_CLAIMED;
243 }
244 if (interrupt_event & OHCI_INTR_RQPKT) {
245 hci1394_isr_arreq(soft_state);
246 status = DDI_INTR_CLAIMED;
247 }
248 if (interrupt_event & OHCI_INTR_RESP_TX_CMPLT) {
249 hci1394_isr_atresp_complete(soft_state);
250 status = DDI_INTR_CLAIMED;
251 }
252 if (interrupt_event & OHCI_INTR_CYC_64_SECS) {
253 hci1394_ohci_isr_cycle64seconds(soft_state->ohci);
254 status = DDI_INTR_CLAIMED;
255 }
256 if (interrupt_event & OHCI_INTR_UNRECOVERABLE_ERR) {
257 h1394_error_detected(soft_state->drvinfo.di_sl_private,
258 H1394_SELF_INITIATED_SHUTDOWN, NULL);
259 cmn_err(CE_WARN, "hci1394(%d): driver shutdown: "
260 "unrecoverable error interrupt detected",
261 soft_state->drvinfo.di_instance);
262 hci1394_shutdown(soft_state->drvinfo.di_dip);
263 status = DDI_INTR_CLAIMED;
264 }
265 if (interrupt_event & OHCI_INTR_CYC_LOST) {
266 hci1394_isoch_cycle_lost(soft_state);
267 status = DDI_INTR_CLAIMED;
268 }
269 if (interrupt_event & OHCI_INTR_CYC_INCONSISTENT) {
270 hci1394_isoch_cycle_inconsistent(soft_state);
271 status = DDI_INTR_CLAIMED;
272 }
273 if (interrupt_event & OHCI_INTR_CYC_TOO_LONG) {
274 hci1394_ohci_intr_clear(soft_state->ohci,
275 OHCI_INTR_CYC_TOO_LONG);
276 /* clear cycle master bit in csr state register */
277 hci1394_csr_state_bclr(soft_state->csr,
278 IEEE1394_CSR_STATE_CMSTR);
279 h1394_error_detected(soft_state->drvinfo.di_sl_private,
280 H1394_CYCLE_TOO_LONG, NULL);
281 status = DDI_INTR_CLAIMED;
282 }
283 if (interrupt_event & OHCI_INTR_POST_WR_ERR) {
284 hci1394_ohci_postwr_addr(soft_state->ohci,
285 &posted_wr_err.addr);
286 h1394_error_detected(soft_state->drvinfo.di_sl_private,
287 H1394_POSTED_WR_ERR, &posted_wr_err);
288 status = DDI_INTR_CLAIMED;
289 }
290 if (interrupt_event & OHCI_INTR_PHY) {
291 hci1394_ohci_isr_phy(soft_state->ohci);
292 status = DDI_INTR_CLAIMED;
293 }
294 if (interrupt_event & OHCI_INTR_LOCK_RESP_ERR) {
295 hci1394_ohci_intr_clear(soft_state->ohci,
296 OHCI_INTR_LOCK_RESP_ERR);
297 h1394_error_detected(soft_state->drvinfo.di_sl_private,
298 H1394_LOCK_RESP_ERR, NULL);
299 status = DDI_INTR_CLAIMED;
300 }
301
302 /*
303 * Check for self-id-complete interrupt disappearing. There is
304 * a chance in OpenHCI where it will assert the selfid
305 * interrupt and then take it away. We will look for this case
306 * and claim it just in case. We could possibly claim an
307 * interrupt that's not ours. We would have to be in the
308 * middle of a bus reset and a bunch of other weird stuff
309 * would have to align. It should not hurt anything if we do.
310 *
311 * This will very very rarely happen, if ever. We still have
312 * to handle the case, just in case. OpenHCI 1.1 should fix
313 * this problem.
314 */
315 if ((status == DDI_INTR_UNCLAIMED) &&
316 (hci1394_state(&soft_state->drvinfo) ==
317 HCI1394_BUS_RESET)) {
318 if (soft_state->drvinfo.di_gencnt !=
319 hci1394_ohci_current_busgen(soft_state->ohci)) {
320 TNF_PROBE_0(hci1394_isr_busgen_claim,
321 HCI1394_TNF_HAL, "");
322 status = DDI_INTR_CLAIMED;
323 }
324 }
325
326 /*
327 * See if any of the enabled 1394 interrupts have been asserted
328 * since we first checked.
329 */
330 interrupt_event = hci1394_ohci_intr_asserted(
331 soft_state->ohci);
332 } while (interrupt_event != 0);
333
334 TNF_PROBE_0_DEBUG(hci1394_isr_exit, HCI1394_TNF_HAL_STACK, "");
335
336 return (status);
337 }
338
339
340 /*
341 * hci1394_isr_bus_reset()
342 * Process a 1394 bus reset. This signifies that a bus reset has started.
343 * A bus reset will not be complete until a selfid complete interrupt
344 * comes in.
345 */
346 static void
hci1394_isr_bus_reset(hci1394_state_t * soft_state)347 hci1394_isr_bus_reset(hci1394_state_t *soft_state)
348 {
349 int status;
350
351
352 ASSERT(soft_state != NULL);
353 TNF_PROBE_0_DEBUG(hci1394_isr_bus_reset_enter,
354 HCI1394_TNF_HAL_STACK, "");
355
356 /*
357 * Set the driver state to reset. If we cannot, we have been shutdown.
358 * The only way we can get in this code is if we have a multi-processor
359 * machine and the HAL is shutdown by one processor running in base
360 * context while this interrupt handler runs in another processor.
361 * We will disable all interrupts and just return. We shouldn't have
362 * to disable the interrupts, but we will just in case.
363 */
364 status = hci1394_state_set(&soft_state->drvinfo, HCI1394_BUS_RESET);
365 if (status != DDI_SUCCESS) {
366 hci1394_ohci_intr_master_disable(soft_state->ohci);
367 return;
368 }
369
370 /*
371 * Save away reset generation count so we can detect self-id-compete
372 * interrupt which disappears in event register. This is discussed in
373 * more detail in hci1394_isr()
374 */
375 soft_state->drvinfo.di_gencnt =
376 hci1394_ohci_current_busgen(soft_state->ohci);
377
378 soft_state->drvinfo.di_stats.st_bus_reset_count++;
379
380 /*
381 * Mask off busReset until SelfIdComplete comes in. The bus reset
382 * interrupt will be asserted until the SelfIdComplete interrupt
383 * comes in (i.e. you cannot clear the interrupt until a SelfIdComplete
384 * interrupt). Therefore, we disable the interrupt via its mask so we
385 * don't get stuck in the ISR indefinitely.
386 */
387 hci1394_ohci_intr_disable(soft_state->ohci, OHCI_INTR_BUS_RESET);
388
389 /* Reset the ATREQ and ATRESP Q's */
390 hci1394_async_atreq_reset(soft_state->async);
391 hci1394_async_atresp_reset(soft_state->async);
392
393 /* Inform Services Layer about Bus Reset */
394 h1394_bus_reset(soft_state->drvinfo.di_sl_private,
395 (void **)&soft_state->sl_selfid_buf);
396
397 TNF_PROBE_0_DEBUG(hci1394_isr_bus_reset_exit,
398 HCI1394_TNF_HAL_STACK, "");
399 }
400
401
402 /*
403 * hci1394_isr_self_id()
404 * Process the selfid complete interrupt. The bus reset has completed
405 * and the 1394 HW has finished it's bus enumeration. The SW needs to
406 * see what's changed and handle any hotplug conditions.
407 */
408 static void
hci1394_isr_self_id(hci1394_state_t * soft_state)409 hci1394_isr_self_id(hci1394_state_t *soft_state)
410 {
411 int status;
412 uint_t node_id;
413 uint_t selfid_size;
414 uint_t quadlet_count;
415 uint_t index;
416 uint32_t *selfid_buf_p;
417 boolean_t selfid_error;
418 boolean_t nodeid_error;
419 boolean_t saw_error = B_FALSE;
420 uint_t phy_status;
421
422
423 ASSERT(soft_state != NULL);
424 TNF_PROBE_0_DEBUG(hci1394_isr_self_id_enter, HCI1394_TNF_HAL_STACK, "");
425
426 soft_state->drvinfo.di_stats.st_selfid_count++;
427
428 /*
429 * check for the bizarre case that we got both a bus reset and self id
430 * complete after checking for a bus reset
431 */
432 if (hci1394_state(&soft_state->drvinfo) != HCI1394_BUS_RESET) {
433 hci1394_isr_bus_reset(soft_state);
434 }
435
436 /*
437 * Clear any set PHY error status bits set. The PHY status bits
438 * may always be set (i.e. we removed cable power) so we do not want
439 * to clear them when we handle the interrupt. We will clear them
440 * every selfid complete interrupt so worst case we will get 1 PHY event
441 * interrupt every bus reset.
442 */
443 status = hci1394_ohci_phy_read(soft_state->ohci, 5, &phy_status);
444 if (status != DDI_SUCCESS) {
445 TNF_PROBE_0(hci1394_isr_self_id_pr_fail,
446 HCI1394_TNF_HAL_ERROR, "");
447 } else {
448 phy_status |= OHCI_PHY_LOOP_ERR | OHCI_PHY_PWRFAIL_ERR |
449 OHCI_PHY_TIMEOUT_ERR | OHCI_PHY_PORTEVT_ERR;
450 status = hci1394_ohci_phy_write(soft_state->ohci, 5,
451 phy_status);
452 if (status != DDI_SUCCESS) {
453 TNF_PROBE_0(hci1394_isr_self_id_pw_fail,
454 HCI1394_TNF_HAL_ERROR, "");
455 } else {
456 /*
457 * Re-enable PHY interrupt. We disable the PHY interrupt
458 * when we get one so that we do not get stuck in the
459 * ISR.
460 */
461 hci1394_ohci_intr_enable(soft_state->ohci,
462 OHCI_INTR_PHY);
463 }
464 }
465
466 /* See if either AT active bit is set */
467 if (hci1394_ohci_at_active(soft_state->ohci) == B_TRUE) {
468 TNF_PROBE_1(hci1394_isr_self_id_as_fail, HCI1394_TNF_HAL_ERROR,
469 "", tnf_string, errmsg, "AT ACTIVE still set");
470 saw_error = B_TRUE;
471 }
472
473 /* Clear busReset and selfIdComplete interrupts */
474 hci1394_ohci_intr_clear(soft_state->ohci, (OHCI_INTR_BUS_RESET |
475 OHCI_INTR_SELFID_CMPLT));
476
477 /* Read node info and test for Invalid Node ID */
478 hci1394_ohci_nodeid_info(soft_state->ohci, &node_id, &nodeid_error);
479 if (nodeid_error == B_TRUE) {
480 TNF_PROBE_1(hci1394_isr_self_id_ni_fail, HCI1394_TNF_HAL_ERROR,
481 "", tnf_string, errmsg, "saw invalid NodeID");
482 saw_error = B_TRUE;
483 }
484
485 /* Sync Selfid Buffer */
486 hci1394_ohci_selfid_sync(soft_state->ohci);
487
488 /* store away selfid info */
489 hci1394_ohci_selfid_info(soft_state->ohci,
490 &soft_state->drvinfo.di_gencnt, &selfid_size, &selfid_error);
491
492 /* Test for selfid error */
493 if (selfid_error == B_TRUE) {
494 TNF_PROBE_1(hci1394_isr_self_id_si_fail, HCI1394_TNF_HAL_ERROR,
495 "", tnf_string, errmsg, "saw invalid SelfID");
496 saw_error = B_TRUE;
497 }
498
499 /*
500 * selfid size could be 0 if a bus reset has occurred. If this occurs,
501 * we should have another selfid int coming later.
502 */
503 if ((saw_error == B_FALSE) && (selfid_size == 0)) {
504 TNF_PROBE_0_DEBUG(hci1394_isr_self_id_exit,
505 HCI1394_TNF_HAL_STACK, "");
506 return;
507 }
508
509 /*
510 * make sure generation count in buffer matches generation
511 * count in register.
512 */
513 if (hci1394_ohci_selfid_buf_current(soft_state->ohci) == B_FALSE) {
514 TNF_PROBE_0_DEBUG(hci1394_isr_self_id_exit,
515 HCI1394_TNF_HAL_STACK, "");
516 return;
517 }
518
519 /*
520 * Skip over first quadlet in selfid buffer, this is OpenHCI specific
521 * data.
522 */
523 selfid_size = selfid_size - IEEE1394_QUADLET;
524 quadlet_count = selfid_size >> 2;
525
526 /* Copy selfid buffer to Services Layer buffer */
527 for (index = 0; index < quadlet_count; index++) {
528 hci1394_ohci_selfid_read(soft_state->ohci, index + 1,
529 &soft_state->sl_selfid_buf[index]);
530 }
531
532 /*
533 * Put our selfID info into the Services Layer's selfid buffer if we
534 * have a 1394-1995 PHY.
535 */
536 if (soft_state->halinfo.phy == H1394_PHY_1995) {
537 selfid_buf_p = (uint32_t *)(
538 (uintptr_t)soft_state->sl_selfid_buf +
539 (uintptr_t)selfid_size);
540 status = hci1394_ohci_phy_info(soft_state->ohci,
541 &selfid_buf_p[0]);
542 if (status != DDI_SUCCESS) {
543 /*
544 * If we fail reading from PHY, put invalid data into
545 * the selfid buffer so the SL will reset the bus again.
546 */
547 TNF_PROBE_0(hci1394_isr_self_id_pi_fail,
548 HCI1394_TNF_HAL_ERROR, "");
549 selfid_buf_p[0] = 0xFFFFFFFF;
550 selfid_buf_p[1] = 0xFFFFFFFF;
551 } else {
552 selfid_buf_p[1] = ~selfid_buf_p[0];
553 }
554 selfid_size = selfid_size + 8;
555 }
556
557 /* Flush out async DMA Q's */
558 hci1394_async_flush(soft_state->async);
559
560 /*
561 * Make sure generation count is still valid. i.e. we have not gotten
562 * another bus reset since the last time we checked. If we have gotten
563 * another bus reset, we should have another selfid interrupt coming.
564 */
565 if (soft_state->drvinfo.di_gencnt !=
566 hci1394_ohci_current_busgen(soft_state->ohci)) {
567 TNF_PROBE_0_DEBUG(hci1394_isr_self_id_exit,
568 HCI1394_TNF_HAL_STACK, "");
569 return;
570 }
571
572 /*
573 * do whatever CSR register processing that needs to be done.
574 */
575 hci1394_csr_bus_reset(soft_state->csr);
576
577 /*
578 * do whatever management may be necessary for the CYCLE_LOST and
579 * CYCLE_INCONSISTENT interrupts.
580 */
581 hci1394_isoch_error_ints_enable(soft_state);
582
583 /*
584 * See if we saw an error. If we did, tell the services layer that we
585 * finished selfid processing and give them an illegal selfid buffer
586 * size of 0. The Services Layer will try to reset the bus again to
587 * see if we can recover from this problem. It will threshold after
588 * a finite number of errors.
589 */
590 if (saw_error == B_TRUE) {
591 h1394_self_ids(soft_state->drvinfo.di_sl_private,
592 soft_state->sl_selfid_buf, 0, node_id,
593 soft_state->drvinfo.di_gencnt);
594
595 /*
596 * Take ourself out of Bus Reset processing mode
597 *
598 * Set the driver state to normal. If we cannot, we have been
599 * shutdown. The only way we can get in this code is if we have
600 * a multi-processor machine and the HAL is shutdown by one
601 * processor running in base context while this interrupt
602 * handler runs in another processor. We will disable all
603 * interrupts and just return. We shouldn't have to disable
604 * the interrupts, but we will just in case.
605 */
606 status = hci1394_state_set(&soft_state->drvinfo,
607 HCI1394_NORMAL);
608 if (status != DDI_SUCCESS) {
609 hci1394_ohci_intr_master_disable(soft_state->ohci);
610 return;
611 }
612 } else if (IEEE1394_NODE_NUM(node_id) != 63) {
613 /*
614 * Notify services layer about self-id-complete. Don't notify
615 * the services layer if there are too many devices on the bus.
616 */
617 h1394_self_ids(soft_state->drvinfo.di_sl_private,
618 soft_state->sl_selfid_buf, selfid_size,
619 node_id, soft_state->drvinfo.di_gencnt);
620
621 /*
622 * Take ourself out of Bus Reset processing mode
623 *
624 * Set the driver state to normal. If we cannot, we have been
625 * shutdown. The only way we can get in this code is if we have
626 * a multi-processor machine and the HAL is shutdown by one
627 * processor running in base context while this interrupt
628 * handler runs in another processor. We will disable all
629 * interrupts and just return. We shouldn't have to disable
630 * the interrupts, but we will just in case.
631 */
632 status = hci1394_state_set(&soft_state->drvinfo,
633 HCI1394_NORMAL);
634 if (status != DDI_SUCCESS) {
635 hci1394_ohci_intr_master_disable(soft_state->ohci);
636 return;
637 }
638 } else {
639 cmn_err(CE_NOTE, "hci1394(%d): Too many devices on the 1394 "
640 "bus", soft_state->drvinfo.di_instance);
641 }
642
643 /* enable bus reset interrupt */
644 hci1394_ohci_intr_enable(soft_state->ohci, OHCI_INTR_BUS_RESET);
645
646 TNF_PROBE_0_DEBUG(hci1394_isr_self_id_exit, HCI1394_TNF_HAL_STACK, "");
647 }
648
649
650 /*
651 * hci1394_isr_isoch_ir()
652 * Process each isoch recv context which has its interrupt asserted. The
653 * interrupt will be asserted when an isoch recv descriptor with the
654 * interrupt bits enabled have finished being processed.
655 */
656 static void
hci1394_isr_isoch_ir(hci1394_state_t * soft_state)657 hci1394_isr_isoch_ir(hci1394_state_t *soft_state)
658 {
659 uint32_t i;
660 uint32_t mask = 0x00000001;
661 uint32_t ev;
662 int num_ir_contexts;
663 hci1394_iso_ctxt_t *ctxtp;
664
665
666 ASSERT(soft_state != NULL);
667 TNF_PROBE_0_DEBUG(hci1394_isr_isoch_ir_enter,
668 HCI1394_TNF_HAL_STACK, "");
669
670 num_ir_contexts = hci1394_isoch_recv_count_get(soft_state->isoch);
671
672 /*
673 * Main isochRx int is not clearable. it is automatically
674 * cleared by the hw when the ir_intr_event is cleared
675 */
676 /* loop until no more IR events */
677 while ((ev = hci1394_ohci_ir_intr_asserted(soft_state->ohci)) != 0) {
678
679 /* clear the events we just learned about */
680 hci1394_ohci_ir_intr_clear(soft_state->ohci, ev);
681
682 /* for each interrupting IR context, process the interrupt */
683 for (i = 0; i < num_ir_contexts; i++) {
684 /*
685 * if the intr bit is on for a context,
686 * call xmit/recv common processing code
687 */
688 if (ev & mask) {
689 ctxtp = hci1394_isoch_recv_ctxt_get(
690 soft_state->isoch, i);
691 hci1394_ixl_interrupt(soft_state, ctxtp,
692 B_FALSE);
693 }
694 mask <<= 1;
695 }
696 }
697 TNF_PROBE_0_DEBUG(hci1394_isr_isoch_ir_exit, HCI1394_TNF_HAL_STACK, "");
698 }
699
700
701 /*
702 * hci1394_isr_isoch_it()
703 * Process each isoch transmit context which has its interrupt asserted. The
704 * interrupt will be asserted when an isoch transmit descriptor with the
705 * interrupt bit is finished being processed.
706 */
707 static void
hci1394_isr_isoch_it(hci1394_state_t * soft_state)708 hci1394_isr_isoch_it(hci1394_state_t *soft_state)
709 {
710 uint32_t i;
711 uint32_t mask = 0x00000001;
712 uint32_t ev;
713 int num_it_contexts;
714 hci1394_iso_ctxt_t *ctxtp;
715
716
717 ASSERT(soft_state != NULL);
718 TNF_PROBE_0_DEBUG(hci1394_isr_isoch_it_enter,
719 HCI1394_TNF_HAL_STACK, "");
720
721 num_it_contexts = hci1394_isoch_xmit_count_get(soft_state->isoch);
722
723 /*
724 * Main isochTx int is not clearable. it is automatically
725 * cleared by the hw when the it_intr_event is cleared.
726 */
727
728 /* loop until no more IT events */
729 while ((ev = hci1394_ohci_it_intr_asserted(soft_state->ohci)) != 0) {
730
731 /* clear the events we just learned about */
732 hci1394_ohci_it_intr_clear(soft_state->ohci, ev);
733
734 /* for each interrupting IR context, process the interrupt */
735 for (i = 0; i < num_it_contexts; i++) {
736 /*
737 * if the intr bit is on for a context,
738 * call xmit/recv common processing code
739 */
740 if (ev & mask) {
741 ctxtp = hci1394_isoch_xmit_ctxt_get(
742 soft_state->isoch, i);
743 hci1394_ixl_interrupt(soft_state, ctxtp,
744 B_FALSE);
745 }
746 mask <<= 1;
747 }
748 }
749 TNF_PROBE_0_DEBUG(hci1394_isr_isoch_it_exit, HCI1394_TNF_HAL_STACK, "");
750 }
751
752
753 /*
754 * hci1394_isr_atreq_complete()
755 * Process all completed requests that we have sent out (i.e. HW gave us
756 * an ack).
757 */
758 static void
hci1394_isr_atreq_complete(hci1394_state_t * soft_state)759 hci1394_isr_atreq_complete(hci1394_state_t *soft_state)
760 {
761 boolean_t request_available;
762 int status;
763
764
765 ASSERT(soft_state != NULL);
766 TNF_PROBE_0_DEBUG(hci1394_isr_atreq_complete_enter,
767 HCI1394_TNF_HAL_STACK, "");
768
769 hci1394_ohci_intr_clear(soft_state->ohci, OHCI_INTR_REQ_TX_CMPLT);
770
771 /*
772 * Processes all ack'd AT requests. If the request is pended, it is
773 * considered complete relative the the atreq engine. AR response
774 * processing will make sure we track the response.
775 */
776 do {
777 /*
778 * Process a single request. Do not flush Q. That is only
779 * done during bus reset processing.
780 */
781 status = hci1394_async_atreq_process(soft_state->async, B_FALSE,
782 &request_available);
783 if (status != DDI_SUCCESS) {
784 TNF_PROBE_0(hci1394_isr_atreq_complete_pr_fail,
785 HCI1394_TNF_HAL_ERROR, "");
786 }
787 } while (request_available == B_TRUE);
788
789 TNF_PROBE_0_DEBUG(hci1394_isr_atreq_complete_exit,
790 HCI1394_TNF_HAL_STACK, "");
791 }
792
793
794 /*
795 * hci1394_isr_arresp()
796 * Process all responses that have come in off the bus and send then up to
797 * the services layer. We send out a request on the bus (atreq) and some time
798 * later a response comes in. We send this response up to the services
799 * layer.
800 */
801 static void
hci1394_isr_arresp(hci1394_state_t * soft_state)802 hci1394_isr_arresp(hci1394_state_t *soft_state)
803 {
804 boolean_t response_available;
805 int status;
806
807
808 ASSERT(soft_state != NULL);
809 TNF_PROBE_0_DEBUG(hci1394_isr_arresp_enter, HCI1394_TNF_HAL_STACK, "");
810
811 hci1394_ohci_intr_clear(soft_state->ohci, OHCI_INTR_RSPKT);
812
813 /*
814 * Process all responses that have been received. If more responses
815 * come in we will stay in interrupt handler and re-run this routine.
816 * It is possible that we will call hci1394_async_arresp_process()
817 * even though there are no more AR responses to process. This would
818 * be because we have processed them earlier on. (i.e. we cleared
819 * interrupt, then got another response and processed it. The interrupt
820 * would still be pending.
821 */
822 do {
823 status = hci1394_async_arresp_process(soft_state->async,
824 &response_available);
825 if (status != DDI_SUCCESS) {
826 TNF_PROBE_0(hci1394_isr_arresp_pr_fail,
827 HCI1394_TNF_HAL_ERROR, "");
828 }
829 } while (response_available == B_TRUE);
830
831 TNF_PROBE_0_DEBUG(hci1394_isr_arresp_exit, HCI1394_TNF_HAL_STACK, "");
832 }
833
834
835 /*
836 * hci1394_isr_arreq()
837 * Process all requests that have come in off the bus and send then up to
838 * the services layer.
839 */
840 static void
hci1394_isr_arreq(hci1394_state_t * soft_state)841 hci1394_isr_arreq(hci1394_state_t *soft_state)
842 {
843 boolean_t request_available;
844 int status;
845
846
847 ASSERT(soft_state != NULL);
848 TNF_PROBE_0_DEBUG(hci1394_isr_arreq_enter, HCI1394_TNF_HAL_STACK, "");
849
850 hci1394_ohci_intr_clear(soft_state->ohci, OHCI_INTR_RQPKT);
851
852 /*
853 * Process all requests that have been received. It is possible that we
854 * will call hci1394_async_arreq_process() even though there are no
855 * more requests to process. This would be because we have processed
856 * them earlier on. (i.e. we cleared interrupt, got another request
857 * and processed it. The interrupt would still be pending.
858 */
859 do {
860 status = hci1394_async_arreq_process(soft_state->async,
861 &request_available);
862 if (status != DDI_SUCCESS) {
863 TNF_PROBE_0(hci1394_isr_arreq_pr_fail,
864 HCI1394_TNF_HAL_ERROR, "");
865 }
866 } while (request_available == B_TRUE);
867
868 TNF_PROBE_0_DEBUG(hci1394_isr_arreq_exit, HCI1394_TNF_HAL_STACK, "");
869 }
870
871
872 /*
873 * hci1394_isr_atresp_complete()
874 * Process all completed responses that we have sent out (i.e. HW gave us
875 * an ack). We get in a request off the bus (arreq) and send it up to the
876 * services layer, they send down a response to that request some time
877 * later. This interrupt signifies that the HW is done with the response.
878 * (i.e. it sent it out or failed it)
879 */
880 static void
hci1394_isr_atresp_complete(hci1394_state_t * soft_state)881 hci1394_isr_atresp_complete(hci1394_state_t *soft_state)
882 {
883 boolean_t response_available;
884 int status;
885
886
887 ASSERT(soft_state != NULL);
888 TNF_PROBE_0_DEBUG(hci1394_isr_atresp_complete_enter,
889 HCI1394_TNF_HAL_STACK, "");
890
891 hci1394_ohci_intr_clear(soft_state->ohci, OHCI_INTR_RESP_TX_CMPLT);
892
893 /*
894 * Processes all ack'd AT responses It is possible that we will call
895 * hci1394_async_atresp_process() even thought there are no more
896 * responses to process. This would be because we have processed
897 * them earlier on. (i.e. we cleared interrupt, then got another
898 * response and processed it. The interrupt would still be pending.
899 */
900 do {
901 /*
902 * Process a single response. Do not flush Q. That is only
903 * done during bus reset processing.
904 */
905 status = hci1394_async_atresp_process(soft_state->async,
906 B_FALSE, &response_available);
907 if (status != DDI_SUCCESS) {
908 TNF_PROBE_0(hci1394_isr_atresp_complete_pr_fail,
909 HCI1394_TNF_HAL_ERROR, "");
910 }
911 } while (response_available == B_TRUE);
912
913 TNF_PROBE_0_DEBUG(hci1394_isr_atresp_complete_exit,
914 HCI1394_TNF_HAL_STACK, "");
915 }
916