1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright (c) 1999-2000 by Sun Microsystems, Inc. 24 * All rights reserved. 25 */ 26 27 #ifndef _SYS_1394_ADAPTERS_HCI1394_CSR_H 28 #define _SYS_1394_ADAPTERS_HCI1394_CSR_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 /* 33 * hci1394_csr.h 34 * This file contains the code for the CSR registers handled by the HAL in 35 * SW. The HW implemented CSR registers are in hci1394_ohci.c 36 * 37 * For more information on CSR registers, see 38 * IEEE 1212 39 * IEEE 1394-1995 40 * section 8.3.2 41 * IEEE P1394A Draft 3.0 42 * sections 10.32,10.33 43 * 44 * NOTE: A read/write to a CSR SW based register will first go to the Services 45 * Layer which will do some filtering and then come through the s1394if. 46 */ 47 48 #ifdef __cplusplus 49 extern "C" { 50 #endif 51 52 #include <sys/ddi.h> 53 #include <sys/modctl.h> 54 #include <sys/sunddi.h> 55 56 #include <sys/1394/adapters/hci1394_def.h> 57 58 59 /* 60 * The 1394 bus sends out cycle start packets periodically. The time in 61 * between these packets is commonly referred to as a bus cycle. The 1394 62 * cycle start packets come every 125uS. split_timeout is represented in 1394 63 * bus cycles (e.g. to have ATREQ ACK_PENDED timeout after 100mS, you would set 64 * split_timeout to 800). 65 * 66 * The CSR register interface has the split timeout broken into two registers, 67 * split_timeout_hi and split_timeout_lo. The least significant 3 bits of 68 * split_timeout_hi contain the # of seconds and the most significant 13 bits 69 * of split_timeout_lo contain the fraction of a seconds in 125uS increments. 70 * There is a further constraint that the value in split_timeout_lo must be >= 71 * 800 && <= 7999 (>=100mS && < 1S). (don't forget that this value is in the 72 * most significant 13 bits, i.e. 800 << 19) We will threshold the writes into 73 * these registers to make sure they always have legal values (i.e. if 74 * [8000 << 19] is written to split_timeout_lo, we will write [7999 << 19]. 75 * 76 * The split timeout CSR registers have some inherent problems. There is a race 77 * condition when updating the split timeout value since you cannot atomically 78 * write to both the hi and lo registers. This should not be a serious problem 79 * since we should never get close to having a split timeout of 1S or greater. 80 */ 81 82 83 /* CSR Register Address Offsets (1394-1995 8.3.2.2) */ 84 #define CSR_STATE_CLEAR 0x000 85 #define CSR_STATE_SET 0x004 86 #define CSR_NODE_IDS 0x008 87 #define CSR_RESET_START 0x00C 88 #define CSR_SPLIT_TIMEOUT_HI 0x018 89 #define CSR_SPLIT_TIMEOUT_LO 0x01C 90 #define CSR_CYCLE_TIME 0x200 91 #define CSR_BUS_TIME 0x204 92 #define CSR_BUSY_TIMEOUT 0x210 93 #define CSR_BUS_MANAGER_ID 0x21C 94 #define CSR_BANDWIDTH_AVAILABLE 0x220 95 #define CSR_CHANNELS_AVAILABLE_HI 0x224 96 #define CSR_CHANNELS_AVAILABLE_LO 0x228 97 98 99 typedef struct hci1394_csr_s { 100 /* SW registers */ 101 uint32_t csr_state; 102 uint32_t csr_split_timeout_lo; 103 uint32_t csr_split_timeout_hi; 104 105 /* split timeout that we are observing */ 106 uint_t csr_split_timeout; 107 108 /* were we root last bus reset */ 109 boolean_t csr_was_root; 110 111 /* our node capabilities */ 112 uint32_t csr_capabilities; 113 114 /* copies of OpenHCI handle and pointer to general driver info */ 115 hci1394_ohci_handle_t csr_ohci; 116 hci1394_drvinfo_t *csr_drvinfo; 117 118 kmutex_t csr_mutex; 119 } hci1394_csr_t; 120 121 /* handle passed back from init() and used for rest of functions */ 122 typedef struct hci1394_csr_s *hci1394_csr_handle_t; 123 124 125 void hci1394_csr_init(hci1394_drvinfo_t *drvinfo, hci1394_ohci_handle_t ohci, 126 hci1394_csr_handle_t *csr_handle); 127 void hci1394_csr_fini(hci1394_csr_handle_t *csr_handle); 128 void hci1394_csr_resume(hci1394_csr_handle_t csr_handle); 129 130 void hci1394_csr_node_capabilities(hci1394_csr_handle_t csr_handle, 131 uint32_t *capabilities); 132 133 void hci1394_csr_state_get(hci1394_csr_handle_t csr_handle, uint32_t *state); 134 void hci1394_csr_state_bset(hci1394_csr_handle_t csr_handle, uint32_t state); 135 void hci1394_csr_state_bclr(hci1394_csr_handle_t csr_handle, uint32_t state); 136 137 void hci1394_csr_split_timeout_hi_get(hci1394_csr_handle_t csr_handle, 138 uint32_t *split_timeout_hi); 139 void hci1394_csr_split_timeout_lo_get(hci1394_csr_handle_t csr_handle, 140 uint32_t *split_timeout_lo); 141 void hci1394_csr_split_timeout_hi_set(hci1394_csr_handle_t csr_handle, 142 uint32_t split_timeout_hi); 143 void hci1394_csr_split_timeout_lo_set(hci1394_csr_handle_t csr_handle, 144 uint32_t split_timeout_lo); 145 uint_t hci1394_csr_split_timeout_get(hci1394_csr_handle_t csr_handle); 146 147 void hci1394_csr_bus_reset(hci1394_csr_handle_t csr_handle); 148 149 150 #ifdef __cplusplus 151 } 152 #endif 153 154 #endif /* _SYS_1394_ADAPTERS_HCI1394_CSR_H */ 155