xref: /illumos-gate/usr/src/uts/common/io/qede/579xx/drivers/ecore/hsi_repository/eth_common.h (revision 14b24e2b79293068c8e016a69ef1d872fb5e2fd5)
1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License, v.1,  (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://opensource.org/licenses/CDDL-1.0.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 
22 /*
23 * Copyright 2014-2017 Cavium, Inc.
24 * The contents of this file are subject to the terms of the Common Development
25 * and Distribution License, v.1,  (the "License").
26 
27 * You may not use this file except in compliance with the License.
28 
29 * You can obtain a copy of the License at available
30 * at http://opensource.org/licenses/CDDL-1.0
31 
32 * See the License for the specific language governing permissions and
33 * limitations under the License.
34 */
35 
36 #ifndef __ETH_COMMON__
37 #define __ETH_COMMON__
38 /********************/
39 /* ETH FW CONSTANTS */
40 /********************/
41 
42 /* FP HSI version. FP HSI is compatible if (fwVer.major == drvVer.major && fwVer.minor >= drvVer.minor) */
43 #define ETH_HSI_VER_MAJOR                   3    /* ETH FP HSI Major version */
44 #define ETH_HSI_VER_MINOR                   10   /* ETH FP HSI Minor version */
45 
46 #define ETH_HSI_VER_NO_PKT_LEN_TUNN         5  /* Alias for 8.7.x.x/8.8.x.x ETH FP HSI MINOR version. In this version driver is not required to set pkt_len field in eth_tx_1st_bd struct, and tunneling offload is not supported. */
47 
48 #define ETH_CACHE_LINE_SIZE                 64
49 #define ETH_RX_CQE_GAP                      32
50 #define ETH_MAX_RAMROD_PER_CON              8
51 #define ETH_TX_BD_PAGE_SIZE_BYTES           4096
52 #define ETH_RX_BD_PAGE_SIZE_BYTES           4096
53 #define ETH_RX_CQE_PAGE_SIZE_BYTES          4096
54 #define ETH_RX_NUM_NEXT_PAGE_BDS            2
55 
56 /* Limitation for Tunneled LSO Packets on the offset (in bytes) of the inner IP header (relevant to LSO for tunneled packet): */
57 #define ETH_MAX_TUNN_LSO_INNER_IPV4_OFFSET          253 /* Offset is limited to 253 bytes (inclusive). */
58 #define ETH_MAX_TUNN_LSO_INNER_IPV6_OFFSET          251 /* Offset is limited to 251 bytes (inclusive). */
59 
60 #define ETH_TX_MIN_BDS_PER_NON_LSO_PKT              1
61 #define ETH_TX_MAX_BDS_PER_NON_LSO_PACKET           18
62 #define ETH_TX_MAX_BDS_PER_LSO_PACKET               255
63 #define ETH_TX_MAX_LSO_HDR_NBD                      4
64 #define ETH_TX_MIN_BDS_PER_LSO_PKT                  3
65 #define ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT   3
66 #define ETH_TX_MIN_BDS_PER_IPV6_WITH_EXT_PKT        2
67 #define ETH_TX_MIN_BDS_PER_PKT_W_LOOPBACK_MODE      2
68 #define ETH_TX_MAX_NON_LSO_PKT_LEN                  (9700 - (4 + 4 + 12 + 8)) /* (QM_REG_TASKBYTECRDCOST_0, QM_VOQ_BYTE_CRD_TASK_COST) - (VLAN-TAG + CRC + IPG + PREAMBLE) */
69 #define ETH_TX_MAX_LSO_HDR_BYTES                    510
70 #define ETH_TX_LSO_WINDOW_BDS_NUM                   (18 - 1)    /* Number of BDs to consider for LSO sliding window restriction is (ETH_TX_LSO_WINDOW_BDS_NUM - hdr_nbd) */
71 #define ETH_TX_LSO_WINDOW_MIN_LEN                   9700  /* Minimum data length (in bytes) in LSO sliding window */
72 #define ETH_TX_MAX_LSO_PAYLOAD_LEN                  0xFE000  /* Maximum LSO packet TCP payload length (in bytes) */
73 #define ETH_TX_NUM_SAME_AS_LAST_ENTRIES             320 /* Number of same-as-last resources in tx switching */
74 #define ETH_TX_INACTIVE_SAME_AS_LAST                0xFFFF /* Value for a connection for which same as last feature is disabled */
75 
76 #define ETH_NUM_STATISTIC_COUNTERS                  MAX_NUM_VPORTS                                     /* Maximum number of statistics counters */
77 #define ETH_NUM_STATISTIC_COUNTERS_DOUBLE_VF_ZONE   (ETH_NUM_STATISTIC_COUNTERS - MAX_NUM_VFS/2)       /* Maximum number of statistics counters when doubled VF zone used */
78 #define ETH_NUM_STATISTIC_COUNTERS_QUAD_VF_ZONE     (ETH_NUM_STATISTIC_COUNTERS - 3*MAX_NUM_VFS/4)     /* Maximum number of statistics counters when quad VF zone used */
79 
80 #define ETH_RX_MAX_BUFF_PER_PKT             5       /* Maximum number of buffers, used for RX packet placement */
81 #define ETH_RX_BD_THRESHOLD                12       /* Minimum number of free BDs in RX ring, that guarantee receiving of at least one RX packet. */
82 
83 /* num of MAC/VLAN filters */
84 #define ETH_NUM_MAC_FILTERS                 512
85 #define ETH_NUM_VLAN_FILTERS                512
86 
87 /* approx. multicast constants */
88 #define ETH_MULTICAST_BIN_FROM_MAC_SEED     0     /* CRC seed for multicast bin calculation */
89 #define ETH_MULTICAST_MAC_BINS              256
90 #define ETH_MULTICAST_MAC_BINS_IN_REGS      (ETH_MULTICAST_MAC_BINS / 32)
91 
92 /*  ethernet vport update constants */
93 #define ETH_FILTER_RULES_COUNT              10
94 #define ETH_RSS_IND_TABLE_ENTRIES_NUM       128  /* number of RSS indirection table entries, per Vport) */
95 #define ETH_RSS_KEY_SIZE_REGS               10  /* Length of RSS key (in regs) */
96 #define ETH_RSS_ENGINE_NUM_K2               207 /* number of available RSS engines in K2 */
97 #define ETH_RSS_ENGINE_NUM_BB               127 /* number of available RSS engines in BB */
98 
99 /* TPA constants */
100 #define ETH_TPA_MAX_AGGS_NUM              64      /* Maximum number of open TPA aggregations */
101 #define ETH_TPA_CQE_START_LEN_LIST_SIZE   ETH_RX_MAX_BUFF_PER_PKT   /* Maximum number of additional buffers, reported by TPA-start CQE */
102 #define ETH_TPA_CQE_CONT_LEN_LIST_SIZE    6       /* Maximum number of buffers, reported by TPA-continue CQE */
103 #define ETH_TPA_CQE_END_LEN_LIST_SIZE     4       /* Maximum number of buffers, reported by TPA-end CQE */
104 
105 /* Control frame check constants */
106 #define ETH_CTL_FRAME_ETH_TYPE_NUM              4        /* Number of etherType values configured by the driver for control frame check */
107 
108 
109 
110 /*
111  * Destination port mode
112  */
113 enum dest_port_mode
114 {
115 	DEST_PORT_PHY /* Send to physical port. */,
116 	DEST_PORT_LOOPBACK /* Send to loopback port. */,
117 	DEST_PORT_PHY_LOOPBACK /* Send to physical and loopback port. */,
118 	DEST_PORT_DROP /* Drop the packet in PBF. */,
119 	MAX_DEST_PORT_MODE
120 };
121 
122 
123 /*
124  * Ethernet address type
125  */
126 enum eth_addr_type
127 {
128 	BROADCAST_ADDRESS,
129 	MULTICAST_ADDRESS,
130 	UNICAST_ADDRESS,
131 	UNKNOWN_ADDRESS,
132 	MAX_ETH_ADDR_TYPE
133 };
134 
135 
136 struct eth_tx_1st_bd_flags
137 {
138 	u8 bitfields;
139 #define ETH_TX_1ST_BD_FLAGS_START_BD_MASK         0x1 /* Set to 1 in the first BD. (for debug) */
140 #define ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT        0
141 #define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_MASK  0x1 /* Do not allow additional VLAN manipulations on this packet. */
142 #define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_SHIFT 1
143 #define ETH_TX_1ST_BD_FLAGS_IP_CSUM_MASK          0x1 /* Recalculate IP checksum. For tunneled packet - relevant to inner header. */
144 #define ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT         2
145 #define ETH_TX_1ST_BD_FLAGS_L4_CSUM_MASK          0x1 /* Recalculate TCP/UDP checksum. For tunneled packet - relevant to inner header. */
146 #define ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT         3
147 #define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_MASK   0x1 /* If set, insert VLAN tag from vlan field to the packet. For tunneled packet - relevant to outer header. */
148 #define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT  4
149 #define ETH_TX_1ST_BD_FLAGS_LSO_MASK              0x1 /* If set, this is an LSO packet. Note: For Tunneled LSO packets, the offset of the inner IPV4 (and IPV6) header is limited to 253 (and 251 respectively) bytes, inclusive. */
150 #define ETH_TX_1ST_BD_FLAGS_LSO_SHIFT             5
151 #define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK     0x1 /* Recalculate Tunnel IP Checksum (if Tunnel IP Header is IPv4) */
152 #define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT    6
153 #define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK     0x1 /* Recalculate Tunnel UDP/GRE Checksum (Depending on Tunnel Type) */
154 #define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT    7
155 };
156 
157 /*
158  * The parsing information data for the first tx bd of a given packet.
159  */
160 struct eth_tx_data_1st_bd
161 {
162 	__le16 vlan /* VLAN tag to insert to packet (if enabled by vlan_insertion flag). */;
163 	u8 nbds /* Number of BDs in packet. Should be at least 1 in non-LSO packet and at least 3 in LSO (or Tunnel with IPv6+ext) packet. */;
164 	struct eth_tx_1st_bd_flags bd_flags;
165 	__le16 bitfields;
166 #define ETH_TX_DATA_1ST_BD_TUNN_FLAG_MASK  0x1 /* Indicates a tunneled packet. Must be set for encapsulated packet. */
167 #define ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT 0
168 #define ETH_TX_DATA_1ST_BD_RESERVED0_MASK  0x1
169 #define ETH_TX_DATA_1ST_BD_RESERVED0_SHIFT 1
170 #define ETH_TX_DATA_1ST_BD_PKT_LEN_MASK    0x3FFF /* Total packet length - must be filled for non-LSO packets. */
171 #define ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT   2
172 };
173 
174 /*
175  * The parsing information data for the second tx bd of a given packet.
176  */
177 struct eth_tx_data_2nd_bd
178 {
179 	__le16 tunn_ip_size /* For tunnel with IPv6+ext - Tunnel header IP datagram length (in BYTEs) */;
180 	__le16 bitfields1;
181 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK  0xF /* For Tunnel header with IPv6 ext. - Inner L2 Header Size (in 2-byte WORDs) */
182 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_SHIFT 0
183 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_MASK       0x3 /* For Tunnel header with IPv6 ext. - Inner L2 Header MAC DA Type (use enum eth_addr_type) */
184 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_SHIFT      4
185 #define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_MASK            0x3 /* Destination port mode. (use enum dest_port_mode) */
186 #define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_SHIFT           6
187 #define ETH_TX_DATA_2ND_BD_START_BD_MASK                  0x1 /* Should be 0 in all the BDs, except the first one. (for debug) */
188 #define ETH_TX_DATA_2ND_BD_START_BD_SHIFT                 8
189 #define ETH_TX_DATA_2ND_BD_TUNN_TYPE_MASK                 0x3 /* For Tunnel header with IPv6 ext. - Tunnel Type (use enum eth_tx_tunn_type) */
190 #define ETH_TX_DATA_2ND_BD_TUNN_TYPE_SHIFT                9
191 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_MASK           0x1 /* For LSO / Tunnel header with IPv6+ext - Set if inner header is IPv6 */
192 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_SHIFT          11
193 #define ETH_TX_DATA_2ND_BD_IPV6_EXT_MASK                  0x1 /* In tunneling mode - Set to 1 when the Inner header is IPv6 with extension. Otherwise set to 1 if the header is IPv6 with extension. */
194 #define ETH_TX_DATA_2ND_BD_IPV6_EXT_SHIFT                 12
195 #define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_MASK             0x1 /* Set to 1 if Tunnel (outer = encapsulating) header has IPv6 ext. (Note: 3rd BD is required, hence EDPM does not support Tunnel [outer] header with Ipv6Ext) */
196 #define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_SHIFT            13
197 #define ETH_TX_DATA_2ND_BD_L4_UDP_MASK                    0x1 /* Set if (inner) L4 protocol is UDP. (Required when IPv6+ext (or tunnel with inner or outer Ipv6+ext) and l4_csum is set) */
198 #define ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT                   14
199 #define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_MASK       0x1 /* The pseudo header checksum type in the L4 checksum field. Required when IPv6+ext and l4_csum is set. (use enum eth_l4_pseudo_checksum_mode) */
200 #define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT      15
201 	__le16 bitfields2;
202 #define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK     0x1FFF /* For inner/outer header IPv6+ext - (inner) L4 header offset (in 2-byte WORDs). For regular packet - offset from the beginning of the packet. For tunneled packet - offset from the beginning of the inner header */
203 #define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT    0
204 #define ETH_TX_DATA_2ND_BD_RESERVED0_MASK                 0x7
205 #define ETH_TX_DATA_2ND_BD_RESERVED0_SHIFT                13
206 };
207 
208 /*
209  * Firmware data for L2-EDPM packet.
210  */
211 struct eth_edpm_fw_data
212 {
213 	struct eth_tx_data_1st_bd data_1st_bd /* Parsing information data from the 1st BD. */;
214 	struct eth_tx_data_2nd_bd data_2nd_bd /* Parsing information data from the 2nd BD. */;
215 	__le32 reserved;
216 };
217 
218 
219 /*
220  * FW debug.
221  */
222 struct eth_fast_path_cqe_fw_debug
223 {
224 	__le16 reserved2 /* FW reserved. */;
225 };
226 
227 
228 /*
229  * tunneling parsing flags
230  */
231 struct eth_tunnel_parsing_flags
232 {
233 	u8 flags;
234 #define ETH_TUNNEL_PARSING_FLAGS_TYPE_MASK              0x3 /* 0 - no tunneling, 1 - GENEVE, 2 - GRE, 3 - VXLAN (use enum eth_rx_tunn_type) */
235 #define ETH_TUNNEL_PARSING_FLAGS_TYPE_SHIFT             0
236 #define ETH_TUNNEL_PARSING_FLAGS_TENNANT_ID_EXIST_MASK  0x1 /*  If it s not an encapsulated packet then put 0x0. If it s an encapsulated packet but the tenant-id doesn t exist then put 0x0. Else put 0x1 */
237 #define ETH_TUNNEL_PARSING_FLAGS_TENNANT_ID_EXIST_SHIFT 2
238 #define ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_MASK     0x3 /* Type of the next header above the tunneling: 0 - unknown, 1 - L2, 2 - Ipv4, 3 - IPv6 (use enum tunnel_next_protocol) */
239 #define ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_SHIFT    3
240 #define ETH_TUNNEL_PARSING_FLAGS_FIRSTHDRIPMATCH_MASK   0x1 /* The result of comparing the DA-ip of the tunnel header. */
241 #define ETH_TUNNEL_PARSING_FLAGS_FIRSTHDRIPMATCH_SHIFT  5
242 #define ETH_TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_MASK     0x1
243 #define ETH_TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_SHIFT    6
244 #define ETH_TUNNEL_PARSING_FLAGS_IPV4_OPTIONS_MASK      0x1
245 #define ETH_TUNNEL_PARSING_FLAGS_IPV4_OPTIONS_SHIFT     7
246 };
247 
248 /*
249  * PMD flow control bits
250  */
251 struct eth_pmd_flow_flags
252 {
253 	u8 flags;
254 #define ETH_PMD_FLOW_FLAGS_VALID_MASK     0x1 /* CQE valid bit */
255 #define ETH_PMD_FLOW_FLAGS_VALID_SHIFT    0
256 #define ETH_PMD_FLOW_FLAGS_TOGGLE_MASK    0x1 /* CQE ring toggle bit */
257 #define ETH_PMD_FLOW_FLAGS_TOGGLE_SHIFT   1
258 #define ETH_PMD_FLOW_FLAGS_RESERVED_MASK  0x3F
259 #define ETH_PMD_FLOW_FLAGS_RESERVED_SHIFT 2
260 };
261 
262 /*
263  * Regular ETH Rx FP CQE.
264  */
265 struct eth_fast_path_rx_reg_cqe
266 {
267 	u8 type /* CQE type */;
268 	u8 bitfields;
269 #define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_MASK  0x7 /* Type of calculated RSS hash (use enum rss_hash_type) */
270 #define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_SHIFT 0
271 #define ETH_FAST_PATH_RX_REG_CQE_TC_MASK             0xF /* Traffic Class */
272 #define ETH_FAST_PATH_RX_REG_CQE_TC_SHIFT            3
273 #define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_MASK      0x1
274 #define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_SHIFT     7
275 	__le16 pkt_len /* Total packet length (from the parser) */;
276 	struct parsing_and_err_flags pars_flags /* Parsing and error flags from the parser */;
277 	__le16 vlan_tag /* 802.1q VLAN tag */;
278 	__le32 rss_hash /* RSS hash result */;
279 	__le16 len_on_first_bd /* Number of bytes placed on first BD */;
280 	u8 placement_offset /* Offset of placement from BD start */;
281 	struct eth_tunnel_parsing_flags tunnel_pars_flags /* Tunnel Parsing Flags */;
282 	u8 bd_num /* Number of BDs, used for packet */;
283 	u8 reserved[9];
284 	struct eth_fast_path_cqe_fw_debug fw_debug /* FW reserved. */;
285 	u8 reserved1[3];
286 	struct eth_pmd_flow_flags pmd_flags /* CQE valid and toggle bits */;
287 };
288 
289 
290 /*
291  * TPA-continue ETH Rx FP CQE.
292  */
293 struct eth_fast_path_rx_tpa_cont_cqe
294 {
295 	u8 type /* CQE type */;
296 	u8 tpa_agg_index /* TPA aggregation index */;
297 	__le16 len_list[ETH_TPA_CQE_CONT_LEN_LIST_SIZE] /* List of the segment sizes */;
298 	u8 reserved;
299 	u8 reserved1 /* FW reserved. */;
300 	__le16 reserved2[ETH_TPA_CQE_CONT_LEN_LIST_SIZE] /* FW reserved. */;
301 	u8 reserved3[3];
302 	struct eth_pmd_flow_flags pmd_flags /* CQE valid and toggle bits */;
303 };
304 
305 
306 /*
307  * TPA-end ETH Rx FP CQE .
308  */
309 struct eth_fast_path_rx_tpa_end_cqe
310 {
311 	u8 type /* CQE type */;
312 	u8 tpa_agg_index /* TPA aggregation index */;
313 	__le16 total_packet_len /* Total aggregated packet length */;
314 	u8 num_of_bds /* Total number of BDs comprising the packet */;
315 	u8 end_reason /* Aggregation end reason. Use enum eth_tpa_end_reason */;
316 	__le16 num_of_coalesced_segs /* Number of coalesced TCP segments */;
317 	__le32 ts_delta /* TCP timestamp delta */;
318 	__le16 len_list[ETH_TPA_CQE_END_LEN_LIST_SIZE] /* List of the segment sizes */;
319 	__le16 reserved3[ETH_TPA_CQE_END_LEN_LIST_SIZE] /* FW reserved. */;
320 	__le16 reserved1;
321 	u8 reserved2 /* FW reserved. */;
322 	struct eth_pmd_flow_flags pmd_flags /* CQE valid and toggle bits */;
323 };
324 
325 
326 /*
327  * TPA-start ETH Rx FP CQE.
328  */
329 struct eth_fast_path_rx_tpa_start_cqe
330 {
331 	u8 type /* CQE type */;
332 	u8 bitfields;
333 #define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_MASK  0x7 /* Type of calculated RSS hash (use enum rss_hash_type) */
334 #define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_SHIFT 0
335 #define ETH_FAST_PATH_RX_TPA_START_CQE_TC_MASK             0xF /* Traffic Class */
336 #define ETH_FAST_PATH_RX_TPA_START_CQE_TC_SHIFT            3
337 #define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_MASK      0x1
338 #define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_SHIFT     7
339 	__le16 seg_len /* Segment length (packetLen from the parser) */;
340 	struct parsing_and_err_flags pars_flags /* Parsing and error flags from the parser */;
341 	__le16 vlan_tag /* 802.1q VLAN tag */;
342 	__le32 rss_hash /* RSS hash result */;
343 	__le16 len_on_first_bd /* Number of bytes placed on first BD */;
344 	u8 placement_offset /* Offset of placement from BD start */;
345 	struct eth_tunnel_parsing_flags tunnel_pars_flags /* Tunnel Parsing Flags */;
346 	u8 tpa_agg_index /* TPA aggregation index */;
347 	u8 header_len /* Packet L2+L3+L4 header length */;
348 	__le16 ext_bd_len_list[ETH_TPA_CQE_START_LEN_LIST_SIZE] /* Additional BDs length list. */;
349 	struct eth_fast_path_cqe_fw_debug fw_debug /* FW reserved. */;
350 	u8 reserved;
351 	struct eth_pmd_flow_flags pmd_flags /* CQE valid and toggle bits */;
352 };
353 
354 
355 /*
356  * The L4 pseudo checksum mode for Ethernet
357  */
358 enum eth_l4_pseudo_checksum_mode
359 {
360 	ETH_L4_PSEUDO_CSUM_CORRECT_LENGTH /* Pseudo Header checksum on packet is calculated with the correct packet length field. */,
361 	ETH_L4_PSEUDO_CSUM_ZERO_LENGTH /* Pseudo Header checksum on packet is calculated with zero length field. */,
362 	MAX_ETH_L4_PSEUDO_CHECKSUM_MODE
363 };
364 
365 
366 
367 struct eth_rx_bd
368 {
369 	struct regpair addr /* single continues buffer */;
370 };
371 
372 
373 /*
374  * regular ETH Rx SP CQE
375  */
376 struct eth_slow_path_rx_cqe
377 {
378 	u8 type /* CQE type */;
379 	u8 ramrod_cmd_id;
380 	u8 error_flag;
381 	u8 reserved[25];
382 	__le16 echo;
383 	u8 reserved1;
384 	struct eth_pmd_flow_flags pmd_flags /* CQE valid and toggle bits */;
385 };
386 
387 /*
388  * union for all ETH Rx CQE types
389  */
390 union eth_rx_cqe
391 {
392 	struct eth_fast_path_rx_reg_cqe fast_path_regular /* Regular FP CQE */;
393 	struct eth_fast_path_rx_tpa_start_cqe fast_path_tpa_start /* TPA-start CQE */;
394 	struct eth_fast_path_rx_tpa_cont_cqe fast_path_tpa_cont /* TPA-continue CQE */;
395 	struct eth_fast_path_rx_tpa_end_cqe fast_path_tpa_end /* TPA-end CQE */;
396 	struct eth_slow_path_rx_cqe slow_path /* SP CQE */;
397 };
398 
399 
400 /*
401  * ETH Rx CQE type
402  */
403 enum eth_rx_cqe_type
404 {
405 	ETH_RX_CQE_TYPE_UNUSED,
406 	ETH_RX_CQE_TYPE_REGULAR /* Regular FP ETH Rx CQE */,
407 	ETH_RX_CQE_TYPE_SLOW_PATH /* Slow path ETH Rx CQE */,
408 	ETH_RX_CQE_TYPE_TPA_START /* TPA start ETH Rx CQE */,
409 	ETH_RX_CQE_TYPE_TPA_CONT /* TPA Continue ETH Rx CQE */,
410 	ETH_RX_CQE_TYPE_TPA_END /* TPA end ETH Rx CQE */,
411 	MAX_ETH_RX_CQE_TYPE
412 };
413 
414 
415 /*
416  * Wrapper for PD RX CQE - used in order to cover full cache line when writing CQE
417  */
418 struct eth_rx_pmd_cqe
419 {
420 	union eth_rx_cqe cqe /* CQE data itself */;
421 	u8 reserved[ETH_RX_CQE_GAP];
422 };
423 
424 
425 /*
426  * Eth RX Tunnel Type
427  */
428 enum eth_rx_tunn_type
429 {
430 	ETH_RX_NO_TUNN /* No Tunnel. */,
431 	ETH_RX_TUNN_GENEVE /* GENEVE Tunnel. */,
432 	ETH_RX_TUNN_GRE /* GRE Tunnel. */,
433 	ETH_RX_TUNN_VXLAN /* VXLAN Tunnel. */,
434 	MAX_ETH_RX_TUNN_TYPE
435 };
436 
437 
438 
439 /*
440  * Aggregation end reason.
441  */
442 enum eth_tpa_end_reason
443 {
444 	ETH_AGG_END_UNUSED,
445 	ETH_AGG_END_SP_UPDATE /* SP configuration update */,
446 	ETH_AGG_END_MAX_LEN /* Maximum aggregation length or maximum buffer number used. */,
447 	ETH_AGG_END_LAST_SEG /* TCP PSH flag or TCP payload length below continue threshold. */,
448 	ETH_AGG_END_TIMEOUT /* Timeout expiration. */,
449 	ETH_AGG_END_NOT_CONSISTENT /* Packet header not consistency: different IPv4 TOS, TTL or flags, IPv6 TC, Hop limit or Flow label, TCP header length or TS options. In GRO different TS value, SMAC, DMAC, ackNum, windowSize or VLAN */,
450 	ETH_AGG_END_OUT_OF_ORDER /* Out of order or retransmission packet: sequence, ack or timestamp not consistent with previous segment. */,
451 	ETH_AGG_END_NON_TPA_SEG /* Next segment cant be aggregated due to LLC/SNAP, IP error, IP fragment, IPv4 options, IPv6 extension, IP ECN = CE, TCP errors, TCP options, zero TCP payload length , TCP flags or not supported tunnel header options.  */,
452 	MAX_ETH_TPA_END_REASON
453 };
454 
455 
456 
457 /*
458  * The first tx bd of a given packet
459  */
460 struct eth_tx_1st_bd
461 {
462 	struct regpair addr /* Single continuous buffer */;
463 	__le16 nbytes /* Number of bytes in this BD. */;
464 	struct eth_tx_data_1st_bd data /* Parsing information data. */;
465 };
466 
467 
468 
469 /*
470  * The second tx bd of a given packet
471  */
472 struct eth_tx_2nd_bd
473 {
474 	struct regpair addr /* Single continuous buffer */;
475 	__le16 nbytes /* Number of bytes in this BD. */;
476 	struct eth_tx_data_2nd_bd data /* Parsing information data. */;
477 };
478 
479 
480 /*
481  * The parsing information data for the third tx bd of a given packet.
482  */
483 struct eth_tx_data_3rd_bd
484 {
485 	__le16 lso_mss /* For LSO packet - the MSS in bytes. */;
486 	__le16 bitfields;
487 #define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_MASK  0xF /* For LSO with inner/outer IPv6+ext - TCP header length (in 4-byte WORDs) */
488 #define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_SHIFT 0
489 #define ETH_TX_DATA_3RD_BD_HDR_NBD_MASK         0xF /* LSO - number of BDs which contain headers. value should be in range (1..ETH_TX_MAX_LSO_HDR_NBD). */
490 #define ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT        4
491 #define ETH_TX_DATA_3RD_BD_START_BD_MASK        0x1 /* Should be 0 in all the BDs, except the first one. (for debug) */
492 #define ETH_TX_DATA_3RD_BD_START_BD_SHIFT       8
493 #define ETH_TX_DATA_3RD_BD_RESERVED0_MASK       0x7F
494 #define ETH_TX_DATA_3RD_BD_RESERVED0_SHIFT      9
495 	u8 tunn_l4_hdr_start_offset_w /* For tunnel with IPv6+ext - Pointer to the tunnel L4 Header (in 2-byte WORDs) */;
496 	u8 tunn_hdr_size_w /* For tunnel with IPv6+ext - Total size of the Tunnel Header (in 2-byte WORDs) */;
497 };
498 
499 /*
500  * The third tx bd of a given packet
501  */
502 struct eth_tx_3rd_bd
503 {
504 	struct regpair addr /* Single continuous buffer */;
505 	__le16 nbytes /* Number of bytes in this BD. */;
506 	struct eth_tx_data_3rd_bd data /* Parsing information data. */;
507 };
508 
509 
510 /*
511  * Complementary information for the regular tx bd of a given packet.
512  */
513 struct eth_tx_data_bd
514 {
515 	__le16 reserved0;
516 	__le16 bitfields;
517 #define ETH_TX_DATA_BD_RESERVED1_MASK  0xFF
518 #define ETH_TX_DATA_BD_RESERVED1_SHIFT 0
519 #define ETH_TX_DATA_BD_START_BD_MASK   0x1 /* Should be 0 in all the BDs, except the first one. (for debug) */
520 #define ETH_TX_DATA_BD_START_BD_SHIFT  8
521 #define ETH_TX_DATA_BD_RESERVED2_MASK  0x7F
522 #define ETH_TX_DATA_BD_RESERVED2_SHIFT 9
523 	__le16 reserved3;
524 };
525 
526 /*
527  * The common regular TX BD ring element
528  */
529 struct eth_tx_bd
530 {
531 	struct regpair addr /* Single continuous buffer */;
532 	__le16 nbytes /* Number of bytes in this BD. */;
533 	struct eth_tx_data_bd data /* Complementary information. */;
534 };
535 
536 
537 union eth_tx_bd_types
538 {
539 	struct eth_tx_1st_bd first_bd /* The first tx bd of a given packet */;
540 	struct eth_tx_2nd_bd second_bd /* The second tx bd of a given packet */;
541 	struct eth_tx_3rd_bd third_bd /* The third tx bd of a given packet */;
542 	struct eth_tx_bd reg_bd /* The common non-special bd */;
543 };
544 
545 
546 
547 
548 
549 
550 /*
551  * Eth Tx Tunnel Type
552  */
553 enum eth_tx_tunn_type
554 {
555 	ETH_TX_TUNN_GENEVE /* GENEVE Tunnel. */,
556 	ETH_TX_TUNN_TTAG /* T-Tag Tunnel. */,
557 	ETH_TX_TUNN_GRE /* GRE Tunnel. */,
558 	ETH_TX_TUNN_VXLAN /* VXLAN Tunnel. */,
559 	MAX_ETH_TX_TUNN_TYPE
560 };
561 
562 
563 /*
564  * Ystorm Queue Zone
565  */
566 struct xstorm_eth_queue_zone
567 {
568 	struct coalescing_timeset int_coalescing_timeset /* Tx interrupt coalescing TimeSet */;
569 	u8 reserved[7];
570 };
571 
572 
573 /*
574  * ETH doorbell data
575  */
576 struct eth_db_data
577 {
578 	u8 params;
579 #define ETH_DB_DATA_DEST_MASK         0x3 /* destination of doorbell (use enum db_dest) */
580 #define ETH_DB_DATA_DEST_SHIFT        0
581 #define ETH_DB_DATA_AGG_CMD_MASK      0x3 /* aggregative command to CM (use enum db_agg_cmd_sel) */
582 #define ETH_DB_DATA_AGG_CMD_SHIFT     2
583 #define ETH_DB_DATA_BYPASS_EN_MASK    0x1 /* enable QM bypass */
584 #define ETH_DB_DATA_BYPASS_EN_SHIFT   4
585 #define ETH_DB_DATA_RESERVED_MASK     0x1
586 #define ETH_DB_DATA_RESERVED_SHIFT    5
587 #define ETH_DB_DATA_AGG_VAL_SEL_MASK  0x3 /* aggregative value selection */
588 #define ETH_DB_DATA_AGG_VAL_SEL_SHIFT 6
589 	u8 agg_flags /* bit for every DQ counter flags in CM context that DQ can increment */;
590 	__le16 bd_prod;
591 };
592 
593 #endif /* __ETH_COMMON__ */
594