1 /******************************************************************************
2 SPDX-License-Identifier: BSD-3-Clause
3
4 Copyright (c) 2001-2020, Intel Corporation
5 All rights reserved.
6
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
9
10 1. Redistributions of source code must retain the above copyright notice,
11 this list of conditions and the following disclaimer.
12
13 2. Redistributions in binary form must reproduce the above copyright
14 notice, this list of conditions and the following disclaimer in the
15 documentation and/or other materials provided with the distribution.
16
17 3. Neither the name of the Intel Corporation nor the names of its
18 contributors may be used to endorse or promote products derived from
19 this software without specific prior written permission.
20
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 POSSIBILITY OF SUCH DAMAGE.
32
33 ******************************************************************************/
34
35 #include "e1000_api.h"
36
37 static s32 e1000_wait_autoneg(struct e1000_hw *hw);
38 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
39 u16 *data, bool read, bool page_set);
40 static u32 e1000_get_phy_addr_for_hv_page(u32 page);
41 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
42 u16 *data, bool read);
43
44 /* Cable length tables */
45 static const u16 e1000_m88_cable_length_table[] = {
46 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
47 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
48 (sizeof(e1000_m88_cable_length_table) / \
49 sizeof(e1000_m88_cable_length_table[0]))
50
51 static const u16 e1000_igp_2_cable_length_table[] = {
52 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
53 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
54 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
55 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
56 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
57 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
58 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
59 124};
60 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
61 (sizeof(e1000_igp_2_cable_length_table) / \
62 sizeof(e1000_igp_2_cable_length_table[0]))
63
64 /**
65 * e1000_init_phy_ops_generic - Initialize PHY function pointers
66 * @hw: pointer to the HW structure
67 *
68 * Setups up the function pointers to no-op functions
69 **/
e1000_init_phy_ops_generic(struct e1000_hw * hw)70 void e1000_init_phy_ops_generic(struct e1000_hw *hw)
71 {
72 struct e1000_phy_info *phy = &hw->phy;
73 DEBUGFUNC("e1000_init_phy_ops_generic");
74
75 /* Initialize function pointers */
76 phy->ops.init_params = e1000_null_ops_generic;
77 phy->ops.acquire = e1000_null_ops_generic;
78 phy->ops.check_polarity = e1000_null_ops_generic;
79 phy->ops.check_reset_block = e1000_null_ops_generic;
80 phy->ops.commit = e1000_null_ops_generic;
81 phy->ops.force_speed_duplex = e1000_null_ops_generic;
82 phy->ops.get_cfg_done = e1000_null_ops_generic;
83 phy->ops.get_cable_length = e1000_null_ops_generic;
84 phy->ops.get_info = e1000_null_ops_generic;
85 phy->ops.set_page = e1000_null_set_page;
86 phy->ops.read_reg = e1000_null_read_reg;
87 phy->ops.read_reg_locked = e1000_null_read_reg;
88 phy->ops.read_reg_page = e1000_null_read_reg;
89 phy->ops.release = e1000_null_phy_generic;
90 phy->ops.reset = e1000_null_ops_generic;
91 phy->ops.set_d0_lplu_state = e1000_null_lplu_state;
92 phy->ops.set_d3_lplu_state = e1000_null_lplu_state;
93 phy->ops.write_reg = e1000_null_write_reg;
94 phy->ops.write_reg_locked = e1000_null_write_reg;
95 phy->ops.write_reg_page = e1000_null_write_reg;
96 phy->ops.power_up = e1000_null_phy_generic;
97 phy->ops.power_down = e1000_null_phy_generic;
98 phy->ops.read_i2c_byte = e1000_read_i2c_byte_null;
99 phy->ops.write_i2c_byte = e1000_write_i2c_byte_null;
100 phy->ops.cfg_on_link_up = e1000_null_ops_generic;
101 }
102
103 /**
104 * e1000_null_set_page - No-op function, return 0
105 * @hw: pointer to the HW structure
106 * @data: dummy variable
107 **/
e1000_null_set_page(struct e1000_hw E1000_UNUSEDARG * hw,u16 E1000_UNUSEDARG data)108 s32 e1000_null_set_page(struct e1000_hw E1000_UNUSEDARG *hw,
109 u16 E1000_UNUSEDARG data)
110 {
111 DEBUGFUNC("e1000_null_set_page");
112 return E1000_SUCCESS;
113 }
114
115 /**
116 * e1000_null_read_reg - No-op function, return 0
117 * @hw: pointer to the HW structure
118 * @offset: dummy variable
119 * @data: dummy variable
120 **/
e1000_null_read_reg(struct e1000_hw E1000_UNUSEDARG * hw,u32 E1000_UNUSEDARG offset,u16 E1000_UNUSEDARG * data)121 s32 e1000_null_read_reg(struct e1000_hw E1000_UNUSEDARG *hw,
122 u32 E1000_UNUSEDARG offset, u16 E1000_UNUSEDARG *data)
123 {
124 DEBUGFUNC("e1000_null_read_reg");
125 return E1000_SUCCESS;
126 }
127
128 /**
129 * e1000_null_phy_generic - No-op function, return void
130 * @hw: pointer to the HW structure
131 **/
e1000_null_phy_generic(struct e1000_hw E1000_UNUSEDARG * hw)132 void e1000_null_phy_generic(struct e1000_hw E1000_UNUSEDARG *hw)
133 {
134 DEBUGFUNC("e1000_null_phy_generic");
135 return;
136 }
137
138 /**
139 * e1000_null_lplu_state - No-op function, return 0
140 * @hw: pointer to the HW structure
141 * @active: dummy variable
142 **/
e1000_null_lplu_state(struct e1000_hw E1000_UNUSEDARG * hw,bool E1000_UNUSEDARG active)143 s32 e1000_null_lplu_state(struct e1000_hw E1000_UNUSEDARG *hw,
144 bool E1000_UNUSEDARG active)
145 {
146 DEBUGFUNC("e1000_null_lplu_state");
147 return E1000_SUCCESS;
148 }
149
150 /**
151 * e1000_null_write_reg - No-op function, return 0
152 * @hw: pointer to the HW structure
153 * @offset: dummy variable
154 * @data: dummy variable
155 **/
e1000_null_write_reg(struct e1000_hw E1000_UNUSEDARG * hw,u32 E1000_UNUSEDARG offset,u16 E1000_UNUSEDARG data)156 s32 e1000_null_write_reg(struct e1000_hw E1000_UNUSEDARG *hw,
157 u32 E1000_UNUSEDARG offset, u16 E1000_UNUSEDARG data)
158 {
159 DEBUGFUNC("e1000_null_write_reg");
160 return E1000_SUCCESS;
161 }
162
163 /**
164 * e1000_read_i2c_byte_null - No-op function, return 0
165 * @hw: pointer to hardware structure
166 * @byte_offset: byte offset to write
167 * @dev_addr: device address
168 * @data: data value read
169 *
170 **/
e1000_read_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG * hw,u8 E1000_UNUSEDARG byte_offset,u8 E1000_UNUSEDARG dev_addr,u8 E1000_UNUSEDARG * data)171 s32 e1000_read_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw,
172 u8 E1000_UNUSEDARG byte_offset,
173 u8 E1000_UNUSEDARG dev_addr,
174 u8 E1000_UNUSEDARG *data)
175 {
176 DEBUGFUNC("e1000_read_i2c_byte_null");
177 return E1000_SUCCESS;
178 }
179
180 /**
181 * e1000_write_i2c_byte_null - No-op function, return 0
182 * @hw: pointer to hardware structure
183 * @byte_offset: byte offset to write
184 * @dev_addr: device address
185 * @data: data value to write
186 *
187 **/
e1000_write_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG * hw,u8 E1000_UNUSEDARG byte_offset,u8 E1000_UNUSEDARG dev_addr,u8 E1000_UNUSEDARG data)188 s32 e1000_write_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw,
189 u8 E1000_UNUSEDARG byte_offset,
190 u8 E1000_UNUSEDARG dev_addr,
191 u8 E1000_UNUSEDARG data)
192 {
193 DEBUGFUNC("e1000_write_i2c_byte_null");
194 return E1000_SUCCESS;
195 }
196
197 /**
198 * e1000_check_reset_block_generic - Check if PHY reset is blocked
199 * @hw: pointer to the HW structure
200 *
201 * Read the PHY management control register and check whether a PHY reset
202 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise
203 * return E1000_BLK_PHY_RESET (12).
204 **/
e1000_check_reset_block_generic(struct e1000_hw * hw)205 s32 e1000_check_reset_block_generic(struct e1000_hw *hw)
206 {
207 u32 manc;
208
209 DEBUGFUNC("e1000_check_reset_block");
210
211 manc = E1000_READ_REG(hw, E1000_MANC);
212
213 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
214 E1000_BLK_PHY_RESET : E1000_SUCCESS;
215 }
216
217 /**
218 * e1000_get_phy_id - Retrieve the PHY ID and revision
219 * @hw: pointer to the HW structure
220 *
221 * Reads the PHY registers and stores the PHY ID and possibly the PHY
222 * revision in the hardware structure.
223 **/
e1000_get_phy_id(struct e1000_hw * hw)224 s32 e1000_get_phy_id(struct e1000_hw *hw)
225 {
226 struct e1000_phy_info *phy = &hw->phy;
227 s32 ret_val = E1000_SUCCESS;
228 u16 phy_id;
229 u16 retry_count = 0;
230
231 DEBUGFUNC("e1000_get_phy_id");
232
233 if (!phy->ops.read_reg)
234 return E1000_SUCCESS;
235
236 while (retry_count < 2) {
237 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
238 if (ret_val)
239 return ret_val;
240
241 phy->id = (u32)(phy_id << 16);
242 usec_delay(20);
243 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
244 if (ret_val)
245 return ret_val;
246
247 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
248 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
249
250 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
251 return E1000_SUCCESS;
252
253 retry_count++;
254 }
255
256 return E1000_SUCCESS;
257 }
258
259 /**
260 * e1000_phy_reset_dsp_generic - Reset PHY DSP
261 * @hw: pointer to the HW structure
262 *
263 * Reset the digital signal processor.
264 **/
e1000_phy_reset_dsp_generic(struct e1000_hw * hw)265 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw)
266 {
267 s32 ret_val;
268
269 DEBUGFUNC("e1000_phy_reset_dsp_generic");
270
271 if (!hw->phy.ops.write_reg)
272 return E1000_SUCCESS;
273
274 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
275 if (ret_val)
276 return ret_val;
277
278 return hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
279 }
280
281 /**
282 * e1000_read_phy_reg_mdic - Read MDI control register
283 * @hw: pointer to the HW structure
284 * @offset: register offset to be read
285 * @data: pointer to the read data
286 *
287 * Reads the MDI control register in the PHY at offset and stores the
288 * information read to data.
289 **/
e1000_read_phy_reg_mdic(struct e1000_hw * hw,u32 offset,u16 * data)290 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
291 {
292 struct e1000_phy_info *phy = &hw->phy;
293 u32 i, mdic = 0;
294
295 DEBUGFUNC("e1000_read_phy_reg_mdic");
296
297 if (offset > MAX_PHY_REG_ADDRESS) {
298 DEBUGOUT1("PHY Address %d is out of range\n", offset);
299 return -E1000_ERR_PARAM;
300 }
301
302 /* Set up Op-code, Phy Address, and register offset in the MDI
303 * Control register. The MAC will take care of interfacing with the
304 * PHY to retrieve the desired data.
305 */
306 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
307 (phy->addr << E1000_MDIC_PHY_SHIFT) |
308 (E1000_MDIC_OP_READ));
309
310 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
311
312 /* Poll the ready bit to see if the MDI read completed
313 * Increasing the time out as testing showed failures with
314 * the lower time out
315 */
316 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
317 usec_delay_irq(50);
318 mdic = E1000_READ_REG(hw, E1000_MDIC);
319 if (mdic & E1000_MDIC_READY)
320 break;
321 }
322 if (!(mdic & E1000_MDIC_READY)) {
323 DEBUGOUT("MDI Read did not complete\n");
324 return -E1000_ERR_PHY;
325 }
326 if (mdic & E1000_MDIC_ERROR) {
327 DEBUGOUT("MDI Error\n");
328 return -E1000_ERR_PHY;
329 }
330 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {
331 DEBUGOUT2("MDI Read offset error - requested %d, returned %d\n",
332 offset,
333 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
334 return -E1000_ERR_PHY;
335 }
336 *data = (u16) mdic;
337
338 /* Allow some time after each MDIC transaction to avoid
339 * reading duplicate data in the next MDIC transaction.
340 */
341 if (hw->mac.type == e1000_pch2lan)
342 usec_delay_irq(100);
343
344 return E1000_SUCCESS;
345 }
346
347 /**
348 * e1000_write_phy_reg_mdic - Write MDI control register
349 * @hw: pointer to the HW structure
350 * @offset: register offset to write to
351 * @data: data to write to register at offset
352 *
353 * Writes data to MDI control register in the PHY at offset.
354 **/
e1000_write_phy_reg_mdic(struct e1000_hw * hw,u32 offset,u16 data)355 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
356 {
357 struct e1000_phy_info *phy = &hw->phy;
358 u32 i, mdic = 0;
359
360 DEBUGFUNC("e1000_write_phy_reg_mdic");
361
362 if (offset > MAX_PHY_REG_ADDRESS) {
363 DEBUGOUT1("PHY Address %d is out of range\n", offset);
364 return -E1000_ERR_PARAM;
365 }
366
367 /* Set up Op-code, Phy Address, and register offset in the MDI
368 * Control register. The MAC will take care of interfacing with the
369 * PHY to retrieve the desired data.
370 */
371 mdic = (((u32)data) |
372 (offset << E1000_MDIC_REG_SHIFT) |
373 (phy->addr << E1000_MDIC_PHY_SHIFT) |
374 (E1000_MDIC_OP_WRITE));
375
376 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
377
378 /* Poll the ready bit to see if the MDI read completed
379 * Increasing the time out as testing showed failures with
380 * the lower time out
381 */
382 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
383 usec_delay_irq(50);
384 mdic = E1000_READ_REG(hw, E1000_MDIC);
385 if (mdic & E1000_MDIC_READY)
386 break;
387 }
388 if (!(mdic & E1000_MDIC_READY)) {
389 DEBUGOUT("MDI Write did not complete\n");
390 return -E1000_ERR_PHY;
391 }
392 if (mdic & E1000_MDIC_ERROR) {
393 DEBUGOUT("MDI Error\n");
394 return -E1000_ERR_PHY;
395 }
396 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {
397 DEBUGOUT2("MDI Write offset error - requested %d, returned %d\n",
398 offset,
399 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
400 return -E1000_ERR_PHY;
401 }
402
403 /* Allow some time after each MDIC transaction to avoid
404 * reading duplicate data in the next MDIC transaction.
405 */
406 if (hw->mac.type == e1000_pch2lan)
407 usec_delay_irq(100);
408
409 return E1000_SUCCESS;
410 }
411
412 /**
413 * e1000_read_phy_reg_i2c - Read PHY register using i2c
414 * @hw: pointer to the HW structure
415 * @offset: register offset to be read
416 * @data: pointer to the read data
417 *
418 * Reads the PHY register at offset using the i2c interface and stores the
419 * retrieved information in data.
420 **/
e1000_read_phy_reg_i2c(struct e1000_hw * hw,u32 offset,u16 * data)421 s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)
422 {
423 struct e1000_phy_info *phy = &hw->phy;
424 u32 i, i2ccmd = 0;
425
426 DEBUGFUNC("e1000_read_phy_reg_i2c");
427
428 /* Set up Op-code, Phy Address, and register address in the I2CCMD
429 * register. The MAC will take care of interfacing with the
430 * PHY to retrieve the desired data.
431 */
432 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
433 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
434 (E1000_I2CCMD_OPCODE_READ));
435
436 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
437
438 /* Poll the ready bit to see if the I2C read completed */
439 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
440 usec_delay(50);
441 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
442 if (i2ccmd & E1000_I2CCMD_READY)
443 break;
444 }
445 if (!(i2ccmd & E1000_I2CCMD_READY)) {
446 DEBUGOUT("I2CCMD Read did not complete\n");
447 return -E1000_ERR_PHY;
448 }
449 if (i2ccmd & E1000_I2CCMD_ERROR) {
450 DEBUGOUT("I2CCMD Error bit set\n");
451 return -E1000_ERR_PHY;
452 }
453
454 /* Need to byte-swap the 16-bit value. */
455 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
456
457 return E1000_SUCCESS;
458 }
459
460 /**
461 * e1000_write_phy_reg_i2c - Write PHY register using i2c
462 * @hw: pointer to the HW structure
463 * @offset: register offset to write to
464 * @data: data to write at register offset
465 *
466 * Writes the data to PHY register at the offset using the i2c interface.
467 **/
e1000_write_phy_reg_i2c(struct e1000_hw * hw,u32 offset,u16 data)468 s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
469 {
470 struct e1000_phy_info *phy = &hw->phy;
471 u32 i, i2ccmd = 0;
472 u16 phy_data_swapped;
473
474 DEBUGFUNC("e1000_write_phy_reg_i2c");
475
476 /* Prevent overwriting SFP I2C EEPROM which is at A0 address.*/
477 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) {
478 DEBUGOUT1("PHY I2C Address %d is out of range.\n",
479 hw->phy.addr);
480 return -E1000_ERR_CONFIG;
481 }
482
483 /* Swap the data bytes for the I2C interface */
484 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
485
486 /* Set up Op-code, Phy Address, and register address in the I2CCMD
487 * register. The MAC will take care of interfacing with the
488 * PHY to retrieve the desired data.
489 */
490 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
491 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
492 E1000_I2CCMD_OPCODE_WRITE |
493 phy_data_swapped);
494
495 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
496
497 /* Poll the ready bit to see if the I2C read completed */
498 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
499 usec_delay(50);
500 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
501 if (i2ccmd & E1000_I2CCMD_READY)
502 break;
503 }
504 if (!(i2ccmd & E1000_I2CCMD_READY)) {
505 DEBUGOUT("I2CCMD Write did not complete\n");
506 return -E1000_ERR_PHY;
507 }
508 if (i2ccmd & E1000_I2CCMD_ERROR) {
509 DEBUGOUT("I2CCMD Error bit set\n");
510 return -E1000_ERR_PHY;
511 }
512
513 return E1000_SUCCESS;
514 }
515
516 /**
517 * e1000_read_sfp_data_byte - Reads SFP module data.
518 * @hw: pointer to the HW structure
519 * @offset: byte location offset to be read
520 * @data: read data buffer pointer
521 *
522 * Reads one byte from SFP module data stored
523 * in SFP resided EEPROM memory or SFP diagnostic area.
524 * Function should be called with
525 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
526 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
527 * access
528 **/
e1000_read_sfp_data_byte(struct e1000_hw * hw,u16 offset,u8 * data)529 s32 e1000_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data)
530 {
531 u32 i = 0;
532 u32 i2ccmd = 0;
533 u32 data_local = 0;
534
535 DEBUGFUNC("e1000_read_sfp_data_byte");
536
537 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
538 DEBUGOUT("I2CCMD command address exceeds upper limit\n");
539 return -E1000_ERR_PHY;
540 }
541
542 /* Set up Op-code, EEPROM Address,in the I2CCMD
543 * register. The MAC will take care of interfacing with the
544 * EEPROM to retrieve the desired data.
545 */
546 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
547 E1000_I2CCMD_OPCODE_READ);
548
549 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
550
551 /* Poll the ready bit to see if the I2C read completed */
552 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
553 usec_delay(50);
554 data_local = E1000_READ_REG(hw, E1000_I2CCMD);
555 if (data_local & E1000_I2CCMD_READY)
556 break;
557 }
558 if (!(data_local & E1000_I2CCMD_READY)) {
559 DEBUGOUT("I2CCMD Read did not complete\n");
560 return -E1000_ERR_PHY;
561 }
562 if (data_local & E1000_I2CCMD_ERROR) {
563 DEBUGOUT("I2CCMD Error bit set\n");
564 return -E1000_ERR_PHY;
565 }
566 *data = (u8) data_local & 0xFF;
567
568 return E1000_SUCCESS;
569 }
570
571 /**
572 * e1000_write_sfp_data_byte - Writes SFP module data.
573 * @hw: pointer to the HW structure
574 * @offset: byte location offset to write to
575 * @data: data to write
576 *
577 * Writes one byte to SFP module data stored
578 * in SFP resided EEPROM memory or SFP diagnostic area.
579 * Function should be called with
580 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
581 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
582 * access
583 **/
e1000_write_sfp_data_byte(struct e1000_hw * hw,u16 offset,u8 data)584 s32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data)
585 {
586 u32 i = 0;
587 u32 i2ccmd = 0;
588 u32 data_local = 0;
589
590 DEBUGFUNC("e1000_write_sfp_data_byte");
591
592 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
593 DEBUGOUT("I2CCMD command address exceeds upper limit\n");
594 return -E1000_ERR_PHY;
595 }
596 /* The programming interface is 16 bits wide
597 * so we need to read the whole word first
598 * then update appropriate byte lane and write
599 * the updated word back.
600 */
601 /* Set up Op-code, EEPROM Address,in the I2CCMD
602 * register. The MAC will take care of interfacing
603 * with an EEPROM to write the data given.
604 */
605 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
606 E1000_I2CCMD_OPCODE_READ);
607 /* Set a command to read single word */
608 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
609 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
610 usec_delay(50);
611 /* Poll the ready bit to see if lastly
612 * launched I2C operation completed
613 */
614 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
615 if (i2ccmd & E1000_I2CCMD_READY) {
616 /* Check if this is READ or WRITE phase */
617 if ((i2ccmd & E1000_I2CCMD_OPCODE_READ) ==
618 E1000_I2CCMD_OPCODE_READ) {
619 /* Write the selected byte
620 * lane and update whole word
621 */
622 data_local = i2ccmd & 0xFF00;
623 data_local |= (u32)data;
624 i2ccmd = ((offset <<
625 E1000_I2CCMD_REG_ADDR_SHIFT) |
626 E1000_I2CCMD_OPCODE_WRITE | data_local);
627 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
628 } else {
629 break;
630 }
631 }
632 }
633 if (!(i2ccmd & E1000_I2CCMD_READY)) {
634 DEBUGOUT("I2CCMD Write did not complete\n");
635 return -E1000_ERR_PHY;
636 }
637 if (i2ccmd & E1000_I2CCMD_ERROR) {
638 DEBUGOUT("I2CCMD Error bit set\n");
639 return -E1000_ERR_PHY;
640 }
641 return E1000_SUCCESS;
642 }
643
644 /**
645 * e1000_read_phy_reg_m88 - Read m88 PHY register
646 * @hw: pointer to the HW structure
647 * @offset: register offset to be read
648 * @data: pointer to the read data
649 *
650 * Acquires semaphore, if necessary, then reads the PHY register at offset
651 * and storing the retrieved information in data. Release any acquired
652 * semaphores before exiting.
653 **/
e1000_read_phy_reg_m88(struct e1000_hw * hw,u32 offset,u16 * data)654 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
655 {
656 s32 ret_val;
657
658 DEBUGFUNC("e1000_read_phy_reg_m88");
659
660 if (!hw->phy.ops.acquire)
661 return E1000_SUCCESS;
662
663 ret_val = hw->phy.ops.acquire(hw);
664 if (ret_val)
665 return ret_val;
666
667 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
668 data);
669
670 hw->phy.ops.release(hw);
671
672 return ret_val;
673 }
674
675 /**
676 * e1000_write_phy_reg_m88 - Write m88 PHY register
677 * @hw: pointer to the HW structure
678 * @offset: register offset to write to
679 * @data: data to write at register offset
680 *
681 * Acquires semaphore, if necessary, then writes the data to PHY register
682 * at the offset. Release any acquired semaphores before exiting.
683 **/
e1000_write_phy_reg_m88(struct e1000_hw * hw,u32 offset,u16 data)684 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
685 {
686 s32 ret_val;
687
688 DEBUGFUNC("e1000_write_phy_reg_m88");
689
690 if (!hw->phy.ops.acquire)
691 return E1000_SUCCESS;
692
693 ret_val = hw->phy.ops.acquire(hw);
694 if (ret_val)
695 return ret_val;
696
697 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
698 data);
699
700 hw->phy.ops.release(hw);
701
702 return ret_val;
703 }
704
705 /**
706 * e1000_set_page_igp - Set page as on IGP-like PHY(s)
707 * @hw: pointer to the HW structure
708 * @page: page to set (shifted left when necessary)
709 *
710 * Sets PHY page required for PHY register access. Assumes semaphore is
711 * already acquired. Note, this function sets phy.addr to 1 so the caller
712 * must set it appropriately (if necessary) after this function returns.
713 **/
e1000_set_page_igp(struct e1000_hw * hw,u16 page)714 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)
715 {
716 DEBUGFUNC("e1000_set_page_igp");
717
718 DEBUGOUT1("Setting page 0x%x\n", page);
719
720 hw->phy.addr = 1;
721
722 return e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);
723 }
724
725 /**
726 * __e1000_read_phy_reg_igp - Read igp PHY register
727 * @hw: pointer to the HW structure
728 * @offset: register offset to be read
729 * @data: pointer to the read data
730 * @locked: semaphore has already been acquired or not
731 *
732 * Acquires semaphore, if necessary, then reads the PHY register at offset
733 * and stores the retrieved information in data. Release any acquired
734 * semaphores before exiting.
735 **/
__e1000_read_phy_reg_igp(struct e1000_hw * hw,u32 offset,u16 * data,bool locked)736 static s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
737 bool locked)
738 {
739 s32 ret_val = E1000_SUCCESS;
740
741 DEBUGFUNC("__e1000_read_phy_reg_igp");
742
743 if (!locked) {
744 if (!hw->phy.ops.acquire)
745 return E1000_SUCCESS;
746
747 ret_val = hw->phy.ops.acquire(hw);
748 if (ret_val)
749 return ret_val;
750 }
751
752 if (offset > MAX_PHY_MULTI_PAGE_REG)
753 ret_val = e1000_write_phy_reg_mdic(hw,
754 IGP01E1000_PHY_PAGE_SELECT,
755 (u16)offset);
756 if (!ret_val)
757 ret_val = e1000_read_phy_reg_mdic(hw,
758 MAX_PHY_REG_ADDRESS & offset,
759 data);
760 if (!locked)
761 hw->phy.ops.release(hw);
762
763 return ret_val;
764 }
765
766 /**
767 * e1000_read_phy_reg_igp - Read igp PHY register
768 * @hw: pointer to the HW structure
769 * @offset: register offset to be read
770 * @data: pointer to the read data
771 *
772 * Acquires semaphore then reads the PHY register at offset and stores the
773 * retrieved information in data.
774 * Release the acquired semaphore before exiting.
775 **/
e1000_read_phy_reg_igp(struct e1000_hw * hw,u32 offset,u16 * data)776 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
777 {
778 return __e1000_read_phy_reg_igp(hw, offset, data, false);
779 }
780
781 /**
782 * e1000_read_phy_reg_igp_locked - Read igp PHY register
783 * @hw: pointer to the HW structure
784 * @offset: register offset to be read
785 * @data: pointer to the read data
786 *
787 * Reads the PHY register at offset and stores the retrieved information
788 * in data. Assumes semaphore already acquired.
789 **/
e1000_read_phy_reg_igp_locked(struct e1000_hw * hw,u32 offset,u16 * data)790 s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
791 {
792 return __e1000_read_phy_reg_igp(hw, offset, data, true);
793 }
794
795 /**
796 * e1000_write_phy_reg_igp - Write igp PHY register
797 * @hw: pointer to the HW structure
798 * @offset: register offset to write to
799 * @data: data to write at register offset
800 * @locked: semaphore has already been acquired or not
801 *
802 * Acquires semaphore, if necessary, then writes the data to PHY register
803 * at the offset. Release any acquired semaphores before exiting.
804 **/
__e1000_write_phy_reg_igp(struct e1000_hw * hw,u32 offset,u16 data,bool locked)805 static s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
806 bool locked)
807 {
808 s32 ret_val = E1000_SUCCESS;
809
810 DEBUGFUNC("e1000_write_phy_reg_igp");
811
812 if (!locked) {
813 if (!hw->phy.ops.acquire)
814 return E1000_SUCCESS;
815
816 ret_val = hw->phy.ops.acquire(hw);
817 if (ret_val)
818 return ret_val;
819 }
820
821 if (offset > MAX_PHY_MULTI_PAGE_REG)
822 ret_val = e1000_write_phy_reg_mdic(hw,
823 IGP01E1000_PHY_PAGE_SELECT,
824 (u16)offset);
825 if (!ret_val)
826 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS &
827 offset,
828 data);
829 if (!locked)
830 hw->phy.ops.release(hw);
831
832 return ret_val;
833 }
834
835 /**
836 * e1000_write_phy_reg_igp - Write igp PHY register
837 * @hw: pointer to the HW structure
838 * @offset: register offset to write to
839 * @data: data to write at register offset
840 *
841 * Acquires semaphore then writes the data to PHY register
842 * at the offset. Release any acquired semaphores before exiting.
843 **/
e1000_write_phy_reg_igp(struct e1000_hw * hw,u32 offset,u16 data)844 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
845 {
846 return __e1000_write_phy_reg_igp(hw, offset, data, false);
847 }
848
849 /**
850 * e1000_write_phy_reg_igp_locked - Write igp PHY register
851 * @hw: pointer to the HW structure
852 * @offset: register offset to write to
853 * @data: data to write at register offset
854 *
855 * Writes the data to PHY register at the offset.
856 * Assumes semaphore already acquired.
857 **/
e1000_write_phy_reg_igp_locked(struct e1000_hw * hw,u32 offset,u16 data)858 s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
859 {
860 return __e1000_write_phy_reg_igp(hw, offset, data, true);
861 }
862
863 /**
864 * __e1000_read_kmrn_reg - Read kumeran register
865 * @hw: pointer to the HW structure
866 * @offset: register offset to be read
867 * @data: pointer to the read data
868 * @locked: semaphore has already been acquired or not
869 *
870 * Acquires semaphore, if necessary. Then reads the PHY register at offset
871 * using the kumeran interface. The information retrieved is stored in data.
872 * Release any acquired semaphores before exiting.
873 **/
__e1000_read_kmrn_reg(struct e1000_hw * hw,u32 offset,u16 * data,bool locked)874 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
875 bool locked)
876 {
877 u32 kmrnctrlsta;
878
879 DEBUGFUNC("__e1000_read_kmrn_reg");
880
881 if (!locked) {
882 s32 ret_val = E1000_SUCCESS;
883
884 if (!hw->phy.ops.acquire)
885 return E1000_SUCCESS;
886
887 ret_val = hw->phy.ops.acquire(hw);
888 if (ret_val)
889 return ret_val;
890 }
891
892 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
893 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
894 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
895 E1000_WRITE_FLUSH(hw);
896
897 usec_delay(2);
898
899 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
900 *data = (u16)kmrnctrlsta;
901
902 if (!locked)
903 hw->phy.ops.release(hw);
904
905 return E1000_SUCCESS;
906 }
907
908 /**
909 * e1000_read_kmrn_reg_generic - Read kumeran register
910 * @hw: pointer to the HW structure
911 * @offset: register offset to be read
912 * @data: pointer to the read data
913 *
914 * Acquires semaphore then reads the PHY register at offset using the
915 * kumeran interface. The information retrieved is stored in data.
916 * Release the acquired semaphore before exiting.
917 **/
e1000_read_kmrn_reg_generic(struct e1000_hw * hw,u32 offset,u16 * data)918 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data)
919 {
920 return __e1000_read_kmrn_reg(hw, offset, data, false);
921 }
922
923 /**
924 * e1000_read_kmrn_reg_locked - Read kumeran register
925 * @hw: pointer to the HW structure
926 * @offset: register offset to be read
927 * @data: pointer to the read data
928 *
929 * Reads the PHY register at offset using the kumeran interface. The
930 * information retrieved is stored in data.
931 * Assumes semaphore already acquired.
932 **/
e1000_read_kmrn_reg_locked(struct e1000_hw * hw,u32 offset,u16 * data)933 s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
934 {
935 return __e1000_read_kmrn_reg(hw, offset, data, true);
936 }
937
938 /**
939 * __e1000_write_kmrn_reg - Write kumeran register
940 * @hw: pointer to the HW structure
941 * @offset: register offset to write to
942 * @data: data to write at register offset
943 * @locked: semaphore has already been acquired or not
944 *
945 * Acquires semaphore, if necessary. Then write the data to PHY register
946 * at the offset using the kumeran interface. Release any acquired semaphores
947 * before exiting.
948 **/
__e1000_write_kmrn_reg(struct e1000_hw * hw,u32 offset,u16 data,bool locked)949 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
950 bool locked)
951 {
952 u32 kmrnctrlsta;
953
954 DEBUGFUNC("e1000_write_kmrn_reg_generic");
955
956 if (!locked) {
957 s32 ret_val = E1000_SUCCESS;
958
959 if (!hw->phy.ops.acquire)
960 return E1000_SUCCESS;
961
962 ret_val = hw->phy.ops.acquire(hw);
963 if (ret_val)
964 return ret_val;
965 }
966
967 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
968 E1000_KMRNCTRLSTA_OFFSET) | data;
969 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
970 E1000_WRITE_FLUSH(hw);
971
972 usec_delay(2);
973
974 if (!locked)
975 hw->phy.ops.release(hw);
976
977 return E1000_SUCCESS;
978 }
979
980 /**
981 * e1000_write_kmrn_reg_generic - Write kumeran register
982 * @hw: pointer to the HW structure
983 * @offset: register offset to write to
984 * @data: data to write at register offset
985 *
986 * Acquires semaphore then writes the data to the PHY register at the offset
987 * using the kumeran interface. Release the acquired semaphore before exiting.
988 **/
e1000_write_kmrn_reg_generic(struct e1000_hw * hw,u32 offset,u16 data)989 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data)
990 {
991 return __e1000_write_kmrn_reg(hw, offset, data, false);
992 }
993
994 /**
995 * e1000_write_kmrn_reg_locked - Write kumeran register
996 * @hw: pointer to the HW structure
997 * @offset: register offset to write to
998 * @data: data to write at register offset
999 *
1000 * Write the data to PHY register at the offset using the kumeran interface.
1001 * Assumes semaphore already acquired.
1002 **/
e1000_write_kmrn_reg_locked(struct e1000_hw * hw,u32 offset,u16 data)1003 s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
1004 {
1005 return __e1000_write_kmrn_reg(hw, offset, data, true);
1006 }
1007
1008 /**
1009 * e1000_set_master_slave_mode - Setup PHY for Master/slave mode
1010 * @hw: pointer to the HW structure
1011 *
1012 * Sets up Master/slave mode
1013 **/
e1000_set_master_slave_mode(struct e1000_hw * hw)1014 static s32 e1000_set_master_slave_mode(struct e1000_hw *hw)
1015 {
1016 s32 ret_val;
1017 u16 phy_data;
1018
1019 /* Resolve Master/Slave mode */
1020 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);
1021 if (ret_val)
1022 return ret_val;
1023
1024 /* load defaults for future use */
1025 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
1026 ((phy_data & CR_1000T_MS_VALUE) ?
1027 e1000_ms_force_master :
1028 e1000_ms_force_slave) : e1000_ms_auto;
1029
1030 switch (hw->phy.ms_type) {
1031 case e1000_ms_force_master:
1032 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1033 break;
1034 case e1000_ms_force_slave:
1035 phy_data |= CR_1000T_MS_ENABLE;
1036 phy_data &= ~(CR_1000T_MS_VALUE);
1037 break;
1038 case e1000_ms_auto:
1039 phy_data &= ~CR_1000T_MS_ENABLE;
1040 break;
1041 default:
1042 break;
1043 }
1044
1045 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);
1046 }
1047
1048 /**
1049 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
1050 * @hw: pointer to the HW structure
1051 *
1052 * Sets up Carrier-sense on Transmit and downshift values.
1053 **/
e1000_copper_link_setup_82577(struct e1000_hw * hw)1054 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
1055 {
1056 s32 ret_val;
1057 u16 phy_data;
1058
1059 DEBUGFUNC("e1000_copper_link_setup_82577");
1060
1061 if (hw->phy.type == e1000_phy_82580) {
1062 ret_val = hw->phy.ops.reset(hw);
1063 if (ret_val) {
1064 DEBUGOUT("Error resetting the PHY.\n");
1065 return ret_val;
1066 }
1067 }
1068
1069 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1070 ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data);
1071 if (ret_val)
1072 return ret_val;
1073
1074 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
1075
1076 /* Enable downshift */
1077 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
1078
1079 ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data);
1080 if (ret_val)
1081 return ret_val;
1082
1083 /* Set MDI/MDIX mode */
1084 ret_val = hw->phy.ops.read_reg(hw, I82577_PHY_CTRL_2, &phy_data);
1085 if (ret_val)
1086 return ret_val;
1087 phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK;
1088 /* Options:
1089 * 0 - Auto (default)
1090 * 1 - MDI mode
1091 * 2 - MDI-X mode
1092 */
1093 switch (hw->phy.mdix) {
1094 case 1:
1095 break;
1096 case 2:
1097 phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX;
1098 break;
1099 case 0:
1100 /* FALLTHROUGH */
1101 default:
1102 phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX;
1103 break;
1104 }
1105 ret_val = hw->phy.ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data);
1106 if (ret_val)
1107 return ret_val;
1108
1109 return e1000_set_master_slave_mode(hw);
1110 }
1111
1112 /**
1113 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link
1114 * @hw: pointer to the HW structure
1115 *
1116 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
1117 * and downshift values are set also.
1118 **/
e1000_copper_link_setup_m88(struct e1000_hw * hw)1119 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw)
1120 {
1121 struct e1000_phy_info *phy = &hw->phy;
1122 s32 ret_val;
1123 u16 phy_data;
1124
1125 DEBUGFUNC("e1000_copper_link_setup_m88");
1126
1127
1128 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1129 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1130 if (ret_val)
1131 return ret_val;
1132
1133 /* For BM PHY this bit is downshift enable */
1134 if (phy->type != e1000_phy_bm)
1135 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1136
1137 /* Options:
1138 * MDI/MDI-X = 0 (default)
1139 * 0 - Auto for all speeds
1140 * 1 - MDI mode
1141 * 2 - MDI-X mode
1142 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1143 */
1144 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1145
1146 switch (phy->mdix) {
1147 case 1:
1148 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1149 break;
1150 case 2:
1151 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1152 break;
1153 case 3:
1154 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1155 break;
1156 case 0:
1157 /* FALLTHROUGH */
1158 default:
1159 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1160 break;
1161 }
1162
1163 /* Options:
1164 * disable_polarity_correction = 0 (default)
1165 * Automatic Correction for Reversed Cable Polarity
1166 * 0 - Disabled
1167 * 1 - Enabled
1168 */
1169 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1170 if (phy->disable_polarity_correction)
1171 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1172
1173 /* Enable downshift on BM (disabled by default) */
1174 if (phy->type == e1000_phy_bm) {
1175 /* For 82574/82583, first disable then enable downshift */
1176 if (phy->id == BME1000_E_PHY_ID_R2) {
1177 phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT;
1178 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1179 phy_data);
1180 if (ret_val)
1181 return ret_val;
1182 /* Commit the changes. */
1183 ret_val = phy->ops.commit(hw);
1184 if (ret_val) {
1185 DEBUGOUT("Error committing the PHY changes\n");
1186 return ret_val;
1187 }
1188 }
1189
1190 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
1191 }
1192
1193 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1194 if (ret_val)
1195 return ret_val;
1196
1197 if ((phy->type == e1000_phy_m88) &&
1198 (phy->revision < E1000_REVISION_4) &&
1199 (phy->id != BME1000_E_PHY_ID_R2)) {
1200 /* Force TX_CLK in the Extended PHY Specific Control Register
1201 * to 25MHz clock.
1202 */
1203 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1204 &phy_data);
1205 if (ret_val)
1206 return ret_val;
1207
1208 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1209
1210 if ((phy->revision == E1000_REVISION_2) &&
1211 (phy->id == M88E1111_I_PHY_ID)) {
1212 /* 82573L PHY - set the downshift counter to 5x. */
1213 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
1214 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1215 } else {
1216 /* Configure Master and Slave downshift values */
1217 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1218 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1219 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1220 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1221 }
1222 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1223 phy_data);
1224 if (ret_val)
1225 return ret_val;
1226 }
1227
1228 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
1229 /* Set PHY page 0, register 29 to 0x0003 */
1230 ret_val = phy->ops.write_reg(hw, 29, 0x0003);
1231 if (ret_val)
1232 return ret_val;
1233
1234 /* Set PHY page 0, register 30 to 0x0000 */
1235 ret_val = phy->ops.write_reg(hw, 30, 0x0000);
1236 if (ret_val)
1237 return ret_val;
1238 }
1239
1240 /* Commit the changes. */
1241 ret_val = phy->ops.commit(hw);
1242 if (ret_val) {
1243 DEBUGOUT("Error committing the PHY changes\n");
1244 return ret_val;
1245 }
1246
1247 if (phy->type == e1000_phy_82578) {
1248 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1249 &phy_data);
1250 if (ret_val)
1251 return ret_val;
1252
1253 /* 82578 PHY - set the downshift count to 1x. */
1254 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
1255 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
1256 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1257 phy_data);
1258 if (ret_val)
1259 return ret_val;
1260 }
1261
1262 return E1000_SUCCESS;
1263 }
1264
1265 /**
1266 * e1000_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link
1267 * @hw: pointer to the HW structure
1268 *
1269 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's.
1270 * Also enables and sets the downshift parameters.
1271 **/
e1000_copper_link_setup_m88_gen2(struct e1000_hw * hw)1272 s32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw)
1273 {
1274 struct e1000_phy_info *phy = &hw->phy;
1275 s32 ret_val;
1276 u16 phy_data;
1277
1278 DEBUGFUNC("e1000_copper_link_setup_m88_gen2");
1279
1280
1281 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1282 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1283 if (ret_val)
1284 return ret_val;
1285
1286 /* Options:
1287 * MDI/MDI-X = 0 (default)
1288 * 0 - Auto for all speeds
1289 * 1 - MDI mode
1290 * 2 - MDI-X mode
1291 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1292 */
1293 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1294
1295 switch (phy->mdix) {
1296 case 1:
1297 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1298 break;
1299 case 2:
1300 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1301 break;
1302 case 3:
1303 /* M88E1112 does not support this mode) */
1304 if (phy->id != M88E1112_E_PHY_ID) {
1305 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1306 break;
1307 }
1308 /* FALLTHROUGH */
1309 case 0:
1310 /* FALLTHROUGH */
1311 default:
1312 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1313 break;
1314 }
1315
1316 /* Options:
1317 * disable_polarity_correction = 0 (default)
1318 * Automatic Correction for Reversed Cable Polarity
1319 * 0 - Disabled
1320 * 1 - Enabled
1321 */
1322 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1323 if (phy->disable_polarity_correction)
1324 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1325
1326 /* Enable downshift and setting it to X6 */
1327 if (phy->id == M88E1543_E_PHY_ID) {
1328 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_ENABLE;
1329 ret_val =
1330 phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1331 if (ret_val)
1332 return ret_val;
1333
1334 ret_val = phy->ops.commit(hw);
1335 if (ret_val) {
1336 DEBUGOUT("Error committing the PHY changes\n");
1337 return ret_val;
1338 }
1339 }
1340
1341 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK;
1342 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X;
1343 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE;
1344
1345 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1346 if (ret_val)
1347 return ret_val;
1348
1349 /* Commit the changes. */
1350 ret_val = phy->ops.commit(hw);
1351 if (ret_val) {
1352 DEBUGOUT("Error committing the PHY changes\n");
1353 return ret_val;
1354 }
1355
1356 ret_val = e1000_set_master_slave_mode(hw);
1357 if (ret_val)
1358 return ret_val;
1359
1360 return E1000_SUCCESS;
1361 }
1362
1363 /**
1364 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link
1365 * @hw: pointer to the HW structure
1366 *
1367 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
1368 * igp PHY's.
1369 **/
e1000_copper_link_setup_igp(struct e1000_hw * hw)1370 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw)
1371 {
1372 struct e1000_phy_info *phy = &hw->phy;
1373 s32 ret_val;
1374 u16 data;
1375
1376 DEBUGFUNC("e1000_copper_link_setup_igp");
1377
1378
1379 ret_val = hw->phy.ops.reset(hw);
1380 if (ret_val) {
1381 DEBUGOUT("Error resetting the PHY.\n");
1382 return ret_val;
1383 }
1384
1385 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
1386 * timeout issues when LFS is enabled.
1387 */
1388 msec_delay(100);
1389
1390 /* The NVM settings will configure LPLU in D3 for
1391 * non-IGP1 PHYs.
1392 */
1393 if (phy->type == e1000_phy_igp) {
1394 /* disable lplu d3 during driver init */
1395 ret_val = hw->phy.ops.set_d3_lplu_state(hw, false);
1396 if (ret_val) {
1397 DEBUGOUT("Error Disabling LPLU D3\n");
1398 return ret_val;
1399 }
1400 }
1401
1402 /* disable lplu d0 during driver init */
1403 if (hw->phy.ops.set_d0_lplu_state) {
1404 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false);
1405 if (ret_val) {
1406 DEBUGOUT("Error Disabling LPLU D0\n");
1407 return ret_val;
1408 }
1409 }
1410 /* Configure mdi-mdix settings */
1411 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
1412 if (ret_val)
1413 return ret_val;
1414
1415 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1416
1417 switch (phy->mdix) {
1418 case 1:
1419 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1420 break;
1421 case 2:
1422 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1423 break;
1424 case 0:
1425 /* FALLTHROUGH */
1426 default:
1427 data |= IGP01E1000_PSCR_AUTO_MDIX;
1428 break;
1429 }
1430 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
1431 if (ret_val)
1432 return ret_val;
1433
1434 /* set auto-master slave resolution settings */
1435 if (hw->mac.autoneg) {
1436 /* when autonegotiation advertisement is only 1000Mbps then we
1437 * should disable SmartSpeed and enable Auto MasterSlave
1438 * resolution as hardware default.
1439 */
1440 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
1441 /* Disable SmartSpeed */
1442 ret_val = phy->ops.read_reg(hw,
1443 IGP01E1000_PHY_PORT_CONFIG,
1444 &data);
1445 if (ret_val)
1446 return ret_val;
1447
1448 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1449 ret_val = phy->ops.write_reg(hw,
1450 IGP01E1000_PHY_PORT_CONFIG,
1451 data);
1452 if (ret_val)
1453 return ret_val;
1454
1455 /* Set auto Master/Slave resolution process */
1456 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1457 if (ret_val)
1458 return ret_val;
1459
1460 data &= ~CR_1000T_MS_ENABLE;
1461 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1462 if (ret_val)
1463 return ret_val;
1464 }
1465
1466 ret_val = e1000_set_master_slave_mode(hw);
1467 }
1468
1469 return ret_val;
1470 }
1471
1472 /**
1473 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
1474 * @hw: pointer to the HW structure
1475 *
1476 * Reads the MII auto-neg advertisement register and/or the 1000T control
1477 * register and if the PHY is already setup for auto-negotiation, then
1478 * return successful. Otherwise, setup advertisement and flow control to
1479 * the appropriate values for the wanted auto-negotiation.
1480 **/
e1000_phy_setup_autoneg(struct e1000_hw * hw)1481 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1482 {
1483 struct e1000_phy_info *phy = &hw->phy;
1484 s32 ret_val;
1485 u16 mii_autoneg_adv_reg;
1486 u16 mii_1000t_ctrl_reg = 0;
1487
1488 DEBUGFUNC("e1000_phy_setup_autoneg");
1489
1490 phy->autoneg_advertised &= phy->autoneg_mask;
1491
1492 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1493 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1494 if (ret_val)
1495 return ret_val;
1496
1497 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1498 /* Read the MII 1000Base-T Control Register (Address 9). */
1499 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
1500 &mii_1000t_ctrl_reg);
1501 if (ret_val)
1502 return ret_val;
1503 }
1504
1505 /* Need to parse both autoneg_advertised and fc and set up
1506 * the appropriate PHY registers. First we will parse for
1507 * autoneg_advertised software override. Since we can advertise
1508 * a plethora of combinations, we need to check each bit
1509 * individually.
1510 */
1511
1512 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1513 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1514 * the 1000Base-T Control Register (Address 9).
1515 */
1516 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
1517 NWAY_AR_100TX_HD_CAPS |
1518 NWAY_AR_10T_FD_CAPS |
1519 NWAY_AR_10T_HD_CAPS);
1520 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
1521
1522 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);
1523
1524 /* Do we want to advertise 10 Mb Half Duplex? */
1525 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
1526 DEBUGOUT("Advertise 10mb Half duplex\n");
1527 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1528 }
1529
1530 /* Do we want to advertise 10 Mb Full Duplex? */
1531 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
1532 DEBUGOUT("Advertise 10mb Full duplex\n");
1533 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1534 }
1535
1536 /* Do we want to advertise 100 Mb Half Duplex? */
1537 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
1538 DEBUGOUT("Advertise 100mb Half duplex\n");
1539 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1540 }
1541
1542 /* Do we want to advertise 100 Mb Full Duplex? */
1543 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
1544 DEBUGOUT("Advertise 100mb Full duplex\n");
1545 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1546 }
1547
1548 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1549 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1550 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n");
1551
1552 /* Do we want to advertise 1000 Mb Full Duplex? */
1553 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1554 DEBUGOUT("Advertise 1000mb Full duplex\n");
1555 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1556 }
1557
1558 /* Check for a software override of the flow control settings, and
1559 * setup the PHY advertisement registers accordingly. If
1560 * auto-negotiation is enabled, then software will have to set the
1561 * "PAUSE" bits to the correct value in the Auto-Negotiation
1562 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1563 * negotiation.
1564 *
1565 * The possible values of the "fc" parameter are:
1566 * 0: Flow control is completely disabled
1567 * 1: Rx flow control is enabled (we can receive pause frames
1568 * but not send pause frames).
1569 * 2: Tx flow control is enabled (we can send pause frames
1570 * but we do not support receiving pause frames).
1571 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1572 * other: No software override. The flow control configuration
1573 * in the EEPROM is used.
1574 */
1575 switch (hw->fc.current_mode) {
1576 case e1000_fc_none:
1577 /* Flow control (Rx & Tx) is completely disabled by a
1578 * software over-ride.
1579 */
1580 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1581 break;
1582 case e1000_fc_rx_pause:
1583 /* Rx Flow control is enabled, and Tx Flow control is
1584 * disabled, by a software over-ride.
1585 *
1586 * Since there really isn't a way to advertise that we are
1587 * capable of Rx Pause ONLY, we will advertise that we
1588 * support both symmetric and asymmetric Rx PAUSE. Later
1589 * (in e1000_config_fc_after_link_up) we will disable the
1590 * hw's ability to send PAUSE frames.
1591 */
1592 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1593 break;
1594 case e1000_fc_tx_pause:
1595 /* Tx Flow control is enabled, and Rx Flow control is
1596 * disabled, by a software over-ride.
1597 */
1598 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1599 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1600 break;
1601 case e1000_fc_full:
1602 /* Flow control (both Rx and Tx) is enabled by a software
1603 * over-ride.
1604 */
1605 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1606 break;
1607 default:
1608 DEBUGOUT("Flow control param set incorrectly\n");
1609 return -E1000_ERR_CONFIG;
1610 }
1611
1612 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1613 if (ret_val)
1614 return ret_val;
1615
1616 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1617
1618 if (phy->autoneg_mask & ADVERTISE_1000_FULL)
1619 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,
1620 mii_1000t_ctrl_reg);
1621
1622 return ret_val;
1623 }
1624
1625 /**
1626 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1627 * @hw: pointer to the HW structure
1628 *
1629 * Performs initial bounds checking on autoneg advertisement parameter, then
1630 * configure to advertise the full capability. Setup the PHY to autoneg
1631 * and restart the negotiation process between the link partner. If
1632 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1633 **/
e1000_copper_link_autoneg(struct e1000_hw * hw)1634 s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1635 {
1636 struct e1000_phy_info *phy = &hw->phy;
1637 s32 ret_val;
1638 u16 phy_ctrl;
1639
1640 DEBUGFUNC("e1000_copper_link_autoneg");
1641
1642 /* Perform some bounds checking on the autoneg advertisement
1643 * parameter.
1644 */
1645 phy->autoneg_advertised &= phy->autoneg_mask;
1646
1647 /* If autoneg_advertised is zero, we assume it was not defaulted
1648 * by the calling code so we set to advertise full capability.
1649 */
1650 if (!phy->autoneg_advertised)
1651 phy->autoneg_advertised = phy->autoneg_mask;
1652
1653 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1654 ret_val = e1000_phy_setup_autoneg(hw);
1655 if (ret_val) {
1656 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1657 return ret_val;
1658 }
1659 DEBUGOUT("Restarting Auto-Neg\n");
1660
1661 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1662 * the Auto Neg Restart bit in the PHY control register.
1663 */
1664 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
1665 if (ret_val)
1666 return ret_val;
1667
1668 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1669 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
1670 if (ret_val)
1671 return ret_val;
1672
1673 /* Does the user want to wait for Auto-Neg to complete here, or
1674 * check at a later time (for example, callback routine).
1675 */
1676 if (phy->autoneg_wait_to_complete) {
1677 ret_val = e1000_wait_autoneg(hw);
1678 if (ret_val) {
1679 DEBUGOUT("Error while waiting for autoneg to complete\n");
1680 return ret_val;
1681 }
1682 }
1683
1684 hw->mac.get_link_status = true;
1685
1686 return ret_val;
1687 }
1688
1689 /**
1690 * e1000_setup_copper_link_generic - Configure copper link settings
1691 * @hw: pointer to the HW structure
1692 *
1693 * Calls the appropriate function to configure the link for auto-neg or forced
1694 * speed and duplex. Then we check for link, once link is established calls
1695 * to configure collision distance and flow control are called. If link is
1696 * not established, we return -E1000_ERR_PHY (-2).
1697 **/
e1000_setup_copper_link_generic(struct e1000_hw * hw)1698 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw)
1699 {
1700 s32 ret_val;
1701 bool link = true;
1702
1703 DEBUGFUNC("e1000_setup_copper_link_generic");
1704
1705 if (hw->mac.autoneg) {
1706 /* Setup autoneg and flow control advertisement and perform
1707 * autonegotiation.
1708 */
1709 ret_val = e1000_copper_link_autoneg(hw);
1710 if (ret_val)
1711 return ret_val;
1712 } else {
1713 /* PHY will be set to 10H, 10F, 100H or 100F
1714 * depending on user settings.
1715 */
1716 DEBUGOUT("Forcing Speed and Duplex\n");
1717 ret_val = hw->phy.ops.force_speed_duplex(hw);
1718 if (ret_val) {
1719 DEBUGOUT("Error Forcing Speed and Duplex\n");
1720 return ret_val;
1721 }
1722 }
1723
1724 /* Check link status. Wait up to 100 microseconds for link to become
1725 * valid.
1726 */
1727 ret_val = e1000_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1728 &link);
1729 if (ret_val)
1730 return ret_val;
1731
1732 if (link) {
1733 DEBUGOUT("Valid link established!!!\n");
1734 hw->mac.ops.config_collision_dist(hw);
1735 ret_val = e1000_config_fc_after_link_up_generic(hw);
1736 } else {
1737 DEBUGOUT("Unable to establish link!!!\n");
1738 }
1739
1740 return ret_val;
1741 }
1742
1743 /**
1744 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1745 * @hw: pointer to the HW structure
1746 *
1747 * Calls the PHY setup function to force speed and duplex. Clears the
1748 * auto-crossover to force MDI manually. Waits for link and returns
1749 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1750 **/
e1000_phy_force_speed_duplex_igp(struct e1000_hw * hw)1751 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1752 {
1753 struct e1000_phy_info *phy = &hw->phy;
1754 s32 ret_val;
1755 u16 phy_data;
1756 bool link;
1757
1758 DEBUGFUNC("e1000_phy_force_speed_duplex_igp");
1759
1760 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1761 if (ret_val)
1762 return ret_val;
1763
1764 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1765
1766 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1767 if (ret_val)
1768 return ret_val;
1769
1770 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1771 * forced whenever speed and duplex are forced.
1772 */
1773 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1774 if (ret_val)
1775 return ret_val;
1776
1777 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1778 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1779
1780 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1781 if (ret_val)
1782 return ret_val;
1783
1784 DEBUGOUT1("IGP PSCR: %X\n", phy_data);
1785
1786 usec_delay(1);
1787
1788 if (phy->autoneg_wait_to_complete) {
1789 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n");
1790
1791 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1792 100000, &link);
1793 if (ret_val)
1794 return ret_val;
1795
1796 if (!link)
1797 DEBUGOUT("Link taking longer than expected.\n");
1798
1799 /* Try once more */
1800 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1801 100000, &link);
1802 }
1803
1804 return ret_val;
1805 }
1806
1807 /**
1808 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1809 * @hw: pointer to the HW structure
1810 *
1811 * Calls the PHY setup function to force speed and duplex. Clears the
1812 * auto-crossover to force MDI manually. Resets the PHY to commit the
1813 * changes. If time expires while waiting for link up, we reset the DSP.
1814 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1815 * successful completion, else return corresponding error code.
1816 **/
e1000_phy_force_speed_duplex_m88(struct e1000_hw * hw)1817 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1818 {
1819 struct e1000_phy_info *phy = &hw->phy;
1820 s32 ret_val;
1821 u16 phy_data;
1822 bool link;
1823
1824 DEBUGFUNC("e1000_phy_force_speed_duplex_m88");
1825
1826 /* I210 and I211 devices support Auto-Crossover in forced operation. */
1827 if (phy->type != e1000_phy_i210) {
1828 /* Clear Auto-Crossover to force MDI manually. M88E1000
1829 * requires MDI forced whenever speed and duplex are forced.
1830 */
1831 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,
1832 &phy_data);
1833 if (ret_val)
1834 return ret_val;
1835
1836 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1837 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1838 phy_data);
1839 if (ret_val)
1840 return ret_val;
1841
1842 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data);
1843 }
1844
1845 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1846 if (ret_val)
1847 return ret_val;
1848
1849 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1850
1851 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1852 if (ret_val)
1853 return ret_val;
1854
1855 /* Reset the phy to commit changes. */
1856 ret_val = hw->phy.ops.commit(hw);
1857 if (ret_val)
1858 return ret_val;
1859
1860 if (phy->autoneg_wait_to_complete) {
1861 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n");
1862
1863 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1864 100000, &link);
1865 if (ret_val)
1866 return ret_val;
1867
1868 if (!link) {
1869 bool reset_dsp = true;
1870
1871 switch (hw->phy.id) {
1872 case I347AT4_E_PHY_ID:
1873 case M88E1340M_E_PHY_ID:
1874 case M88E1112_E_PHY_ID:
1875 case M88E1543_E_PHY_ID:
1876 case M88E1512_E_PHY_ID:
1877 case I210_I_PHY_ID:
1878 reset_dsp = false;
1879 break;
1880 default:
1881 if (hw->phy.type != e1000_phy_m88)
1882 reset_dsp = false;
1883 break;
1884 }
1885
1886 if (!reset_dsp) {
1887 DEBUGOUT("Link taking longer than expected.\n");
1888 } else {
1889 /* We didn't get link.
1890 * Reset the DSP and cross our fingers.
1891 */
1892 ret_val = phy->ops.write_reg(hw,
1893 M88E1000_PHY_PAGE_SELECT,
1894 0x001d);
1895 if (ret_val)
1896 return ret_val;
1897 ret_val = e1000_phy_reset_dsp_generic(hw);
1898 if (ret_val)
1899 return ret_val;
1900 }
1901 }
1902
1903 /* Try once more */
1904 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1905 100000, &link);
1906 if (ret_val)
1907 return ret_val;
1908 }
1909
1910 if (hw->phy.type != e1000_phy_m88)
1911 return E1000_SUCCESS;
1912
1913 if (hw->phy.id == I347AT4_E_PHY_ID ||
1914 hw->phy.id == M88E1340M_E_PHY_ID ||
1915 hw->phy.id == M88E1112_E_PHY_ID)
1916 return E1000_SUCCESS;
1917 if (hw->phy.id == I210_I_PHY_ID)
1918 return E1000_SUCCESS;
1919 if ((hw->phy.id == M88E1543_E_PHY_ID) ||
1920 (hw->phy.id == M88E1512_E_PHY_ID))
1921 return E1000_SUCCESS;
1922 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1923 if (ret_val)
1924 return ret_val;
1925
1926 /* Resetting the phy means we need to re-force TX_CLK in the
1927 * Extended PHY Specific Control Register to 25MHz clock from
1928 * the reset value of 2.5MHz.
1929 */
1930 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1931 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1932 if (ret_val)
1933 return ret_val;
1934
1935 /* In addition, we must re-enable CRS on Tx for both half and full
1936 * duplex.
1937 */
1938 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1939 if (ret_val)
1940 return ret_val;
1941
1942 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1943 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1944
1945 return ret_val;
1946 }
1947
1948 /**
1949 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1950 * @hw: pointer to the HW structure
1951 *
1952 * Forces the speed and duplex settings of the PHY.
1953 * This is a function pointer entry point only called by
1954 * PHY setup routines.
1955 **/
e1000_phy_force_speed_duplex_ife(struct e1000_hw * hw)1956 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1957 {
1958 struct e1000_phy_info *phy = &hw->phy;
1959 s32 ret_val;
1960 u16 data;
1961 bool link;
1962
1963 DEBUGFUNC("e1000_phy_force_speed_duplex_ife");
1964
1965 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data);
1966 if (ret_val)
1967 return ret_val;
1968
1969 e1000_phy_force_speed_duplex_setup(hw, &data);
1970
1971 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);
1972 if (ret_val)
1973 return ret_val;
1974
1975 /* Disable MDI-X support for 10/100 */
1976 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
1977 if (ret_val)
1978 return ret_val;
1979
1980 data &= ~IFE_PMC_AUTO_MDIX;
1981 data &= ~IFE_PMC_FORCE_MDIX;
1982
1983 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);
1984 if (ret_val)
1985 return ret_val;
1986
1987 DEBUGOUT1("IFE PMC: %X\n", data);
1988
1989 usec_delay(1);
1990
1991 if (phy->autoneg_wait_to_complete) {
1992 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n");
1993
1994 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1995 100000, &link);
1996 if (ret_val)
1997 return ret_val;
1998
1999 if (!link)
2000 DEBUGOUT("Link taking longer than expected.\n");
2001
2002 /* Try once more */
2003 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
2004 100000, &link);
2005 if (ret_val)
2006 return ret_val;
2007 }
2008
2009 return E1000_SUCCESS;
2010 }
2011
2012 /**
2013 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
2014 * @hw: pointer to the HW structure
2015 * @phy_ctrl: pointer to current value of PHY_CONTROL
2016 *
2017 * Forces speed and duplex on the PHY by doing the following: disable flow
2018 * control, force speed/duplex on the MAC, disable auto speed detection,
2019 * disable auto-negotiation, configure duplex, configure speed, configure
2020 * the collision distance, write configuration to CTRL register. The
2021 * caller must write to the PHY_CONTROL register for these settings to
2022 * take effect.
2023 **/
e1000_phy_force_speed_duplex_setup(struct e1000_hw * hw,u16 * phy_ctrl)2024 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
2025 {
2026 struct e1000_mac_info *mac = &hw->mac;
2027 u32 ctrl;
2028
2029 DEBUGFUNC("e1000_phy_force_speed_duplex_setup");
2030
2031 /* Turn off flow control when forcing speed/duplex */
2032 hw->fc.current_mode = e1000_fc_none;
2033
2034 /* Force speed/duplex on the mac */
2035 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2036 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2037 ctrl &= ~E1000_CTRL_SPD_SEL;
2038
2039 /* Disable Auto Speed Detection */
2040 ctrl &= ~E1000_CTRL_ASDE;
2041
2042 /* Disable autoneg on the phy */
2043 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
2044
2045 /* Forcing Full or Half Duplex? */
2046 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
2047 ctrl &= ~E1000_CTRL_FD;
2048 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
2049 DEBUGOUT("Half Duplex\n");
2050 } else {
2051 ctrl |= E1000_CTRL_FD;
2052 *phy_ctrl |= MII_CR_FULL_DUPLEX;
2053 DEBUGOUT("Full Duplex\n");
2054 }
2055
2056 /* Forcing 10mb or 100mb? */
2057 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
2058 ctrl |= E1000_CTRL_SPD_100;
2059 *phy_ctrl |= MII_CR_SPEED_100;
2060 *phy_ctrl &= ~MII_CR_SPEED_1000;
2061 DEBUGOUT("Forcing 100mb\n");
2062 } else {
2063 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2064 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
2065 DEBUGOUT("Forcing 10mb\n");
2066 }
2067
2068 hw->mac.ops.config_collision_dist(hw);
2069
2070 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2071 }
2072
2073 /**
2074 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3
2075 * @hw: pointer to the HW structure
2076 * @active: boolean used to enable/disable lplu
2077 *
2078 * Success returns 0, Failure returns 1
2079 *
2080 * The low power link up (lplu) state is set to the power management level D3
2081 * and SmartSpeed is disabled when active is true, else clear lplu for D3
2082 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
2083 * is used during Dx states where the power conservation is most important.
2084 * During driver activity, SmartSpeed should be enabled so performance is
2085 * maintained.
2086 **/
e1000_set_d3_lplu_state_generic(struct e1000_hw * hw,bool active)2087 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active)
2088 {
2089 struct e1000_phy_info *phy = &hw->phy;
2090 s32 ret_val;
2091 u16 data;
2092
2093 DEBUGFUNC("e1000_set_d3_lplu_state_generic");
2094
2095 if (!hw->phy.ops.read_reg)
2096 return E1000_SUCCESS;
2097
2098 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
2099 if (ret_val)
2100 return ret_val;
2101
2102 if (!active) {
2103 data &= ~IGP02E1000_PM_D3_LPLU;
2104 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2105 data);
2106 if (ret_val)
2107 return ret_val;
2108 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
2109 * during Dx states where the power conservation is most
2110 * important. During driver activity we should enable
2111 * SmartSpeed, so performance is maintained.
2112 */
2113 if (phy->smart_speed == e1000_smart_speed_on) {
2114 ret_val = phy->ops.read_reg(hw,
2115 IGP01E1000_PHY_PORT_CONFIG,
2116 &data);
2117 if (ret_val)
2118 return ret_val;
2119
2120 data |= IGP01E1000_PSCFR_SMART_SPEED;
2121 ret_val = phy->ops.write_reg(hw,
2122 IGP01E1000_PHY_PORT_CONFIG,
2123 data);
2124 if (ret_val)
2125 return ret_val;
2126 } else if (phy->smart_speed == e1000_smart_speed_off) {
2127 ret_val = phy->ops.read_reg(hw,
2128 IGP01E1000_PHY_PORT_CONFIG,
2129 &data);
2130 if (ret_val)
2131 return ret_val;
2132
2133 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2134 ret_val = phy->ops.write_reg(hw,
2135 IGP01E1000_PHY_PORT_CONFIG,
2136 data);
2137 if (ret_val)
2138 return ret_val;
2139 }
2140 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2141 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2142 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2143 data |= IGP02E1000_PM_D3_LPLU;
2144 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2145 data);
2146 if (ret_val)
2147 return ret_val;
2148
2149 /* When LPLU is enabled, we should disable SmartSpeed */
2150 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2151 &data);
2152 if (ret_val)
2153 return ret_val;
2154
2155 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2156 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2157 data);
2158 }
2159
2160 return ret_val;
2161 }
2162
2163 /**
2164 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred
2165 * @hw: pointer to the HW structure
2166 *
2167 * Success returns 0, Failure returns 1
2168 *
2169 * A downshift is detected by querying the PHY link health.
2170 **/
e1000_check_downshift_generic(struct e1000_hw * hw)2171 s32 e1000_check_downshift_generic(struct e1000_hw *hw)
2172 {
2173 struct e1000_phy_info *phy = &hw->phy;
2174 s32 ret_val;
2175 u16 phy_data, offset, mask;
2176
2177 DEBUGFUNC("e1000_check_downshift_generic");
2178
2179 switch (phy->type) {
2180 case e1000_phy_i210:
2181 case e1000_phy_m88:
2182 case e1000_phy_gg82563:
2183 case e1000_phy_bm:
2184 case e1000_phy_82578:
2185 offset = M88E1000_PHY_SPEC_STATUS;
2186 mask = M88E1000_PSSR_DOWNSHIFT;
2187 break;
2188 case e1000_phy_igp:
2189 case e1000_phy_igp_2:
2190 case e1000_phy_igp_3:
2191 offset = IGP01E1000_PHY_LINK_HEALTH;
2192 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
2193 break;
2194 default:
2195 /* speed downshift not supported */
2196 phy->speed_downgraded = false;
2197 return E1000_SUCCESS;
2198 }
2199
2200 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2201
2202 if (!ret_val)
2203 phy->speed_downgraded = !!(phy_data & mask);
2204
2205 return ret_val;
2206 }
2207
2208 /**
2209 * e1000_check_polarity_m88 - Checks the polarity.
2210 * @hw: pointer to the HW structure
2211 *
2212 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2213 *
2214 * Polarity is determined based on the PHY specific status register.
2215 **/
e1000_check_polarity_m88(struct e1000_hw * hw)2216 s32 e1000_check_polarity_m88(struct e1000_hw *hw)
2217 {
2218 struct e1000_phy_info *phy = &hw->phy;
2219 s32 ret_val;
2220 u16 data;
2221
2222 DEBUGFUNC("e1000_check_polarity_m88");
2223
2224 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
2225
2226 if (!ret_val)
2227 phy->cable_polarity = ((data & M88E1000_PSSR_REV_POLARITY)
2228 ? e1000_rev_polarity_reversed
2229 : e1000_rev_polarity_normal);
2230
2231 return ret_val;
2232 }
2233
2234 /**
2235 * e1000_check_polarity_igp - Checks the polarity.
2236 * @hw: pointer to the HW structure
2237 *
2238 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2239 *
2240 * Polarity is determined based on the PHY port status register, and the
2241 * current speed (since there is no polarity at 100Mbps).
2242 **/
e1000_check_polarity_igp(struct e1000_hw * hw)2243 s32 e1000_check_polarity_igp(struct e1000_hw *hw)
2244 {
2245 struct e1000_phy_info *phy = &hw->phy;
2246 s32 ret_val;
2247 u16 data, offset, mask;
2248
2249 DEBUGFUNC("e1000_check_polarity_igp");
2250
2251 /* Polarity is determined based on the speed of
2252 * our connection.
2253 */
2254 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2255 if (ret_val)
2256 return ret_val;
2257
2258 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2259 IGP01E1000_PSSR_SPEED_1000MBPS) {
2260 offset = IGP01E1000_PHY_PCS_INIT_REG;
2261 mask = IGP01E1000_PHY_POLARITY_MASK;
2262 } else {
2263 /* This really only applies to 10Mbps since
2264 * there is no polarity for 100Mbps (always 0).
2265 */
2266 offset = IGP01E1000_PHY_PORT_STATUS;
2267 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
2268 }
2269
2270 ret_val = phy->ops.read_reg(hw, offset, &data);
2271
2272 if (!ret_val)
2273 phy->cable_polarity = ((data & mask)
2274 ? e1000_rev_polarity_reversed
2275 : e1000_rev_polarity_normal);
2276
2277 return ret_val;
2278 }
2279
2280 /**
2281 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
2282 * @hw: pointer to the HW structure
2283 *
2284 * Polarity is determined on the polarity reversal feature being enabled.
2285 **/
e1000_check_polarity_ife(struct e1000_hw * hw)2286 s32 e1000_check_polarity_ife(struct e1000_hw *hw)
2287 {
2288 struct e1000_phy_info *phy = &hw->phy;
2289 s32 ret_val;
2290 u16 phy_data, offset, mask;
2291
2292 DEBUGFUNC("e1000_check_polarity_ife");
2293
2294 /* Polarity is determined based on the reversal feature being enabled.
2295 */
2296 if (phy->polarity_correction) {
2297 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
2298 mask = IFE_PESC_POLARITY_REVERSED;
2299 } else {
2300 offset = IFE_PHY_SPECIAL_CONTROL;
2301 mask = IFE_PSC_FORCE_POLARITY;
2302 }
2303
2304 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2305
2306 if (!ret_val)
2307 phy->cable_polarity = ((phy_data & mask)
2308 ? e1000_rev_polarity_reversed
2309 : e1000_rev_polarity_normal);
2310
2311 return ret_val;
2312 }
2313
2314 /**
2315 * e1000_wait_autoneg - Wait for auto-neg completion
2316 * @hw: pointer to the HW structure
2317 *
2318 * Waits for auto-negotiation to complete or for the auto-negotiation time
2319 * limit to expire, which ever happens first.
2320 **/
e1000_wait_autoneg(struct e1000_hw * hw)2321 static s32 e1000_wait_autoneg(struct e1000_hw *hw)
2322 {
2323 s32 ret_val = E1000_SUCCESS;
2324 u16 i, phy_status;
2325
2326 DEBUGFUNC("e1000_wait_autoneg");
2327
2328 if (!hw->phy.ops.read_reg)
2329 return E1000_SUCCESS;
2330
2331 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
2332 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
2333 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2334 if (ret_val)
2335 break;
2336 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2337 if (ret_val)
2338 break;
2339 if (phy_status & MII_SR_AUTONEG_COMPLETE)
2340 break;
2341 msec_delay(100);
2342 }
2343
2344 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
2345 * has completed.
2346 */
2347 return ret_val;
2348 }
2349
2350 /**
2351 * e1000_phy_has_link_generic - Polls PHY for link
2352 * @hw: pointer to the HW structure
2353 * @iterations: number of times to poll for link
2354 * @usec_interval: delay between polling attempts
2355 * @success: pointer to whether polling was successful or not
2356 *
2357 * Polls the PHY status register for link, 'iterations' number of times.
2358 **/
e1000_phy_has_link_generic(struct e1000_hw * hw,u32 iterations,u32 usec_interval,bool * success)2359 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
2360 u32 usec_interval, bool *success)
2361 {
2362 s32 ret_val = E1000_SUCCESS;
2363 u16 i, phy_status;
2364
2365 DEBUGFUNC("e1000_phy_has_link_generic");
2366
2367 if (!hw->phy.ops.read_reg)
2368 return E1000_SUCCESS;
2369
2370 for (i = 0; i < iterations; i++) {
2371 /* Some PHYs require the PHY_STATUS register to be read
2372 * twice due to the link bit being sticky. No harm doing
2373 * it across the board.
2374 */
2375 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2376 if (ret_val) {
2377 /* If the first read fails, another entity may have
2378 * ownership of the resources, wait and try again to
2379 * see if they have relinquished the resources yet.
2380 */
2381 if (usec_interval >= 1000)
2382 msec_delay(usec_interval/1000);
2383 else
2384 usec_delay(usec_interval);
2385 }
2386 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2387 if (ret_val)
2388 break;
2389 if (phy_status & MII_SR_LINK_STATUS)
2390 break;
2391 if (usec_interval >= 1000)
2392 msec_delay(usec_interval/1000);
2393 else
2394 usec_delay(usec_interval);
2395 }
2396
2397 *success = (i < iterations);
2398
2399 return ret_val;
2400 }
2401
2402 /**
2403 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY
2404 * @hw: pointer to the HW structure
2405 *
2406 * Reads the PHY specific status register to retrieve the cable length
2407 * information. The cable length is determined by averaging the minimum and
2408 * maximum values to get the "average" cable length. The m88 PHY has four
2409 * possible cable length values, which are:
2410 * Register Value Cable Length
2411 * 0 < 50 meters
2412 * 1 50 - 80 meters
2413 * 2 80 - 110 meters
2414 * 3 110 - 140 meters
2415 * 4 > 140 meters
2416 **/
e1000_get_cable_length_m88(struct e1000_hw * hw)2417 s32 e1000_get_cable_length_m88(struct e1000_hw *hw)
2418 {
2419 struct e1000_phy_info *phy = &hw->phy;
2420 s32 ret_val;
2421 u16 phy_data, index;
2422
2423 DEBUGFUNC("e1000_get_cable_length_m88");
2424
2425 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2426 if (ret_val)
2427 return ret_val;
2428
2429 index = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2430 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
2431
2432 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
2433 return -E1000_ERR_PHY;
2434
2435 phy->min_cable_length = e1000_m88_cable_length_table[index];
2436 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2437
2438 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2439
2440 return E1000_SUCCESS;
2441 }
2442
e1000_get_cable_length_m88_gen2(struct e1000_hw * hw)2443 s32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw)
2444 {
2445 struct e1000_phy_info *phy = &hw->phy;
2446 s32 ret_val;
2447 u16 phy_data, phy_data2, is_cm;
2448 u16 index, default_page;
2449
2450 DEBUGFUNC("e1000_get_cable_length_m88_gen2");
2451
2452 switch (hw->phy.id) {
2453 case I210_I_PHY_ID:
2454 /* Get cable length from PHY Cable Diagnostics Control Reg */
2455 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
2456 (I347AT4_PCDL + phy->addr),
2457 &phy_data);
2458 if (ret_val)
2459 return ret_val;
2460
2461 /* Check if the unit of cable length is meters or cm */
2462 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
2463 I347AT4_PCDC, &phy_data2);
2464 if (ret_val)
2465 return ret_val;
2466
2467 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
2468
2469 /* Populate the phy structure with cable length in meters */
2470 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2471 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2472 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2473 break;
2474 case M88E1543_E_PHY_ID:
2475 case M88E1512_E_PHY_ID:
2476 case M88E1340M_E_PHY_ID:
2477 case I347AT4_E_PHY_ID:
2478 /* Remember the original page select and set it to 7 */
2479 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2480 &default_page);
2481 if (ret_val)
2482 return ret_val;
2483
2484 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);
2485 if (ret_val)
2486 return ret_val;
2487
2488 /* Get cable length from PHY Cable Diagnostics Control Reg */
2489 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr),
2490 &phy_data);
2491 if (ret_val)
2492 return ret_val;
2493
2494 /* Check if the unit of cable length is meters or cm */
2495 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);
2496 if (ret_val)
2497 return ret_val;
2498
2499 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
2500
2501 /* Populate the phy structure with cable length in meters */
2502 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2503 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2504 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2505
2506 /* Reset the page select to its original value */
2507 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2508 default_page);
2509 if (ret_val)
2510 return ret_val;
2511 break;
2512
2513 case M88E1112_E_PHY_ID:
2514 /* Remember the original page select and set it to 5 */
2515 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2516 &default_page);
2517 if (ret_val)
2518 return ret_val;
2519
2520 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);
2521 if (ret_val)
2522 return ret_val;
2523
2524 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,
2525 &phy_data);
2526 if (ret_val)
2527 return ret_val;
2528
2529 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2530 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
2531
2532 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
2533 return -E1000_ERR_PHY;
2534
2535 phy->min_cable_length = e1000_m88_cable_length_table[index];
2536 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2537
2538 phy->cable_length = (phy->min_cable_length +
2539 phy->max_cable_length) / 2;
2540
2541 /* Reset the page select to its original value */
2542 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2543 default_page);
2544 if (ret_val)
2545 return ret_val;
2546
2547 break;
2548 default:
2549 return -E1000_ERR_PHY;
2550 }
2551
2552 return ret_val;
2553 }
2554
2555 /**
2556 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY
2557 * @hw: pointer to the HW structure
2558 *
2559 * The automatic gain control (agc) normalizes the amplitude of the
2560 * received signal, adjusting for the attenuation produced by the
2561 * cable. By reading the AGC registers, which represent the
2562 * combination of coarse and fine gain value, the value can be put
2563 * into a lookup table to obtain the approximate cable length
2564 * for each channel.
2565 **/
e1000_get_cable_length_igp_2(struct e1000_hw * hw)2566 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw)
2567 {
2568 struct e1000_phy_info *phy = &hw->phy;
2569 s32 ret_val;
2570 u16 phy_data, i, agc_value = 0;
2571 u16 cur_agc_index, max_agc_index = 0;
2572 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
2573 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
2574 IGP02E1000_PHY_AGC_A,
2575 IGP02E1000_PHY_AGC_B,
2576 IGP02E1000_PHY_AGC_C,
2577 IGP02E1000_PHY_AGC_D
2578 };
2579
2580 DEBUGFUNC("e1000_get_cable_length_igp_2");
2581
2582 /* Read the AGC registers for all channels */
2583 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
2584 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
2585 if (ret_val)
2586 return ret_val;
2587
2588 /* Getting bits 15:9, which represent the combination of
2589 * coarse and fine gain values. The result is a number
2590 * that can be put into the lookup table to obtain the
2591 * approximate cable length.
2592 */
2593 cur_agc_index = ((phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
2594 IGP02E1000_AGC_LENGTH_MASK);
2595
2596 /* Array index bound check. */
2597 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
2598 (cur_agc_index == 0))
2599 return -E1000_ERR_PHY;
2600
2601 /* Remove min & max AGC values from calculation. */
2602 if (e1000_igp_2_cable_length_table[min_agc_index] >
2603 e1000_igp_2_cable_length_table[cur_agc_index])
2604 min_agc_index = cur_agc_index;
2605 if (e1000_igp_2_cable_length_table[max_agc_index] <
2606 e1000_igp_2_cable_length_table[cur_agc_index])
2607 max_agc_index = cur_agc_index;
2608
2609 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
2610 }
2611
2612 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
2613 e1000_igp_2_cable_length_table[max_agc_index]);
2614 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
2615
2616 /* Calculate cable length with the error range of +/- 10 meters. */
2617 phy->min_cable_length = (((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
2618 (agc_value - IGP02E1000_AGC_RANGE) : 0);
2619 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
2620
2621 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2622
2623 return E1000_SUCCESS;
2624 }
2625
2626 /**
2627 * e1000_get_phy_info_m88 - Retrieve PHY information
2628 * @hw: pointer to the HW structure
2629 *
2630 * Valid for only copper links. Read the PHY status register (sticky read)
2631 * to verify that link is up. Read the PHY special control register to
2632 * determine the polarity and 10base-T extended distance. Read the PHY
2633 * special status register to determine MDI/MDIx and current speed. If
2634 * speed is 1000, then determine cable length, local and remote receiver.
2635 **/
e1000_get_phy_info_m88(struct e1000_hw * hw)2636 s32 e1000_get_phy_info_m88(struct e1000_hw *hw)
2637 {
2638 struct e1000_phy_info *phy = &hw->phy;
2639 s32 ret_val;
2640 u16 phy_data;
2641 bool link;
2642
2643 DEBUGFUNC("e1000_get_phy_info_m88");
2644
2645 if (phy->media_type != e1000_media_type_copper) {
2646 DEBUGOUT("Phy info is only valid for copper media\n");
2647 return -E1000_ERR_CONFIG;
2648 }
2649
2650 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2651 if (ret_val)
2652 return ret_val;
2653
2654 if (!link) {
2655 DEBUGOUT("Phy info is only valid if link is up\n");
2656 return -E1000_ERR_CONFIG;
2657 }
2658
2659 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2660 if (ret_val)
2661 return ret_val;
2662
2663 phy->polarity_correction = !!(phy_data &
2664 M88E1000_PSCR_POLARITY_REVERSAL);
2665
2666 ret_val = e1000_check_polarity_m88(hw);
2667 if (ret_val)
2668 return ret_val;
2669
2670 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2671 if (ret_val)
2672 return ret_val;
2673
2674 phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX);
2675
2676 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
2677 ret_val = hw->phy.ops.get_cable_length(hw);
2678 if (ret_val)
2679 return ret_val;
2680
2681 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
2682 if (ret_val)
2683 return ret_val;
2684
2685 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
2686 ? e1000_1000t_rx_status_ok
2687 : e1000_1000t_rx_status_not_ok;
2688
2689 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
2690 ? e1000_1000t_rx_status_ok
2691 : e1000_1000t_rx_status_not_ok;
2692 } else {
2693 /* Set values to "undefined" */
2694 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2695 phy->local_rx = e1000_1000t_rx_status_undefined;
2696 phy->remote_rx = e1000_1000t_rx_status_undefined;
2697 }
2698
2699 return ret_val;
2700 }
2701
2702 /**
2703 * e1000_get_phy_info_igp - Retrieve igp PHY information
2704 * @hw: pointer to the HW structure
2705 *
2706 * Read PHY status to determine if link is up. If link is up, then
2707 * set/determine 10base-T extended distance and polarity correction. Read
2708 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2709 * determine on the cable length, local and remote receiver.
2710 **/
e1000_get_phy_info_igp(struct e1000_hw * hw)2711 s32 e1000_get_phy_info_igp(struct e1000_hw *hw)
2712 {
2713 struct e1000_phy_info *phy = &hw->phy;
2714 s32 ret_val;
2715 u16 data;
2716 bool link;
2717
2718 DEBUGFUNC("e1000_get_phy_info_igp");
2719
2720 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2721 if (ret_val)
2722 return ret_val;
2723
2724 if (!link) {
2725 DEBUGOUT("Phy info is only valid if link is up\n");
2726 return -E1000_ERR_CONFIG;
2727 }
2728
2729 phy->polarity_correction = true;
2730
2731 ret_val = e1000_check_polarity_igp(hw);
2732 if (ret_val)
2733 return ret_val;
2734
2735 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2736 if (ret_val)
2737 return ret_val;
2738
2739 phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX);
2740
2741 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2742 IGP01E1000_PSSR_SPEED_1000MBPS) {
2743 ret_val = phy->ops.get_cable_length(hw);
2744 if (ret_val)
2745 return ret_val;
2746
2747 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2748 if (ret_val)
2749 return ret_val;
2750
2751 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2752 ? e1000_1000t_rx_status_ok
2753 : e1000_1000t_rx_status_not_ok;
2754
2755 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2756 ? e1000_1000t_rx_status_ok
2757 : e1000_1000t_rx_status_not_ok;
2758 } else {
2759 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2760 phy->local_rx = e1000_1000t_rx_status_undefined;
2761 phy->remote_rx = e1000_1000t_rx_status_undefined;
2762 }
2763
2764 return ret_val;
2765 }
2766
2767 /**
2768 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2769 * @hw: pointer to the HW structure
2770 *
2771 * Populates "phy" structure with various feature states.
2772 **/
e1000_get_phy_info_ife(struct e1000_hw * hw)2773 s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2774 {
2775 struct e1000_phy_info *phy = &hw->phy;
2776 s32 ret_val;
2777 u16 data;
2778 bool link;
2779
2780 DEBUGFUNC("e1000_get_phy_info_ife");
2781
2782 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2783 if (ret_val)
2784 return ret_val;
2785
2786 if (!link) {
2787 DEBUGOUT("Phy info is only valid if link is up\n");
2788 return -E1000_ERR_CONFIG;
2789 }
2790
2791 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2792 if (ret_val)
2793 return ret_val;
2794 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE);
2795
2796 if (phy->polarity_correction) {
2797 ret_val = e1000_check_polarity_ife(hw);
2798 if (ret_val)
2799 return ret_val;
2800 } else {
2801 /* Polarity is forced */
2802 phy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY)
2803 ? e1000_rev_polarity_reversed
2804 : e1000_rev_polarity_normal);
2805 }
2806
2807 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
2808 if (ret_val)
2809 return ret_val;
2810
2811 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS);
2812
2813 /* The following parameters are undefined for 10/100 operation. */
2814 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2815 phy->local_rx = e1000_1000t_rx_status_undefined;
2816 phy->remote_rx = e1000_1000t_rx_status_undefined;
2817
2818 return E1000_SUCCESS;
2819 }
2820
2821 /**
2822 * e1000_phy_sw_reset_generic - PHY software reset
2823 * @hw: pointer to the HW structure
2824 *
2825 * Does a software reset of the PHY by reading the PHY control register and
2826 * setting/write the control register reset bit to the PHY.
2827 **/
e1000_phy_sw_reset_generic(struct e1000_hw * hw)2828 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw)
2829 {
2830 s32 ret_val;
2831 u16 phy_ctrl;
2832
2833 DEBUGFUNC("e1000_phy_sw_reset_generic");
2834
2835 if (!hw->phy.ops.read_reg)
2836 return E1000_SUCCESS;
2837
2838 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2839 if (ret_val)
2840 return ret_val;
2841
2842 phy_ctrl |= MII_CR_RESET;
2843 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2844 if (ret_val)
2845 return ret_val;
2846
2847 usec_delay(1);
2848
2849 return ret_val;
2850 }
2851
2852 /**
2853 * e1000_phy_hw_reset_generic - PHY hardware reset
2854 * @hw: pointer to the HW structure
2855 *
2856 * Verify the reset block is not blocking us from resetting. Acquire
2857 * semaphore (if necessary) and read/set/write the device control reset
2858 * bit in the PHY. Wait the appropriate delay time for the device to
2859 * reset and release the semaphore (if necessary).
2860 **/
e1000_phy_hw_reset_generic(struct e1000_hw * hw)2861 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw)
2862 {
2863 struct e1000_phy_info *phy = &hw->phy;
2864 s32 ret_val;
2865 u32 ctrl;
2866
2867 DEBUGFUNC("e1000_phy_hw_reset_generic");
2868
2869 if (phy->ops.check_reset_block) {
2870 ret_val = phy->ops.check_reset_block(hw);
2871 if (ret_val)
2872 return E1000_SUCCESS;
2873 }
2874
2875 ret_val = phy->ops.acquire(hw);
2876 if (ret_val)
2877 return ret_val;
2878
2879 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2880 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
2881 E1000_WRITE_FLUSH(hw);
2882
2883 usec_delay(phy->reset_delay_us);
2884
2885 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2886 E1000_WRITE_FLUSH(hw);
2887
2888 usec_delay(150);
2889
2890 phy->ops.release(hw);
2891
2892 return phy->ops.get_cfg_done(hw);
2893 }
2894
2895 /**
2896 * e1000_get_cfg_done_generic - Generic configuration done
2897 * @hw: pointer to the HW structure
2898 *
2899 * Generic function to wait 10 milli-seconds for configuration to complete
2900 * and return success.
2901 **/
e1000_get_cfg_done_generic(struct e1000_hw E1000_UNUSEDARG * hw)2902 s32 e1000_get_cfg_done_generic(struct e1000_hw E1000_UNUSEDARG *hw)
2903 {
2904 DEBUGFUNC("e1000_get_cfg_done_generic");
2905
2906 msec_delay_irq(10);
2907
2908 return E1000_SUCCESS;
2909 }
2910
2911 /**
2912 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY
2913 * @hw: pointer to the HW structure
2914 *
2915 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2916 **/
e1000_phy_init_script_igp3(struct e1000_hw * hw)2917 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw)
2918 {
2919 DEBUGOUT("Running IGP 3 PHY init script\n");
2920
2921 /* PHY init IGP 3 */
2922 /* Enable rise/fall, 10-mode work in class-A */
2923 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2924 /* Remove all caps from Replica path filter */
2925 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2926 /* Bias trimming for ADC, AFE and Driver (Default) */
2927 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2928 /* Increase Hybrid poly bias */
2929 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2930 /* Add 4% to Tx amplitude in Gig mode */
2931 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2932 /* Disable trimming (TTT) */
2933 hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2934 /* Poly DC correction to 94.6% + 2% for all channels */
2935 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2936 /* ABS DC correction to 95.9% */
2937 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2938 /* BG temp curve trim */
2939 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2940 /* Increasing ADC OPAMP stage 1 currents to max */
2941 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2942 /* Force 1000 ( required for enabling PHY regs configuration) */
2943 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2944 /* Set upd_freq to 6 */
2945 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2946 /* Disable NPDFE */
2947 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2948 /* Disable adaptive fixed FFE (Default) */
2949 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2950 /* Enable FFE hysteresis */
2951 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2952 /* Fixed FFE for short cable lengths */
2953 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2954 /* Fixed FFE for medium cable lengths */
2955 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2956 /* Fixed FFE for long cable lengths */
2957 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2958 /* Enable Adaptive Clip Threshold */
2959 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2960 /* AHT reset limit to 1 */
2961 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2962 /* Set AHT master delay to 127 msec */
2963 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2964 /* Set scan bits for AHT */
2965 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2966 /* Set AHT Preset bits */
2967 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2968 /* Change integ_factor of channel A to 3 */
2969 hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2970 /* Change prop_factor of channels BCD to 8 */
2971 hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2972 /* Change cg_icount + enable integbp for channels BCD */
2973 hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2974 /* Change cg_icount + enable integbp + change prop_factor_master
2975 * to 8 for channel A
2976 */
2977 hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2978 /* Disable AHT in Slave mode on channel A */
2979 hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2980 /* Enable LPLU and disable AN to 1000 in non-D0a states,
2981 * Enable SPD+B2B
2982 */
2983 hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2984 /* Enable restart AN on an1000_dis change */
2985 hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
2986 /* Enable wh_fifo read clock in 10/100 modes */
2987 hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
2988 /* Restart AN, Speed selection is 1000 */
2989 hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
2990
2991 return E1000_SUCCESS;
2992 }
2993
2994 /**
2995 * e1000_get_phy_type_from_id - Get PHY type from id
2996 * @phy_id: phy_id read from the phy
2997 *
2998 * Returns the phy type from the id.
2999 **/
e1000_get_phy_type_from_id(u32 phy_id)3000 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id)
3001 {
3002 enum e1000_phy_type phy_type = e1000_phy_unknown;
3003
3004 switch (phy_id) {
3005 case M88E1000_I_PHY_ID:
3006 case M88E1000_E_PHY_ID:
3007 case M88E1111_I_PHY_ID:
3008 case M88E1011_I_PHY_ID:
3009 case M88E1543_E_PHY_ID:
3010 case M88E1512_E_PHY_ID:
3011 case I347AT4_E_PHY_ID:
3012 case M88E1112_E_PHY_ID:
3013 case M88E1340M_E_PHY_ID:
3014 phy_type = e1000_phy_m88;
3015 break;
3016 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
3017 phy_type = e1000_phy_igp_2;
3018 break;
3019 case GG82563_E_PHY_ID:
3020 phy_type = e1000_phy_gg82563;
3021 break;
3022 case IGP03E1000_E_PHY_ID:
3023 phy_type = e1000_phy_igp_3;
3024 break;
3025 case IFE_E_PHY_ID:
3026 case IFE_PLUS_E_PHY_ID:
3027 case IFE_C_E_PHY_ID:
3028 phy_type = e1000_phy_ife;
3029 break;
3030 case BME1000_E_PHY_ID:
3031 case BME1000_E_PHY_ID_R2:
3032 phy_type = e1000_phy_bm;
3033 break;
3034 case I82578_E_PHY_ID:
3035 phy_type = e1000_phy_82578;
3036 break;
3037 case I82577_E_PHY_ID:
3038 phy_type = e1000_phy_82577;
3039 break;
3040 case I82579_E_PHY_ID:
3041 phy_type = e1000_phy_82579;
3042 break;
3043 case I217_E_PHY_ID:
3044 phy_type = e1000_phy_i217;
3045 break;
3046 case I82580_I_PHY_ID:
3047 phy_type = e1000_phy_82580;
3048 break;
3049 case I210_I_PHY_ID:
3050 phy_type = e1000_phy_i210;
3051 break;
3052 default:
3053 phy_type = e1000_phy_unknown;
3054 break;
3055 }
3056 return phy_type;
3057 }
3058
3059 /**
3060 * e1000_determine_phy_address - Determines PHY address.
3061 * @hw: pointer to the HW structure
3062 *
3063 * This uses a trial and error method to loop through possible PHY
3064 * addresses. It tests each by reading the PHY ID registers and
3065 * checking for a match.
3066 **/
e1000_determine_phy_address(struct e1000_hw * hw)3067 s32 e1000_determine_phy_address(struct e1000_hw *hw)
3068 {
3069 u32 phy_addr = 0;
3070 u32 i;
3071 enum e1000_phy_type phy_type = e1000_phy_unknown;
3072
3073 hw->phy.id = phy_type;
3074
3075 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
3076 hw->phy.addr = phy_addr;
3077 i = 0;
3078
3079 do {
3080 e1000_get_phy_id(hw);
3081 phy_type = e1000_get_phy_type_from_id(hw->phy.id);
3082
3083 /* If phy_type is valid, break - we found our
3084 * PHY address
3085 */
3086 if (phy_type != e1000_phy_unknown)
3087 return E1000_SUCCESS;
3088
3089 msec_delay(1);
3090 i++;
3091 } while (i < 10);
3092 }
3093
3094 return -E1000_ERR_PHY_TYPE;
3095 }
3096
3097 /**
3098 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
3099 * @page: page to access
3100 * @reg: register to access
3101 *
3102 * Returns the phy address for the page requested.
3103 **/
e1000_get_phy_addr_for_bm_page(u32 page,u32 reg)3104 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
3105 {
3106 u32 phy_addr = 2;
3107
3108 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
3109 phy_addr = 1;
3110
3111 return phy_addr;
3112 }
3113
3114 /**
3115 * e1000_write_phy_reg_bm - Write BM PHY register
3116 * @hw: pointer to the HW structure
3117 * @offset: register offset to write to
3118 * @data: data to write at register offset
3119 *
3120 * Acquires semaphore, if necessary, then writes the data to PHY register
3121 * at the offset. Release any acquired semaphores before exiting.
3122 **/
e1000_write_phy_reg_bm(struct e1000_hw * hw,u32 offset,u16 data)3123 s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
3124 {
3125 s32 ret_val;
3126 u32 page = offset >> IGP_PAGE_SHIFT;
3127
3128 DEBUGFUNC("e1000_write_phy_reg_bm");
3129
3130 ret_val = hw->phy.ops.acquire(hw);
3131 if (ret_val)
3132 return ret_val;
3133
3134 /* Page 800 works differently than the rest so it has its own func */
3135 if (page == BM_WUC_PAGE) {
3136 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3137 false, false);
3138 goto release;
3139 }
3140
3141 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
3142
3143 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3144 u32 page_shift, page_select;
3145
3146 /* Page select is register 31 for phy address 1 and 22 for
3147 * phy address 2 and 3. Page select is shifted only for
3148 * phy address 1.
3149 */
3150 if (hw->phy.addr == 1) {
3151 page_shift = IGP_PAGE_SHIFT;
3152 page_select = IGP01E1000_PHY_PAGE_SELECT;
3153 } else {
3154 page_shift = 0;
3155 page_select = BM_PHY_PAGE_SELECT;
3156 }
3157
3158 /* Page is shifted left, PHY expects (page x 32) */
3159 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
3160 (page << page_shift));
3161 if (ret_val)
3162 goto release;
3163 }
3164
3165 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3166 data);
3167
3168 release:
3169 hw->phy.ops.release(hw);
3170 return ret_val;
3171 }
3172
3173 /**
3174 * e1000_read_phy_reg_bm - Read BM PHY register
3175 * @hw: pointer to the HW structure
3176 * @offset: register offset to be read
3177 * @data: pointer to the read data
3178 *
3179 * Acquires semaphore, if necessary, then reads the PHY register at offset
3180 * and storing the retrieved information in data. Release any acquired
3181 * semaphores before exiting.
3182 **/
e1000_read_phy_reg_bm(struct e1000_hw * hw,u32 offset,u16 * data)3183 s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
3184 {
3185 s32 ret_val;
3186 u32 page = offset >> IGP_PAGE_SHIFT;
3187
3188 DEBUGFUNC("e1000_read_phy_reg_bm");
3189
3190 ret_val = hw->phy.ops.acquire(hw);
3191 if (ret_val)
3192 return ret_val;
3193
3194 /* Page 800 works differently than the rest so it has its own func */
3195 if (page == BM_WUC_PAGE) {
3196 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3197 true, false);
3198 goto release;
3199 }
3200
3201 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
3202
3203 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3204 u32 page_shift, page_select;
3205
3206 /* Page select is register 31 for phy address 1 and 22 for
3207 * phy address 2 and 3. Page select is shifted only for
3208 * phy address 1.
3209 */
3210 if (hw->phy.addr == 1) {
3211 page_shift = IGP_PAGE_SHIFT;
3212 page_select = IGP01E1000_PHY_PAGE_SELECT;
3213 } else {
3214 page_shift = 0;
3215 page_select = BM_PHY_PAGE_SELECT;
3216 }
3217
3218 /* Page is shifted left, PHY expects (page x 32) */
3219 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
3220 (page << page_shift));
3221 if (ret_val)
3222 goto release;
3223 }
3224
3225 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3226 data);
3227 release:
3228 hw->phy.ops.release(hw);
3229 return ret_val;
3230 }
3231
3232 /**
3233 * e1000_read_phy_reg_bm2 - Read BM PHY register
3234 * @hw: pointer to the HW structure
3235 * @offset: register offset to be read
3236 * @data: pointer to the read data
3237 *
3238 * Acquires semaphore, if necessary, then reads the PHY register at offset
3239 * and storing the retrieved information in data. Release any acquired
3240 * semaphores before exiting.
3241 **/
e1000_read_phy_reg_bm2(struct e1000_hw * hw,u32 offset,u16 * data)3242 s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
3243 {
3244 s32 ret_val;
3245 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
3246
3247 DEBUGFUNC("e1000_read_phy_reg_bm2");
3248
3249 ret_val = hw->phy.ops.acquire(hw);
3250 if (ret_val)
3251 return ret_val;
3252
3253 /* Page 800 works differently than the rest so it has its own func */
3254 if (page == BM_WUC_PAGE) {
3255 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3256 true, false);
3257 goto release;
3258 }
3259
3260 hw->phy.addr = 1;
3261
3262 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3263 /* Page is shifted left, PHY expects (page x 32) */
3264 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3265 page);
3266
3267 if (ret_val)
3268 goto release;
3269 }
3270
3271 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3272 data);
3273 release:
3274 hw->phy.ops.release(hw);
3275 return ret_val;
3276 }
3277
3278 /**
3279 * e1000_write_phy_reg_bm2 - Write BM PHY register
3280 * @hw: pointer to the HW structure
3281 * @offset: register offset to write to
3282 * @data: data to write at register offset
3283 *
3284 * Acquires semaphore, if necessary, then writes the data to PHY register
3285 * at the offset. Release any acquired semaphores before exiting.
3286 **/
e1000_write_phy_reg_bm2(struct e1000_hw * hw,u32 offset,u16 data)3287 s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
3288 {
3289 s32 ret_val;
3290 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
3291
3292 DEBUGFUNC("e1000_write_phy_reg_bm2");
3293
3294 ret_val = hw->phy.ops.acquire(hw);
3295 if (ret_val)
3296 return ret_val;
3297
3298 /* Page 800 works differently than the rest so it has its own func */
3299 if (page == BM_WUC_PAGE) {
3300 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3301 false, false);
3302 goto release;
3303 }
3304
3305 hw->phy.addr = 1;
3306
3307 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3308 /* Page is shifted left, PHY expects (page x 32) */
3309 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3310 page);
3311
3312 if (ret_val)
3313 goto release;
3314 }
3315
3316 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3317 data);
3318
3319 release:
3320 hw->phy.ops.release(hw);
3321 return ret_val;
3322 }
3323
3324 /**
3325 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers
3326 * @hw: pointer to the HW structure
3327 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG
3328 *
3329 * Assumes semaphore already acquired and phy_reg points to a valid memory
3330 * address to store contents of the BM_WUC_ENABLE_REG register.
3331 **/
e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw * hw,u16 * phy_reg)3332 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
3333 {
3334 s32 ret_val;
3335 u16 temp;
3336
3337 DEBUGFUNC("e1000_enable_phy_wakeup_reg_access_bm");
3338
3339 if (!phy_reg)
3340 return -E1000_ERR_PARAM;
3341
3342 /* All page select, port ctrl and wakeup registers use phy address 1 */
3343 hw->phy.addr = 1;
3344
3345 /* Select Port Control Registers page */
3346 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
3347 if (ret_val) {
3348 DEBUGOUT("Could not set Port Control page\n");
3349 return ret_val;
3350 }
3351
3352 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
3353 if (ret_val) {
3354 DEBUGOUT2("Could not read PHY register %d.%d\n",
3355 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3356 return ret_val;
3357 }
3358
3359 /* Enable both PHY wakeup mode and Wakeup register page writes.
3360 * Prevent a power state change by disabling ME and Host PHY wakeup.
3361 */
3362 temp = *phy_reg;
3363 temp |= BM_WUC_ENABLE_BIT;
3364 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);
3365
3366 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp);
3367 if (ret_val) {
3368 DEBUGOUT2("Could not write PHY register %d.%d\n",
3369 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3370 return ret_val;
3371 }
3372
3373 /* Select Host Wakeup Registers page - caller now able to write
3374 * registers on the Wakeup registers page
3375 */
3376 return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
3377 }
3378
3379 /**
3380 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs
3381 * @hw: pointer to the HW structure
3382 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG
3383 *
3384 * Restore BM_WUC_ENABLE_REG to its original value.
3385 *
3386 * Assumes semaphore already acquired and *phy_reg is the contents of the
3387 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by
3388 * caller.
3389 **/
e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw * hw,u16 * phy_reg)3390 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
3391 {
3392 s32 ret_val;
3393
3394 DEBUGFUNC("e1000_disable_phy_wakeup_reg_access_bm");
3395
3396 if (!phy_reg)
3397 return -E1000_ERR_PARAM;
3398
3399 /* Select Port Control Registers page */
3400 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
3401 if (ret_val) {
3402 DEBUGOUT("Could not set Port Control page\n");
3403 return ret_val;
3404 }
3405
3406 /* Restore 769.17 to its original value */
3407 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg);
3408 if (ret_val)
3409 DEBUGOUT2("Could not restore PHY register %d.%d\n",
3410 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3411
3412 return ret_val;
3413 }
3414
3415 /**
3416 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register
3417 * @hw: pointer to the HW structure
3418 * @offset: register offset to be read or written
3419 * @data: pointer to the data to read or write
3420 * @read: determines if operation is read or write
3421 * @page_set: BM_WUC_PAGE already set and access enabled
3422 *
3423 * Read the PHY register at offset and store the retrieved information in
3424 * data, or write data to PHY register at offset. Note the procedure to
3425 * access the PHY wakeup registers is different than reading the other PHY
3426 * registers. It works as such:
3427 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1
3428 * 2) Set page to 800 for host (801 if we were manageability)
3429 * 3) Write the address using the address opcode (0x11)
3430 * 4) Read or write the data using the data opcode (0x12)
3431 * 5) Restore 769.17.2 to its original value
3432 *
3433 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and
3434 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm().
3435 *
3436 * Assumes semaphore is already acquired. When page_set==true, assumes
3437 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack
3438 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()).
3439 **/
e1000_access_phy_wakeup_reg_bm(struct e1000_hw * hw,u32 offset,u16 * data,bool read,bool page_set)3440 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
3441 u16 *data, bool read, bool page_set)
3442 {
3443 s32 ret_val;
3444 u16 reg = BM_PHY_REG_NUM(offset);
3445 u16 page = BM_PHY_REG_PAGE(offset);
3446 u16 phy_reg = 0;
3447
3448 DEBUGFUNC("e1000_access_phy_wakeup_reg_bm");
3449
3450 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */
3451 if ((hw->mac.type == e1000_pchlan) &&
3452 (!(E1000_READ_REG(hw, E1000_PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
3453 DEBUGOUT1("Attempting to access page %d while gig enabled.\n",
3454 page);
3455
3456 if (!page_set) {
3457 /* Enable access to PHY wakeup registers */
3458 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
3459 if (ret_val) {
3460 DEBUGOUT("Could not enable PHY wakeup reg access\n");
3461 return ret_val;
3462 }
3463 }
3464
3465 DEBUGOUT2("Accessing PHY page %d reg 0x%x\n", page, reg);
3466
3467 /* Write the Wakeup register page offset value using opcode 0x11 */
3468 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
3469 if (ret_val) {
3470 DEBUGOUT1("Could not write address opcode to page %d\n", page);
3471 return ret_val;
3472 }
3473
3474 if (read) {
3475 /* Read the Wakeup register page value using opcode 0x12 */
3476 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3477 data);
3478 } else {
3479 /* Write the Wakeup register page value using opcode 0x12 */
3480 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3481 *data);
3482 }
3483
3484 if (ret_val) {
3485 DEBUGOUT2("Could not access PHY reg %d.%d\n", page, reg);
3486 return ret_val;
3487 }
3488
3489 if (!page_set)
3490 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
3491
3492 return ret_val;
3493 }
3494
3495 /**
3496 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
3497 * @hw: pointer to the HW structure
3498 *
3499 * In the case of a PHY power down to save power, or to turn off link during a
3500 * driver unload, or wake on lan is not enabled, restore the link to previous
3501 * settings.
3502 **/
e1000_power_up_phy_copper(struct e1000_hw * hw)3503 void e1000_power_up_phy_copper(struct e1000_hw *hw)
3504 {
3505 u16 mii_reg = 0;
3506
3507 /* The PHY will retain its settings across a power down/up cycle */
3508 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3509 mii_reg &= ~MII_CR_POWER_DOWN;
3510 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3511 }
3512
3513 /**
3514 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
3515 * @hw: pointer to the HW structure
3516 *
3517 * In the case of a PHY power down to save power, or to turn off link during a
3518 * driver unload, or wake on lan is not enabled, restore the link to previous
3519 * settings.
3520 **/
e1000_power_down_phy_copper(struct e1000_hw * hw)3521 void e1000_power_down_phy_copper(struct e1000_hw *hw)
3522 {
3523 u16 mii_reg = 0;
3524
3525 /* The PHY will retain its settings across a power down/up cycle */
3526 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3527 mii_reg |= MII_CR_POWER_DOWN;
3528 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3529 msec_delay(1);
3530 }
3531
3532 /**
3533 * __e1000_read_phy_reg_hv - Read HV PHY register
3534 * @hw: pointer to the HW structure
3535 * @offset: register offset to be read
3536 * @data: pointer to the read data
3537 * @locked: semaphore has already been acquired or not
3538 * @page_set: BM_WUC_PAGE already set and access enabled
3539 *
3540 * Acquires semaphore, if necessary, then reads the PHY register at offset
3541 * and stores the retrieved information in data. Release any acquired
3542 * semaphore before exiting.
3543 **/
__e1000_read_phy_reg_hv(struct e1000_hw * hw,u32 offset,u16 * data,bool locked,bool page_set)3544 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
3545 bool locked, bool page_set)
3546 {
3547 s32 ret_val;
3548 u16 page = BM_PHY_REG_PAGE(offset);
3549 u16 reg = BM_PHY_REG_NUM(offset);
3550 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3551
3552 DEBUGFUNC("__e1000_read_phy_reg_hv");
3553
3554 if (!locked) {
3555 ret_val = hw->phy.ops.acquire(hw);
3556 if (ret_val)
3557 return ret_val;
3558 }
3559 /* Page 800 works differently than the rest so it has its own func */
3560 if (page == BM_WUC_PAGE) {
3561 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3562 true, page_set);
3563 goto out;
3564 }
3565
3566 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
3567 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3568 data, true);
3569 goto out;
3570 }
3571
3572 if (!page_set) {
3573 if (page == HV_INTC_FC_PAGE_START)
3574 page = 0;
3575
3576 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3577 /* Page is shifted left, PHY expects (page x 32) */
3578 ret_val = e1000_set_page_igp(hw,
3579 (page << IGP_PAGE_SHIFT));
3580
3581 hw->phy.addr = phy_addr;
3582
3583 if (ret_val)
3584 goto out;
3585 }
3586 }
3587
3588 DEBUGOUT3("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
3589 page << IGP_PAGE_SHIFT, reg);
3590
3591 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3592 data);
3593 out:
3594 if (!locked)
3595 hw->phy.ops.release(hw);
3596
3597 return ret_val;
3598 }
3599
3600 /**
3601 * e1000_read_phy_reg_hv - Read HV PHY register
3602 * @hw: pointer to the HW structure
3603 * @offset: register offset to be read
3604 * @data: pointer to the read data
3605 *
3606 * Acquires semaphore then reads the PHY register at offset and stores
3607 * the retrieved information in data. Release the acquired semaphore
3608 * before exiting.
3609 **/
e1000_read_phy_reg_hv(struct e1000_hw * hw,u32 offset,u16 * data)3610 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
3611 {
3612 return __e1000_read_phy_reg_hv(hw, offset, data, false, false);
3613 }
3614
3615 /**
3616 * e1000_read_phy_reg_hv_locked - Read HV PHY register
3617 * @hw: pointer to the HW structure
3618 * @offset: register offset to be read
3619 * @data: pointer to the read data
3620 *
3621 * Reads the PHY register at offset and stores the retrieved information
3622 * in data. Assumes semaphore already acquired.
3623 **/
e1000_read_phy_reg_hv_locked(struct e1000_hw * hw,u32 offset,u16 * data)3624 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
3625 {
3626 return __e1000_read_phy_reg_hv(hw, offset, data, true, false);
3627 }
3628
3629 /**
3630 * e1000_read_phy_reg_page_hv - Read HV PHY register
3631 * @hw: pointer to the HW structure
3632 * @offset: register offset to write to
3633 * @data: data to write at register offset
3634 *
3635 * Reads the PHY register at offset and stores the retrieved information
3636 * in data. Assumes semaphore already acquired and page already set.
3637 **/
e1000_read_phy_reg_page_hv(struct e1000_hw * hw,u32 offset,u16 * data)3638 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data)
3639 {
3640 return __e1000_read_phy_reg_hv(hw, offset, data, true, true);
3641 }
3642
3643 /**
3644 * __e1000_write_phy_reg_hv - Write HV PHY register
3645 * @hw: pointer to the HW structure
3646 * @offset: register offset to write to
3647 * @data: data to write at register offset
3648 * @locked: semaphore has already been acquired or not
3649 * @page_set: BM_WUC_PAGE already set and access enabled
3650 *
3651 * Acquires semaphore, if necessary, then writes the data to PHY register
3652 * at the offset. Release any acquired semaphores before exiting.
3653 **/
__e1000_write_phy_reg_hv(struct e1000_hw * hw,u32 offset,u16 data,bool locked,bool page_set)3654 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
3655 bool locked, bool page_set)
3656 {
3657 s32 ret_val;
3658 u16 page = BM_PHY_REG_PAGE(offset);
3659 u16 reg = BM_PHY_REG_NUM(offset);
3660 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3661
3662 DEBUGFUNC("__e1000_write_phy_reg_hv");
3663
3664 if (!locked) {
3665 ret_val = hw->phy.ops.acquire(hw);
3666 if (ret_val)
3667 return ret_val;
3668 }
3669 /* Page 800 works differently than the rest so it has its own func */
3670 if (page == BM_WUC_PAGE) {
3671 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3672 false, page_set);
3673 goto out;
3674 }
3675
3676 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
3677 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3678 &data, false);
3679 goto out;
3680 }
3681
3682 if (!page_set) {
3683 if (page == HV_INTC_FC_PAGE_START)
3684 page = 0;
3685
3686 /* Workaround MDIO accesses being disabled after entering IEEE
3687 * Power Down (when bit 11 of the PHY Control register is set)
3688 */
3689 if ((hw->phy.type == e1000_phy_82578) &&
3690 (hw->phy.revision >= 1) &&
3691 (hw->phy.addr == 2) &&
3692 !(MAX_PHY_REG_ADDRESS & reg) &&
3693 (data & (1 << 11))) {
3694 u16 data2 = 0x7EFF;
3695 ret_val = e1000_access_phy_debug_regs_hv(hw,
3696 (1 << 6) | 0x3,
3697 &data2, false);
3698 if (ret_val)
3699 goto out;
3700 }
3701
3702 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3703 /* Page is shifted left, PHY expects (page x 32) */
3704 ret_val = e1000_set_page_igp(hw,
3705 (page << IGP_PAGE_SHIFT));
3706
3707 hw->phy.addr = phy_addr;
3708
3709 if (ret_val)
3710 goto out;
3711 }
3712 }
3713
3714 DEBUGOUT3("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
3715 page << IGP_PAGE_SHIFT, reg);
3716
3717 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3718 data);
3719
3720 out:
3721 if (!locked)
3722 hw->phy.ops.release(hw);
3723
3724 return ret_val;
3725 }
3726
3727 /**
3728 * e1000_write_phy_reg_hv - Write HV PHY register
3729 * @hw: pointer to the HW structure
3730 * @offset: register offset to write to
3731 * @data: data to write at register offset
3732 *
3733 * Acquires semaphore then writes the data to PHY register at the offset.
3734 * Release the acquired semaphores before exiting.
3735 **/
e1000_write_phy_reg_hv(struct e1000_hw * hw,u32 offset,u16 data)3736 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
3737 {
3738 return __e1000_write_phy_reg_hv(hw, offset, data, false, false);
3739 }
3740
3741 /**
3742 * e1000_write_phy_reg_hv_locked - Write HV PHY register
3743 * @hw: pointer to the HW structure
3744 * @offset: register offset to write to
3745 * @data: data to write at register offset
3746 *
3747 * Writes the data to PHY register at the offset. Assumes semaphore
3748 * already acquired.
3749 **/
e1000_write_phy_reg_hv_locked(struct e1000_hw * hw,u32 offset,u16 data)3750 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
3751 {
3752 return __e1000_write_phy_reg_hv(hw, offset, data, true, false);
3753 }
3754
3755 /**
3756 * e1000_write_phy_reg_page_hv - Write HV PHY register
3757 * @hw: pointer to the HW structure
3758 * @offset: register offset to write to
3759 * @data: data to write at register offset
3760 *
3761 * Writes the data to PHY register at the offset. Assumes semaphore
3762 * already acquired and page already set.
3763 **/
e1000_write_phy_reg_page_hv(struct e1000_hw * hw,u32 offset,u16 data)3764 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data)
3765 {
3766 return __e1000_write_phy_reg_hv(hw, offset, data, true, true);
3767 }
3768
3769 /**
3770 * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page
3771 * @page: page to be accessed
3772 **/
e1000_get_phy_addr_for_hv_page(u32 page)3773 static u32 e1000_get_phy_addr_for_hv_page(u32 page)
3774 {
3775 u32 phy_addr = 2;
3776
3777 if (page >= HV_INTC_FC_PAGE_START)
3778 phy_addr = 1;
3779
3780 return phy_addr;
3781 }
3782
3783 /**
3784 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
3785 * @hw: pointer to the HW structure
3786 * @offset: register offset to be read or written
3787 * @data: pointer to the data to be read or written
3788 * @read: determines if operation is read or write
3789 *
3790 * Reads the PHY register at offset and stores the retreived information
3791 * in data. Assumes semaphore already acquired. Note that the procedure
3792 * to access these regs uses the address port and data port to read/write.
3793 * These accesses done with PHY address 2 and without using pages.
3794 **/
e1000_access_phy_debug_regs_hv(struct e1000_hw * hw,u32 offset,u16 * data,bool read)3795 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
3796 u16 *data, bool read)
3797 {
3798 s32 ret_val;
3799 u32 addr_reg;
3800 u32 data_reg;
3801
3802 DEBUGFUNC("e1000_access_phy_debug_regs_hv");
3803
3804 /* This takes care of the difference with desktop vs mobile phy */
3805 addr_reg = ((hw->phy.type == e1000_phy_82578) ?
3806 I82578_ADDR_REG : I82577_ADDR_REG);
3807 data_reg = addr_reg + 1;
3808
3809 /* All operations in this function are phy address 2 */
3810 hw->phy.addr = 2;
3811
3812 /* masking with 0x3F to remove the page from offset */
3813 ret_val = e1000_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3814 if (ret_val) {
3815 DEBUGOUT("Could not write the Address Offset port register\n");
3816 return ret_val;
3817 }
3818
3819 /* Read or write the data value next */
3820 if (read)
3821 ret_val = e1000_read_phy_reg_mdic(hw, data_reg, data);
3822 else
3823 ret_val = e1000_write_phy_reg_mdic(hw, data_reg, *data);
3824
3825 if (ret_val)
3826 DEBUGOUT("Could not access the Data port register\n");
3827
3828 return ret_val;
3829 }
3830
3831 /**
3832 * e1000_link_stall_workaround_hv - Si workaround
3833 * @hw: pointer to the HW structure
3834 *
3835 * This function works around a Si bug where the link partner can get
3836 * a link up indication before the PHY does. If small packets are sent
3837 * by the link partner they can be placed in the packet buffer without
3838 * being properly accounted for by the PHY and will stall preventing
3839 * further packets from being received. The workaround is to clear the
3840 * packet buffer after the PHY detects link up.
3841 **/
e1000_link_stall_workaround_hv(struct e1000_hw * hw)3842 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3843 {
3844 s32 ret_val = E1000_SUCCESS;
3845 u16 data;
3846
3847 DEBUGFUNC("e1000_link_stall_workaround_hv");
3848
3849 if (hw->phy.type != e1000_phy_82578)
3850 return E1000_SUCCESS;
3851
3852 /* Do not apply workaround if in PHY loopback bit 14 set */
3853 hw->phy.ops.read_reg(hw, PHY_CONTROL, &data);
3854 if (data & PHY_CONTROL_LB)
3855 return E1000_SUCCESS;
3856
3857 /* check if link is up and at 1Gbps */
3858 ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data);
3859 if (ret_val)
3860 return ret_val;
3861
3862 data &= (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3863 BM_CS_STATUS_SPEED_MASK);
3864
3865 if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3866 BM_CS_STATUS_SPEED_1000))
3867 return E1000_SUCCESS;
3868
3869 msec_delay(200);
3870
3871 /* flush the packets in the fifo buffer */
3872 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3873 (HV_MUX_DATA_CTRL_GEN_TO_MAC |
3874 HV_MUX_DATA_CTRL_FORCE_SPEED));
3875 if (ret_val)
3876 return ret_val;
3877
3878 return hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3879 HV_MUX_DATA_CTRL_GEN_TO_MAC);
3880 }
3881
3882 /**
3883 * e1000_check_polarity_82577 - Checks the polarity.
3884 * @hw: pointer to the HW structure
3885 *
3886 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3887 *
3888 * Polarity is determined based on the PHY specific status register.
3889 **/
e1000_check_polarity_82577(struct e1000_hw * hw)3890 s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3891 {
3892 struct e1000_phy_info *phy = &hw->phy;
3893 s32 ret_val;
3894 u16 data;
3895
3896 DEBUGFUNC("e1000_check_polarity_82577");
3897
3898 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3899
3900 if (!ret_val)
3901 phy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY)
3902 ? e1000_rev_polarity_reversed
3903 : e1000_rev_polarity_normal);
3904
3905 return ret_val;
3906 }
3907
3908 /**
3909 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3910 * @hw: pointer to the HW structure
3911 *
3912 * Calls the PHY setup function to force speed and duplex.
3913 **/
e1000_phy_force_speed_duplex_82577(struct e1000_hw * hw)3914 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3915 {
3916 struct e1000_phy_info *phy = &hw->phy;
3917 s32 ret_val;
3918 u16 phy_data;
3919 bool link;
3920
3921 DEBUGFUNC("e1000_phy_force_speed_duplex_82577");
3922
3923 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
3924 if (ret_val)
3925 return ret_val;
3926
3927 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
3928
3929 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
3930 if (ret_val)
3931 return ret_val;
3932
3933 usec_delay(1);
3934
3935 if (phy->autoneg_wait_to_complete) {
3936 DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n");
3937
3938 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3939 100000, &link);
3940 if (ret_val)
3941 return ret_val;
3942
3943 if (!link)
3944 DEBUGOUT("Link taking longer than expected.\n");
3945
3946 /* Try once more */
3947 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3948 100000, &link);
3949 }
3950
3951 return ret_val;
3952 }
3953
3954 /**
3955 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3956 * @hw: pointer to the HW structure
3957 *
3958 * Read PHY status to determine if link is up. If link is up, then
3959 * set/determine 10base-T extended distance and polarity correction. Read
3960 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3961 * determine on the cable length, local and remote receiver.
3962 **/
e1000_get_phy_info_82577(struct e1000_hw * hw)3963 s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3964 {
3965 struct e1000_phy_info *phy = &hw->phy;
3966 s32 ret_val;
3967 u16 data;
3968 bool link;
3969
3970 DEBUGFUNC("e1000_get_phy_info_82577");
3971
3972 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
3973 if (ret_val)
3974 return ret_val;
3975
3976 if (!link) {
3977 DEBUGOUT("Phy info is only valid if link is up\n");
3978 return -E1000_ERR_CONFIG;
3979 }
3980
3981 phy->polarity_correction = true;
3982
3983 ret_val = e1000_check_polarity_82577(hw);
3984 if (ret_val)
3985 return ret_val;
3986
3987 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3988 if (ret_val)
3989 return ret_val;
3990
3991 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX);
3992
3993 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
3994 I82577_PHY_STATUS2_SPEED_1000MBPS) {
3995 ret_val = hw->phy.ops.get_cable_length(hw);
3996 if (ret_val)
3997 return ret_val;
3998
3999 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
4000 if (ret_val)
4001 return ret_val;
4002
4003 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
4004 ? e1000_1000t_rx_status_ok
4005 : e1000_1000t_rx_status_not_ok;
4006
4007 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
4008 ? e1000_1000t_rx_status_ok
4009 : e1000_1000t_rx_status_not_ok;
4010 } else {
4011 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
4012 phy->local_rx = e1000_1000t_rx_status_undefined;
4013 phy->remote_rx = e1000_1000t_rx_status_undefined;
4014 }
4015
4016 return E1000_SUCCESS;
4017 }
4018
4019 /**
4020 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
4021 * @hw: pointer to the HW structure
4022 *
4023 * Reads the diagnostic status register and verifies result is valid before
4024 * placing it in the phy_cable_length field.
4025 **/
e1000_get_cable_length_82577(struct e1000_hw * hw)4026 s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
4027 {
4028 struct e1000_phy_info *phy = &hw->phy;
4029 s32 ret_val;
4030 u16 phy_data, length;
4031
4032 DEBUGFUNC("e1000_get_cable_length_82577");
4033
4034 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);
4035 if (ret_val)
4036 return ret_val;
4037
4038 length = ((phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
4039 I82577_DSTATUS_CABLE_LENGTH_SHIFT);
4040
4041 if (length == E1000_CABLE_LENGTH_UNDEFINED)
4042 return -E1000_ERR_PHY;
4043
4044 phy->cable_length = length;
4045
4046 return E1000_SUCCESS;
4047 }
4048
4049 /**
4050 * e1000_write_phy_reg_gs40g - Write GS40G PHY register
4051 * @hw: pointer to the HW structure
4052 * @offset: register offset to write to
4053 * @data: data to write at register offset
4054 *
4055 * Acquires semaphore, if necessary, then writes the data to PHY register
4056 * at the offset. Release any acquired semaphores before exiting.
4057 **/
e1000_write_phy_reg_gs40g(struct e1000_hw * hw,u32 offset,u16 data)4058 s32 e1000_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)
4059 {
4060 s32 ret_val;
4061 u16 page = offset >> GS40G_PAGE_SHIFT;
4062
4063 DEBUGFUNC("e1000_write_phy_reg_gs40g");
4064
4065 offset = offset & GS40G_OFFSET_MASK;
4066 ret_val = hw->phy.ops.acquire(hw);
4067 if (ret_val)
4068 return ret_val;
4069
4070 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
4071 if (ret_val)
4072 goto release;
4073 ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
4074
4075 release:
4076 hw->phy.ops.release(hw);
4077 return ret_val;
4078 }
4079
4080 /**
4081 * e1000_read_phy_reg_gs40g - Read GS40G PHY register
4082 * @hw: pointer to the HW structure
4083 * @offset: lower half is register offset to read to
4084 * upper half is page to use.
4085 * @data: data to read at register offset
4086 *
4087 * Acquires semaphore, if necessary, then reads the data in the PHY register
4088 * at the offset. Release any acquired semaphores before exiting.
4089 **/
e1000_read_phy_reg_gs40g(struct e1000_hw * hw,u32 offset,u16 * data)4090 s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)
4091 {
4092 s32 ret_val;
4093 u16 page = offset >> GS40G_PAGE_SHIFT;
4094
4095 DEBUGFUNC("e1000_read_phy_reg_gs40g");
4096
4097 offset = offset & GS40G_OFFSET_MASK;
4098 ret_val = hw->phy.ops.acquire(hw);
4099 if (ret_val)
4100 return ret_val;
4101
4102 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
4103 if (ret_val)
4104 goto release;
4105 ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
4106
4107 release:
4108 hw->phy.ops.release(hw);
4109 return ret_val;
4110 }
4111
4112 /**
4113 * e1000_read_phy_reg_mphy - Read mPHY control register
4114 * @hw: pointer to the HW structure
4115 * @address: address to be read
4116 * @data: pointer to the read data
4117 *
4118 * Reads the mPHY control register in the PHY at offset and stores the
4119 * information read to data.
4120 **/
e1000_read_phy_reg_mphy(struct e1000_hw * hw,u32 address,u32 * data)4121 s32 e1000_read_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 *data)
4122 {
4123 u32 mphy_ctrl = 0;
4124 bool locked = false;
4125 bool ready;
4126
4127 DEBUGFUNC("e1000_read_phy_reg_mphy");
4128
4129 /* Check if mPHY is ready to read/write operations */
4130 ready = e1000_is_mphy_ready(hw);
4131 if (!ready)
4132 return -E1000_ERR_PHY;
4133
4134 /* Check if mPHY access is disabled and enable it if so */
4135 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
4136 if (mphy_ctrl & E1000_MPHY_DIS_ACCESS) {
4137 locked = true;
4138 ready = e1000_is_mphy_ready(hw);
4139 if (!ready)
4140 return -E1000_ERR_PHY;
4141 mphy_ctrl |= E1000_MPHY_ENA_ACCESS;
4142 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4143 }
4144
4145 /* Set the address that we want to read */
4146 ready = e1000_is_mphy_ready(hw);
4147 if (!ready)
4148 return -E1000_ERR_PHY;
4149
4150 /* We mask address, because we want to use only current lane */
4151 mphy_ctrl = (mphy_ctrl & ~E1000_MPHY_ADDRESS_MASK &
4152 ~E1000_MPHY_ADDRESS_FNC_OVERRIDE) |
4153 (address & E1000_MPHY_ADDRESS_MASK);
4154 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4155
4156 /* Read data from the address */
4157 ready = e1000_is_mphy_ready(hw);
4158 if (!ready)
4159 return -E1000_ERR_PHY;
4160 *data = E1000_READ_REG(hw, E1000_MPHY_DATA);
4161
4162 /* Disable access to mPHY if it was originally disabled */
4163 if (locked)
4164 ready = e1000_is_mphy_ready(hw);
4165 if (!ready)
4166 return -E1000_ERR_PHY;
4167 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL,
4168 E1000_MPHY_DIS_ACCESS);
4169
4170 return E1000_SUCCESS;
4171 }
4172
4173 /**
4174 * e1000_write_phy_reg_mphy - Write mPHY control register
4175 * @hw: pointer to the HW structure
4176 * @address: address to write to
4177 * @data: data to write to register at offset
4178 * @line_override: used when we want to use different line than default one
4179 *
4180 * Writes data to mPHY control register.
4181 **/
e1000_write_phy_reg_mphy(struct e1000_hw * hw,u32 address,u32 data,bool line_override)4182 s32 e1000_write_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 data,
4183 bool line_override)
4184 {
4185 u32 mphy_ctrl = 0;
4186 bool locked = false;
4187 bool ready;
4188
4189 DEBUGFUNC("e1000_write_phy_reg_mphy");
4190
4191 /* Check if mPHY is ready to read/write operations */
4192 ready = e1000_is_mphy_ready(hw);
4193 if (!ready)
4194 return -E1000_ERR_PHY;
4195
4196 /* Check if mPHY access is disabled and enable it if so */
4197 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
4198 if (mphy_ctrl & E1000_MPHY_DIS_ACCESS) {
4199 locked = true;
4200 ready = e1000_is_mphy_ready(hw);
4201 if (!ready)
4202 return -E1000_ERR_PHY;
4203 mphy_ctrl |= E1000_MPHY_ENA_ACCESS;
4204 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4205 }
4206
4207 /* Set the address that we want to read */
4208 ready = e1000_is_mphy_ready(hw);
4209 if (!ready)
4210 return -E1000_ERR_PHY;
4211
4212 /* We mask address, because we want to use only current lane */
4213 if (line_override)
4214 mphy_ctrl |= E1000_MPHY_ADDRESS_FNC_OVERRIDE;
4215 else
4216 mphy_ctrl &= ~E1000_MPHY_ADDRESS_FNC_OVERRIDE;
4217 mphy_ctrl = (mphy_ctrl & ~E1000_MPHY_ADDRESS_MASK) |
4218 (address & E1000_MPHY_ADDRESS_MASK);
4219 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4220
4221 /* Read data from the address */
4222 ready = e1000_is_mphy_ready(hw);
4223 if (!ready)
4224 return -E1000_ERR_PHY;
4225 E1000_WRITE_REG(hw, E1000_MPHY_DATA, data);
4226
4227 /* Disable access to mPHY if it was originally disabled */
4228 if (locked)
4229 ready = e1000_is_mphy_ready(hw);
4230 if (!ready)
4231 return -E1000_ERR_PHY;
4232 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL,
4233 E1000_MPHY_DIS_ACCESS);
4234
4235 return E1000_SUCCESS;
4236 }
4237
4238 /**
4239 * e1000_is_mphy_ready - Check if mPHY control register is not busy
4240 * @hw: pointer to the HW structure
4241 *
4242 * Returns mPHY control register status.
4243 **/
e1000_is_mphy_ready(struct e1000_hw * hw)4244 bool e1000_is_mphy_ready(struct e1000_hw *hw)
4245 {
4246 u16 retry_count = 0;
4247 u32 mphy_ctrl = 0;
4248 bool ready = false;
4249
4250 while (retry_count < 2) {
4251 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
4252 if (mphy_ctrl & E1000_MPHY_BUSY) {
4253 usec_delay(20);
4254 retry_count++;
4255 continue;
4256 }
4257 ready = true;
4258 break;
4259 }
4260
4261 if (!ready)
4262 DEBUGOUT("ERROR READING mPHY control register, phy is busy.\n");
4263
4264 return ready;
4265 }
4266
4267 /**
4268 * __e1000_access_xmdio_reg - Read/write XMDIO register
4269 * @hw: pointer to the HW structure
4270 * @address: XMDIO address to program
4271 * @dev_addr: device address to program
4272 * @data: pointer to value to read/write from/to the XMDIO address
4273 * @read: boolean flag to indicate read or write
4274 **/
__e1000_access_xmdio_reg(struct e1000_hw * hw,u16 address,u8 dev_addr,u16 * data,bool read)4275 static s32 __e1000_access_xmdio_reg(struct e1000_hw *hw, u16 address,
4276 u8 dev_addr, u16 *data, bool read)
4277 {
4278 s32 ret_val;
4279
4280 DEBUGFUNC("__e1000_access_xmdio_reg");
4281
4282 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, dev_addr);
4283 if (ret_val)
4284 return ret_val;
4285
4286 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, address);
4287 if (ret_val)
4288 return ret_val;
4289
4290 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, E1000_MMDAC_FUNC_DATA |
4291 dev_addr);
4292 if (ret_val)
4293 return ret_val;
4294
4295 if (read)
4296 ret_val = hw->phy.ops.read_reg(hw, E1000_MMDAAD, data);
4297 else
4298 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, *data);
4299 if (ret_val)
4300 return ret_val;
4301
4302 /* Recalibrate the device back to 0 */
4303 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, 0);
4304 if (ret_val)
4305 return ret_val;
4306
4307 return ret_val;
4308 }
4309
4310 /**
4311 * e1000_read_xmdio_reg - Read XMDIO register
4312 * @hw: pointer to the HW structure
4313 * @addr: XMDIO address to program
4314 * @dev_addr: device address to program
4315 * @data: value to be read from the EMI address
4316 **/
e1000_read_xmdio_reg(struct e1000_hw * hw,u16 addr,u8 dev_addr,u16 * data)4317 s32 e1000_read_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 *data)
4318 {
4319 DEBUGFUNC("e1000_read_xmdio_reg");
4320
4321 return __e1000_access_xmdio_reg(hw, addr, dev_addr, data, true);
4322 }
4323
4324 /**
4325 * e1000_write_xmdio_reg - Write XMDIO register
4326 * @hw: pointer to the HW structure
4327 * @addr: XMDIO address to program
4328 * @dev_addr: device address to program
4329 * @data: value to be written to the XMDIO address
4330 **/
e1000_write_xmdio_reg(struct e1000_hw * hw,u16 addr,u8 dev_addr,u16 data)4331 s32 e1000_write_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 data)
4332 {
4333 DEBUGFUNC("e1000_write_xmdio_reg");
4334
4335 return __e1000_access_xmdio_reg(hw, addr, dev_addr, &data,
4336 false);
4337 }
4338