1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /******************************************************************************* 3 Copyright (C) 2007-2009 STMicroelectronics Ltd 4 5 6 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 7 *******************************************************************************/ 8 #ifndef __DWMAC1000_H__ 9 #define __DWMAC1000_H__ 10 11 #include <linux/phy.h> 12 #include "common.h" 13 14 #define GMAC_CONTROL 0x00000000 /* Configuration */ 15 #define GMAC_FRAME_FILTER 0x00000004 /* Frame Filter */ 16 #define GMAC_HASH_HIGH 0x00000008 /* Multicast Hash Table High */ 17 #define GMAC_HASH_LOW 0x0000000c /* Multicast Hash Table Low */ 18 #define GMAC_MII_ADDR 0x00000010 /* MII Address */ 19 #define GMAC_MII_DATA 0x00000014 /* MII Data */ 20 #define GMAC_FLOW_CTRL 0x00000018 /* Flow Control */ 21 #define GMAC_VLAN_TAG 0x0000001c /* VLAN Tag */ 22 #define GMAC_DEBUG 0x00000024 /* GMAC debug register */ 23 #define GMAC_WAKEUP_FILTER 0x00000028 /* Wake-up Frame Filter */ 24 25 #define GMAC_INT_STATUS 0x00000038 /* interrupt status register */ 26 #define GMAC_INT_STATUS_PMT BIT(3) 27 #define GMAC_INT_STATUS_MMCIS BIT(4) 28 #define GMAC_INT_STATUS_MMCRIS BIT(5) 29 #define GMAC_INT_STATUS_MMCTIS BIT(6) 30 #define GMAC_INT_STATUS_MMCCSUM BIT(7) 31 #define GMAC_INT_STATUS_TSTAMP BIT(9) 32 #define GMAC_INT_STATUS_LPIIS BIT(10) 33 34 /* interrupt mask register */ 35 #define GMAC_INT_MASK 0x0000003c 36 #define GMAC_INT_DISABLE_RGMII BIT(0) 37 #define GMAC_INT_DISABLE_PCSLINK BIT(1) 38 #define GMAC_INT_DISABLE_PCSAN BIT(2) 39 #define GMAC_INT_DISABLE_PMT BIT(3) 40 #define GMAC_INT_DISABLE_TIMESTAMP BIT(9) 41 #define GMAC_INT_DISABLE_PCS (GMAC_INT_DISABLE_RGMII | \ 42 GMAC_INT_DISABLE_PCSLINK | \ 43 GMAC_INT_DISABLE_PCSAN) 44 #define GMAC_INT_DEFAULT_MASK (GMAC_INT_DISABLE_TIMESTAMP | \ 45 GMAC_INT_DISABLE_PCS) 46 47 /* PMT Control and Status */ 48 #define GMAC_PMT 0x0000002c 49 enum power_event { 50 pointer_reset = 0x80000000, 51 global_unicast = 0x00000200, 52 wake_up_rx_frame = 0x00000040, 53 magic_frame = 0x00000020, 54 wake_up_frame_en = 0x00000004, 55 magic_pkt_en = 0x00000002, 56 power_down = 0x00000001, 57 }; 58 59 /* Energy Efficient Ethernet (EEE) 60 * 61 * LPI status, timer and control register offset 62 * For LPI control and status bit definitions, see common.h. 63 */ 64 #define LPI_CTRL_STATUS 0x0030 65 #define LPI_TIMER_CTRL 0x0034 66 67 /* GMAC HW ADDR regs */ 68 #define GMAC_ADDR_HIGH(reg) ((reg > 15) ? 0x00000800 + (reg - 16) * 8 : \ 69 0x00000040 + (reg * 8)) 70 #define GMAC_ADDR_LOW(reg) ((reg > 15) ? 0x00000804 + (reg - 16) * 8 : \ 71 0x00000044 + (reg * 8)) 72 #define GMAC_MAX_PERFECT_ADDRESSES 1 73 74 #define GMAC_PCS_BASE 0x000000c0 /* PCS register base */ 75 #define GMAC_RGSMIIIS 0x000000d8 /* RGMII/SMII status */ 76 77 /* SGMII/RGMII status register */ 78 #define GMAC_RGSMIIIS_LNKMODE BIT(0) 79 #define GMAC_RGSMIIIS_SPEED GENMASK(2, 1) 80 #define GMAC_RGSMIIIS_SPEED_SHIFT 1 81 #define GMAC_RGSMIIIS_LNKSTS BIT(3) 82 #define GMAC_RGSMIIIS_JABTO BIT(4) 83 #define GMAC_RGSMIIIS_FALSECARDET BIT(5) 84 #define GMAC_RGSMIIIS_SMIDRXS BIT(16) 85 /* LNKMOD */ 86 #define GMAC_RGSMIIIS_LNKMOD_MASK 0x1 87 /* LNKSPEED */ 88 #define GMAC_RGSMIIIS_SPEED_125 0x2 89 #define GMAC_RGSMIIIS_SPEED_25 0x1 90 #define GMAC_RGSMIIIS_SPEED_2_5 0x0 91 92 /* GMAC Configuration defines */ 93 #define GMAC_CONTROL_2K 0x08000000 /* IEEE 802.3as 2K packets */ 94 #define GMAC_CONTROL_TC 0x01000000 /* Transmit Conf. in RGMII/SGMII */ 95 #define GMAC_CONTROL_WD 0x00800000 /* Disable Watchdog on receive */ 96 #define GMAC_CONTROL_JD 0x00400000 /* Jabber disable */ 97 #define GMAC_CONTROL_BE 0x00200000 /* Frame Burst Enable */ 98 #define GMAC_CONTROL_JE 0x00100000 /* Jumbo frame */ 99 enum inter_frame_gap { 100 GMAC_CONTROL_IFG_88 = 0x00040000, 101 GMAC_CONTROL_IFG_80 = 0x00020000, 102 GMAC_CONTROL_IFG_40 = 0x000e0000, 103 }; 104 #define GMAC_CONTROL_DCRS 0x00010000 /* Disable carrier sense */ 105 #define GMAC_CONTROL_PS 0x00008000 /* Port Select 0:GMI 1:MII */ 106 #define GMAC_CONTROL_FES 0x00004000 /* Speed 0:10 1:100 */ 107 #define GMAC_CONTROL_DO 0x00002000 /* Disable Rx Own */ 108 #define GMAC_CONTROL_LM 0x00001000 /* Loop-back mode */ 109 #define GMAC_CONTROL_DM 0x00000800 /* Duplex Mode */ 110 #define GMAC_CONTROL_IPC 0x00000400 /* Checksum Offload */ 111 #define GMAC_CONTROL_DR 0x00000200 /* Disable Retry */ 112 #define GMAC_CONTROL_LUD 0x00000100 /* Link up/down */ 113 #define GMAC_CONTROL_ACS 0x00000080 /* Auto Pad/FCS Stripping */ 114 #define GMAC_CONTROL_DC 0x00000010 /* Deferral Check */ 115 #define GMAC_CONTROL_TE 0x00000008 /* Transmitter Enable */ 116 #define GMAC_CONTROL_RE 0x00000004 /* Receiver Enable */ 117 118 #define GMAC_CORE_INIT (GMAC_CONTROL_JD | GMAC_CONTROL_PS | \ 119 GMAC_CONTROL_BE | GMAC_CONTROL_DCRS) 120 121 /* GMAC Frame Filter defines */ 122 #define GMAC_FRAME_FILTER_PR 0x00000001 /* Promiscuous Mode */ 123 #define GMAC_FRAME_FILTER_HUC 0x00000002 /* Hash Unicast */ 124 #define GMAC_FRAME_FILTER_HMC 0x00000004 /* Hash Multicast */ 125 #define GMAC_FRAME_FILTER_DAIF 0x00000008 /* DA Inverse Filtering */ 126 #define GMAC_FRAME_FILTER_PM 0x00000010 /* Pass all multicast */ 127 #define GMAC_FRAME_FILTER_DBF 0x00000020 /* Disable Broadcast frames */ 128 #define GMAC_FRAME_FILTER_PCF 0x00000080 /* Pass Control frames */ 129 #define GMAC_FRAME_FILTER_SAIF 0x00000100 /* Inverse Filtering */ 130 #define GMAC_FRAME_FILTER_SAF 0x00000200 /* Source Address Filter */ 131 #define GMAC_FRAME_FILTER_HPF 0x00000400 /* Hash or perfect Filter */ 132 #define GMAC_FRAME_FILTER_RA 0x80000000 /* Receive all mode */ 133 /* GMII ADDR defines */ 134 #define GMAC_MII_ADDR_WRITE 0x00000002 /* MII Write */ 135 #define GMAC_MII_ADDR_BUSY 0x00000001 /* MII Busy */ 136 /* GMAC FLOW CTRL defines */ 137 #define GMAC_FLOW_CTRL_PT_MASK 0xffff0000 /* Pause Time Mask */ 138 #define GMAC_FLOW_CTRL_PT_SHIFT 16 139 #define GMAC_FLOW_CTRL_UP 0x00000008 /* Unicast pause frame enable */ 140 #define GMAC_FLOW_CTRL_RFE 0x00000004 /* Rx Flow Control Enable */ 141 #define GMAC_FLOW_CTRL_TFE 0x00000002 /* Tx Flow Control Enable */ 142 #define GMAC_FLOW_CTRL_FCB_BPA 0x00000001 /* Flow Control Busy ... */ 143 144 /* DEBUG Register defines */ 145 /* MTL TxStatus FIFO */ 146 #define GMAC_DEBUG_TXSTSFSTS BIT(25) /* MTL TxStatus FIFO Full Status */ 147 #define GMAC_DEBUG_TXFSTS BIT(24) /* MTL Tx FIFO Not Empty Status */ 148 #define GMAC_DEBUG_TWCSTS BIT(22) /* MTL Tx FIFO Write Controller */ 149 /* MTL Tx FIFO Read Controller Status */ 150 #define GMAC_DEBUG_TRCSTS_MASK GENMASK(21, 20) 151 #define GMAC_DEBUG_TRCSTS_SHIFT 20 152 #define GMAC_DEBUG_TRCSTS_IDLE 0 153 #define GMAC_DEBUG_TRCSTS_READ 1 154 #define GMAC_DEBUG_TRCSTS_TXW 2 155 #define GMAC_DEBUG_TRCSTS_WRITE 3 156 #define GMAC_DEBUG_TXPAUSED BIT(19) /* MAC Transmitter in PAUSE */ 157 /* MAC Transmit Frame Controller Status */ 158 #define GMAC_DEBUG_TFCSTS_MASK GENMASK(18, 17) 159 #define GMAC_DEBUG_TFCSTS_SHIFT 17 160 #define GMAC_DEBUG_TFCSTS_IDLE 0 161 #define GMAC_DEBUG_TFCSTS_WAIT 1 162 #define GMAC_DEBUG_TFCSTS_GEN_PAUSE 2 163 #define GMAC_DEBUG_TFCSTS_XFER 3 164 /* MAC GMII or MII Transmit Protocol Engine Status */ 165 #define GMAC_DEBUG_TPESTS BIT(16) 166 #define GMAC_DEBUG_RXFSTS_MASK GENMASK(9, 8) /* MTL Rx FIFO Fill-level */ 167 #define GMAC_DEBUG_RXFSTS_SHIFT 8 168 #define GMAC_DEBUG_RXFSTS_EMPTY 0 169 #define GMAC_DEBUG_RXFSTS_BT 1 170 #define GMAC_DEBUG_RXFSTS_AT 2 171 #define GMAC_DEBUG_RXFSTS_FULL 3 172 #define GMAC_DEBUG_RRCSTS_MASK GENMASK(6, 5) /* MTL Rx FIFO Read Controller */ 173 #define GMAC_DEBUG_RRCSTS_SHIFT 5 174 #define GMAC_DEBUG_RRCSTS_IDLE 0 175 #define GMAC_DEBUG_RRCSTS_RDATA 1 176 #define GMAC_DEBUG_RRCSTS_RSTAT 2 177 #define GMAC_DEBUG_RRCSTS_FLUSH 3 178 #define GMAC_DEBUG_RWCSTS BIT(4) /* MTL Rx FIFO Write Controller Active */ 179 /* MAC Receive Frame Controller FIFO Status */ 180 #define GMAC_DEBUG_RFCFCSTS_MASK GENMASK(2, 1) 181 #define GMAC_DEBUG_RFCFCSTS_SHIFT 1 182 /* MAC GMII or MII Receive Protocol Engine Status */ 183 #define GMAC_DEBUG_RPESTS BIT(0) 184 185 /*--- DMA BLOCK defines ---*/ 186 /* DMA Bus Mode register defines */ 187 #define DMA_BUS_MODE_DA 0x00000002 /* Arbitration scheme */ 188 #define DMA_BUS_MODE_DSL_MASK 0x0000007c /* Descriptor Skip Length */ 189 #define DMA_BUS_MODE_DSL_SHIFT 2 /* (in DWORDS) */ 190 /* Programmable burst length (passed thorugh platform)*/ 191 #define DMA_BUS_MODE_PBL_MASK 0x00003f00 /* Programmable Burst Len */ 192 #define DMA_BUS_MODE_PBL_SHIFT 8 193 #define DMA_BUS_MODE_ATDS 0x00000080 /* Alternate Descriptor Size */ 194 195 enum rx_tx_priority_ratio { 196 double_ratio = 0x00004000, /* 2:1 */ 197 triple_ratio = 0x00008000, /* 3:1 */ 198 quadruple_ratio = 0x0000c000, /* 4:1 */ 199 }; 200 201 #define DMA_BUS_MODE_FB 0x00010000 /* Fixed burst */ 202 #define DMA_BUS_MODE_MB 0x04000000 /* Mixed burst */ 203 #define DMA_BUS_MODE_RPBL_MASK 0x007e0000 /* Rx-Programmable Burst Len */ 204 #define DMA_BUS_MODE_RPBL_SHIFT 17 205 #define DMA_BUS_MODE_USP 0x00800000 206 #define DMA_BUS_MODE_MAXPBL 0x01000000 207 #define DMA_BUS_MODE_AAL 0x02000000 208 209 /* DMA CRS Control and Status Register Mapping */ 210 #define DMA_HOST_TX_DESC 0x00001048 /* Current Host Tx descriptor */ 211 #define DMA_HOST_RX_DESC 0x0000104c /* Current Host Rx descriptor */ 212 /* DMA Bus Mode register defines */ 213 #define DMA_BUS_PR_RATIO_MASK 0x0000c000 /* Rx/Tx priority ratio */ 214 #define DMA_BUS_PR_RATIO_SHIFT 14 215 #define DMA_BUS_FB 0x00010000 /* Fixed Burst */ 216 217 /* DMA operation mode defines (start/stop tx/rx are placed in common header)*/ 218 /* Disable Drop TCP/IP csum error */ 219 #define DMA_CONTROL_DT 0x04000000 220 #define DMA_CONTROL_RSF 0x02000000 /* Receive Store and Forward */ 221 #define DMA_CONTROL_DFF 0x01000000 /* Disaable flushing */ 222 /* Threshold for Activating the FC */ 223 enum rfa { 224 act_full_minus_1 = 0x00800000, 225 act_full_minus_2 = 0x00800200, 226 act_full_minus_3 = 0x00800400, 227 act_full_minus_4 = 0x00800600, 228 }; 229 /* Threshold for Deactivating the FC */ 230 enum rfd { 231 deac_full_minus_1 = 0x00400000, 232 deac_full_minus_2 = 0x00400800, 233 deac_full_minus_3 = 0x00401000, 234 deac_full_minus_4 = 0x00401800, 235 }; 236 #define DMA_CONTROL_TSF 0x00200000 /* Transmit Store and Forward */ 237 238 enum ttc_control { 239 DMA_CONTROL_TTC_64 = 0x00000000, 240 DMA_CONTROL_TTC_128 = 0x00004000, 241 DMA_CONTROL_TTC_192 = 0x00008000, 242 DMA_CONTROL_TTC_256 = 0x0000c000, 243 DMA_CONTROL_TTC_40 = 0x00010000, 244 DMA_CONTROL_TTC_32 = 0x00014000, 245 DMA_CONTROL_TTC_24 = 0x00018000, 246 DMA_CONTROL_TTC_16 = 0x0001c000, 247 }; 248 #define DMA_CONTROL_TC_TX_MASK 0xfffe3fff 249 250 #define DMA_CONTROL_EFC 0x00000100 251 #define DMA_CONTROL_FEF 0x00000080 252 #define DMA_CONTROL_FUF 0x00000040 253 254 /* Receive flow control activation field 255 * RFA field in DMA control register, bits 23,10:9 256 */ 257 #define DMA_CONTROL_RFA_MASK 0x00800600 258 259 /* Receive flow control deactivation field 260 * RFD field in DMA control register, bits 22,12:11 261 */ 262 #define DMA_CONTROL_RFD_MASK 0x00401800 263 264 /* RFD and RFA fields are encoded as follows 265 * 266 * Bit Field 267 * 0,00 - Full minus 1KB (only valid when rxfifo >= 4KB and EFC enabled) 268 * 0,01 - Full minus 2KB (only valid when rxfifo >= 4KB and EFC enabled) 269 * 0,10 - Full minus 3KB (only valid when rxfifo >= 4KB and EFC enabled) 270 * 0,11 - Full minus 4KB (only valid when rxfifo > 4KB and EFC enabled) 271 * 1,00 - Full minus 5KB (only valid when rxfifo > 8KB and EFC enabled) 272 * 1,01 - Full minus 6KB (only valid when rxfifo > 8KB and EFC enabled) 273 * 1,10 - Full minus 7KB (only valid when rxfifo > 8KB and EFC enabled) 274 * 1,11 - Reserved 275 * 276 * RFD should always be > RFA for a given FIFO size. RFD == RFA may work, 277 * but packet throughput performance may not be as expected. 278 * 279 * Be sure that bit 3 in GMAC Register 6 is set for Unicast Pause frame 280 * detection (IEEE Specification Requirement, Annex 31B, 31B.1, Pause 281 * Description). 282 * 283 * Be sure that DZPA (bit 7 in Flow Control Register, GMAC Register 6), 284 * is set to 0. This allows pause frames with a quanta of 0 to be sent 285 * as an XOFF message to the link peer. 286 */ 287 288 #define RFA_FULL_MINUS_1K 0x00000000 289 #define RFA_FULL_MINUS_2K 0x00000200 290 #define RFA_FULL_MINUS_3K 0x00000400 291 #define RFA_FULL_MINUS_4K 0x00000600 292 #define RFA_FULL_MINUS_5K 0x00800000 293 #define RFA_FULL_MINUS_6K 0x00800200 294 #define RFA_FULL_MINUS_7K 0x00800400 295 296 #define RFD_FULL_MINUS_1K 0x00000000 297 #define RFD_FULL_MINUS_2K 0x00000800 298 #define RFD_FULL_MINUS_3K 0x00001000 299 #define RFD_FULL_MINUS_4K 0x00001800 300 #define RFD_FULL_MINUS_5K 0x00400000 301 #define RFD_FULL_MINUS_6K 0x00400800 302 #define RFD_FULL_MINUS_7K 0x00401000 303 304 enum rtc_control { 305 DMA_CONTROL_RTC_64 = 0x00000000, 306 DMA_CONTROL_RTC_32 = 0x00000008, 307 DMA_CONTROL_RTC_96 = 0x00000010, 308 DMA_CONTROL_RTC_128 = 0x00000018, 309 }; 310 #define DMA_CONTROL_TC_RX_MASK 0xffffffe7 311 312 #define DMA_CONTROL_OSF 0x00000004 /* Operate on second frame */ 313 314 /* MMC registers offset */ 315 #define GMAC_MMC_CTRL 0x100 316 #define GMAC_MMC_RX_INTR 0x104 317 #define GMAC_MMC_TX_INTR 0x108 318 #define GMAC_MMC_RX_CSUM_OFFLOAD 0x208 319 #define GMAC_EXTHASH_BASE 0x500 320 321 /* PTP and timestamping registers */ 322 323 #define GMAC3_X_ATSNS GENMASK(29, 25) 324 #define GMAC3_X_ATSNS_SHIFT 25 325 326 #define GMAC_PTP_TCR_ATSFC BIT(24) 327 #define GMAC_PTP_TCR_ATSEN0 BIT(25) 328 329 #define GMAC3_X_TIMESTAMP_STATUS 0x28 330 #define GMAC_PTP_ATNR 0x30 331 #define GMAC_PTP_ATSR 0x34 332 333 extern const struct stmmac_dma_ops dwmac1000_dma_ops; 334 #endif /* __DWMAC1000_H__ */ 335